include/hw/cxl/cxl_device.h

   1 /*
   2  * QEMU CXL Devices
   3  *
   4  * Copyright (c) 2020 Intel
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef CXL_DEVICE_H
  11 #define CXL_DEVICE_H
  12
  13 #include "hw/cxl/cxl_component.h"
  14 #include "hw/pci/pci_device.h"
  15 #include "hw/register.h"
  16 #include "hw/cxl/cxl_events.h"
  17
  18 /*
  19  * The following is how a CXL device's Memory Device registers are laid out.
  20  * The only requirement from the spec is that the capabilities array and the
  21  * capability headers start at offset 0 and are contiguously packed. The headers
  22  * themselves provide offsets to the register fields. For this emulation, the
  23  * actual registers  * will start at offset 0x80 (m == 0x80). No secondary
  24  * mailbox is implemented which means that the offset of the start of the
  25  * mailbox payload (n) is given by
  26  * n = m + sizeof(mailbox registers) + sizeof(device registers).
  27  *
  28  *                       +---------------------------------+
  29  *                       |                                 |
  30  *                       |    Memory Device Registers      |
  31  *                       |                                 |
  32  * n + PAYLOAD_SIZE_MAX  -----------------------------------
  33  *                  ^    |                                 |
  34  *                  |    |                                 |
  35  *                  |    |                                 |
  36  *                  |    |                                 |
  37  *                  |    |                                 |
  38  *                  |    |         Mailbox Payload         |
  39  *                  |    |                                 |
  40  *                  |    |                                 |
  41  *                  |    |                                 |
  42  *                  n    -----------------------------------
  43  *                  ^    |       Mailbox Registers         |
  44  *                  |    |                                 |
  45  *                  |    -----------------------------------
  46  *                  |    |                                 |
  47  *                  |    |        Device Registers         |
  48  *                  |    |                                 |
  49  *                  m    ---------------------------------->
  50  *                  ^    |  Memory Device Capability Header|
  51  *                  |    -----------------------------------
  52  *                  |    |     Mailbox Capability Header   |
  53  *                  |    -----------------------------------
  54  *                  |    |     Device Capability Header    |
  55  *                  |    -----------------------------------
  56  *                  |    |     Device Cap Array Register   |
  57  *                  0    +---------------------------------+
  58  *
  59  */
  60
  61 /* CXL r3.1 Figure 8-12: CXL Device Registers */
  62 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10
  63 /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */
  64 #define CXL_DEVICE_CAP_REG_SIZE 0x10
  65
  66 /*
  67  * CXL r3.1 Section 8.2.8.2.1: CXL Device Capabilities +
  68  * CXL r3.1 Section 8.2.8.5: Memory Device Capabilities
  69  */
  70 #define CXL_DEVICE_CAPS_MAX 4
  71 #define CXL_CAPS_SIZE \
  72     (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */
  73
  74 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */
  75 /*
  76  * CXL r3.1 Section 8.2.8.3: Device Status Registers
  77  * As it is the only Device Status Register in CXL r3.1
  78  */
  79 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8
  80
  81 #define CXL_MAILBOX_REGISTERS_OFFSET \
  82     (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH)
  83 /* CXL r3.1 Figure 8-13: Mailbox Registers */
  84 #define CXL_MAILBOX_REGISTERS_SIZE 0x20
  85 #define CXL_MAILBOX_PAYLOAD_SHIFT 11
  86 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT)
  87 #define CXL_MAILBOX_REGISTERS_LENGTH \
  88     (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
  89
  90 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
  91     (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
  92 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
  93
  94 #define CXL_MMIO_SIZE                                                   \
  95     (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH +     \
  96      CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
  97
  98 /* CXL r3.1 Table 8-34: Command Return Codes */
  99 typedef enum {
 100     CXL_MBOX_SUCCESS = 0x0,
 101     CXL_MBOX_BG_STARTED = 0x1,
 102     CXL_MBOX_INVALID_INPUT = 0x2,
 103     CXL_MBOX_UNSUPPORTED = 0x3,
 104     CXL_MBOX_INTERNAL_ERROR = 0x4,
 105     CXL_MBOX_RETRY_REQUIRED = 0x5,
 106     CXL_MBOX_BUSY = 0x6,
 107     CXL_MBOX_MEDIA_DISABLED = 0x7,
 108     CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
 109     CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
 110     CXL_MBOX_FW_AUTH_FAILED = 0xa,
 111     CXL_MBOX_FW_INVALID_SLOT = 0xb,
 112     CXL_MBOX_FW_ROLLEDBACK = 0xc,
 113     CXL_MBOX_FW_REST_REQD = 0xd,
 114     CXL_MBOX_INVALID_HANDLE = 0xe,
 115     CXL_MBOX_INVALID_PA = 0xf,
 116     CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
 117     CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
 118     CXL_MBOX_ABORTED = 0x12,
 119     CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
 120     CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
 121     CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
 122     CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
 123     CXL_MBOX_INVALID_LOG = 0x17,
 124     CXL_MBOX_INTERRUPTED = 0x18,
 125     CXL_MBOX_UNSUPPORTED_FEATURE_VERSION = 0x19,
 126     CXL_MBOX_UNSUPPORTED_FEATURE_SELECTION_VALUE = 0x1a,
 127     CXL_MBOX_FEATURE_TRANSFER_IN_PROGRESS = 0x1b,
 128     CXL_MBOX_FEATURE_TRANSFER_OUT_OF_ORDER = 0x1c,
 129     CXL_MBOX_RESOURCES_EXHAUSTED = 0x1d,
 130     CXL_MBOX_INVALID_EXTENT_LIST = 0x1e,
 131     CXL_MBOX_TRANSFER_OUT_OF_ORDER = 0x1f,
 132     CXL_MBOX_REQUEST_ABORT_NOTSUP = 0x20,
 133     CXL_MBOX_MAX = 0x20
 134 } CXLRetCode;
 135
 136 typedef struct CXLCCI CXLCCI;
 137 typedef struct cxl_device_state CXLDeviceState;
 138 struct cxl_cmd;
 139 typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd,
 140                                      uint8_t *payload_in, size_t len_in,
 141                                      uint8_t *payload_out, size_t *len_out,
 142                                      CXLCCI *cci);
 143 struct cxl_cmd {
 144     const char *name;
 145     opcode_handler handler;
 146     ssize_t in;
 147     uint16_t effect; /* Reported in CEL */
 148 };
 149
 150 typedef struct CXLEvent {
 151     CXLEventRecordRaw data;
 152     QSIMPLEQ_ENTRY(CXLEvent) node;
 153 } CXLEvent;
 154
 155 typedef struct CXLEventLog {
 156     uint16_t next_handle;
 157     uint16_t overflow_err_count;
 158     uint64_t first_overflow_timestamp;
 159     uint64_t last_overflow_timestamp;
 160     bool irq_enabled;
 161     int irq_vec;
 162     QemuMutex lock;
 163     QSIMPLEQ_HEAD(, CXLEvent) events;
 164 } CXLEventLog;
 165
 166 typedef struct CXLCCI {
 167     struct cxl_cmd cxl_cmd_set[256][256];
 168     struct cel_log {
 169         uint16_t opcode;
 170         uint16_t effect;
 171     } cel_log[1 << 16];
 172     size_t cel_size;
 173
 174     /* background command handling (times in ms) */
 175     struct {
 176         uint16_t opcode;
 177         uint16_t complete_pct;
 178         uint16_t ret_code; /* Current value of retcode */
 179         uint64_t starttime;
 180         /* set by each bg cmd, cleared by the bg_timer when complete */
 181         uint64_t runtime;
 182         QEMUTimer *timer;
 183     } bg;
 184
 185     /* firmware update */
 186     struct {
 187         uint8_t active_slot;
 188         uint8_t staged_slot;
 189         bool slot[4];
 190         uint8_t curr_action;
 191         uint8_t curr_slot;
 192         /* handle partial transfers */
 193         bool transferring;
 194         size_t prev_offset;
 195         size_t prev_len;
 196         time_t last_partxfer;
 197     } fw;
 198
 199     size_t payload_max;
 200     /* Pointer to device hosting the CCI */
 201     DeviceState *d;
 202     /* Pointer to the device hosting the protocol conversion */
 203     DeviceState *intf;
 204 } CXLCCI;
 205
 206 typedef struct cxl_device_state {
 207     MemoryRegion device_registers;
 208
 209     /* CXL r3.1 Section 8.2.8.3: Device Status Registers */
 210     struct {
 211         MemoryRegion device;
 212         union {
 213             uint8_t dev_reg_state[CXL_DEVICE_STATUS_REGISTERS_LENGTH];
 214             uint16_t dev_reg_state16[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 2];
 215             uint32_t dev_reg_state32[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 4];
 216             uint64_t dev_reg_state64[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 8];
 217         };
 218         uint64_t event_status;
 219     };
 220     MemoryRegion memory_device;
 221     struct {
 222         MemoryRegion caps;
 223         union {
 224             uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4];
 225             uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8];
 226         };
 227     };
 228
 229     /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
 230     struct {
 231         MemoryRegion mailbox;
 232         uint16_t payload_size;
 233         uint8_t mbox_msi_n;
 234         union {
 235             uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
 236             uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
 237             uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4];
 238             uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8];
 239         };
 240     };
 241
 242     /* Stash the memory device status value */
 243     uint64_t memdev_status;
 244
 245     struct {
 246         bool set;
 247         uint64_t last_set;
 248         uint64_t host_set;
 249     } timestamp;
 250
 251     /* memory region size, HDM */
 252     uint64_t static_mem_size;
 253     uint64_t pmem_size;
 254     uint64_t vmem_size;
 255
 256     const struct cxl_cmd (*cxl_cmd_set)[256];
 257     CXLEventLog event_logs[CXL_EVENT_TYPE_MAX];
 258 } CXLDeviceState;
 259
 260 /* Initialize the register block for a device */
 261 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev,
 262                                     CXLCCI *cci);
 263
 264 typedef struct CXLType3Dev CXLType3Dev;
 265 typedef struct CSWMBCCIDev CSWMBCCIDev;
 266 /* Set up default values for the register block */
 267 void cxl_device_register_init_t3(CXLType3Dev *ct3d);
 268 void cxl_device_register_init_swcci(CSWMBCCIDev *sw);
 269
 270 /*
 271  * CXL r3.1 Section 8.2.8.1: CXL Device Capabilities Array Register
 272  * Documented as a 128 bit register, but 64 bit accesses and the second
 273  * 64 bits are currently reserved.
 274  */
 275 REG64(CXL_DEV_CAP_ARRAY, 0)
 276     FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
 277     FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
 278     FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
 279
 280 void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
 281                           bool available);
 282
 283 /*
 284  * Helper macro to initialize capability headers for CXL devices.
 285  *
 286  * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
 287  * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register
 288  * Interface, it says:
 289  * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
 290  * > is the maximum access size allowed for these registers. If this rule is not
 291  * > followed, the behavior is undefined.
 292  *
 293  * > To illustrate how the fields fit together, the layouts ... are shown as
 294  * > wider than a 64 bit register. Implementations are expected to use any size
 295  * > accesses for this information up to 64 bits without lost of functionality
 296  *
 297  * Here we've chosen to make it 4 dwords.
 298  */
 299 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset)  \
 300     REG32(CXL_DEV_##n##_CAP_HDR0, offset)                 \
 301         FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16)      \
 302         FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \
 303     REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4)             \
 304         FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32)  \
 305     REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8)             \
 306         FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32)
 307
 308 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET)
 309 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
 310                                                CXL_DEVICE_CAP_REG_SIZE)
 311 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
 312                                       CXL_DEVICE_CAP_HDR1_OFFSET +
 313                                           CXL_DEVICE_CAP_REG_SIZE * 2)
 314
 315 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max);
 316 void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf,
 317                                   DeviceState *d, size_t payload_max);
 318 void cxl_init_cci(CXLCCI *cci, size_t payload_max);
 319 void cxl_add_cci_commands(CXLCCI *cci, const struct cxl_cmd (*cxl_cmd_set)[256],
 320                           size_t payload_max);
 321 int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
 322                             size_t len_in, uint8_t *pl_in,
 323                             size_t *len_out, uint8_t *pl_out,
 324                             bool *bg_started);
 325 void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
 326                                            DeviceState *intf,
 327                                            size_t payload_max);
 328
 329 void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d,
 330                               DeviceState *intf, size_t payload_max);
 331
 332 #define cxl_device_cap_init(dstate, reg, cap_id, ver)                      \
 333     do {                                                                   \
 334         uint32_t *cap_hdrs = dstate->caps_reg_state32;                     \
 335         int which = R_CXL_DEV_##reg##_CAP_HDR0;                            \
 336         cap_hdrs[which] =                                                  \
 337             FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0,          \
 338                        CAP_ID, cap_id);                                    \
 339         cap_hdrs[which] = FIELD_DP32(                                      \
 340             cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, ver);  \
 341         cap_hdrs[which + 1] =                                              \
 342             FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1,      \
 343                        CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET);          \
 344         cap_hdrs[which + 2] =                                              \
 345             FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2,      \
 346                        CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH);          \
 347     } while (0)
 348
 349 /* CXL r3.2 Section 8.2.8.3.1: Event Status Register */
 350 #define CXL_DEVICE_STATUS_VERSION 2
 351 REG64(CXL_DEV_EVENT_STATUS, 0)
 352     FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32)
 353
 354 #define CXL_DEV_MAILBOX_VERSION 1
 355 /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */
 356 REG32(CXL_DEV_MAILBOX_CAP, 0)
 357     FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
 358     FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
 359     FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1)
 360     FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4)
 361     FIELD(CXL_DEV_MAILBOX_CAP, MBOX_READY_TIME, 11, 8)
 362     FIELD(CXL_DEV_MAILBOX_CAP, TYPE, 19, 4)
 363
 364 /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */
 365 REG32(CXL_DEV_MAILBOX_CTRL, 4)
 366     FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1)
 367     FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1)
 368     FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1)
 369
 370 /* CXL r3.1 Section 8.2.8.4.5: Command Register */
 371 REG64(CXL_DEV_MAILBOX_CMD, 8)
 372     FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8)
 373     FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8)
 374     FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20)
 375
 376 /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */
 377 REG64(CXL_DEV_MAILBOX_STS, 0x10)
 378     FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
 379     FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
 380     FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
 381
 382 /* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */
 383 REG64(CXL_DEV_BG_CMD_STS, 0x18)
 384     FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16)
 385     FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7)
 386     FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16)
 387     FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16)
 388
 389 /* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */
 390 REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
 391
 392 /* CXL r3.1 Section 8.2.8.4.1: Memory Device Status Registers */
 393 #define CXL_MEM_DEV_STATUS_VERSION 1
 394 REG64(CXL_MEM_DEV_STS, 0)
 395     FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1)
 396     FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1)
 397     FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2)
 398     FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
 399     FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
 400
 401 static inline void __toggle_media(CXLDeviceState *cxl_dstate, int val)
 402 {
 403     uint64_t dev_status_reg;
 404
 405     dev_status_reg = cxl_dstate->memdev_status;
 406     dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS,
 407                                 val);
 408     cxl_dstate->memdev_status = dev_status_reg;
 409 }
 410 #define cxl_dev_disable_media(cxlds)                    \
 411         do { __toggle_media((cxlds), 0x3); } while (0)
 412 #define cxl_dev_enable_media(cxlds)                     \
 413         do { __toggle_media((cxlds), 0x1); } while (0)
 414
 415 static inline bool cxl_dev_media_disabled(CXLDeviceState *cxl_dstate)
 416 {
 417     uint64_t dev_status_reg = cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS];
 418     return FIELD_EX64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS) == 0x3;
 419 }
 420 static inline bool scan_media_running(CXLCCI *cci)
 421 {
 422     return !!cci->bg.runtime && cci->bg.opcode == 0x4304;
 423 }
 424
 425 typedef struct CXLError {
 426     QTAILQ_ENTRY(CXLError) node;
 427     int type; /* Error code as per FE definition */
 428     uint32_t header[CXL_RAS_ERR_HEADER_NUM];
 429 } CXLError;
 430
 431 typedef QTAILQ_HEAD(, CXLError) CXLErrorList;
 432
 433 typedef struct CXLPoison {
 434     uint64_t start, length;
 435     uint8_t type;
 436 #define CXL_POISON_TYPE_EXTERNAL 0x1
 437 #define CXL_POISON_TYPE_INTERNAL 0x2
 438 #define CXL_POISON_TYPE_INJECTED 0x3
 439     QLIST_ENTRY(CXLPoison) node;
 440 } CXLPoison;
 441
 442 typedef QLIST_HEAD(, CXLPoison) CXLPoisonList;
 443 #define CXL_POISON_LIST_LIMIT 256
 444
 445 /* CXL memory device patrol scrub control attributes */
 446 typedef struct CXLMemPatrolScrubReadAttrs {
 447         uint8_t scrub_cycle_cap;
 448         uint16_t scrub_cycle;
 449         uint8_t scrub_flags;
 450 } QEMU_PACKED CXLMemPatrolScrubReadAttrs;
 451
 452 typedef struct CXLMemPatrolScrubWriteAttrs {
 453     uint8_t scrub_cycle_hr;
 454     uint8_t scrub_flags;
 455 } QEMU_PACKED CXLMemPatrolScrubWriteAttrs;
 456
 457 #define CXL_MEMDEV_PS_GET_FEATURE_VERSION    0x01
 458 #define CXL_MEMDEV_PS_SET_FEATURE_VERSION    0x01
 459 #define CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT    BIT(0)
 460 #define CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT    BIT(1)
 461 #define CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT    12
 462 #define CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT    1
 463 #define CXL_MEMDEV_PS_ENABLE_DEFAULT    0
 464
 465 /* CXL memory device DDR5 ECS control attributes */
 466 typedef struct CXLMemECSReadAttrs {
 467         uint8_t ecs_log_cap;
 468         uint8_t ecs_cap;
 469         uint16_t ecs_config;
 470         uint8_t ecs_flags;
 471 } QEMU_PACKED CXLMemECSReadAttrs;
 472
 473 typedef struct CXLMemECSWriteAttrs {
 474    uint8_t ecs_log_cap;
 475     uint16_t ecs_config;
 476 } QEMU_PACKED CXLMemECSWriteAttrs;
 477
 478 #define CXL_ECS_GET_FEATURE_VERSION    0x01
 479 #define CXL_ECS_SET_FEATURE_VERSION    0x01
 480 #define CXL_ECS_LOG_ENTRY_TYPE_DEFAULT    0x01
 481 #define CXL_ECS_REALTIME_REPORT_CAP_DEFAULT    1
 482 #define CXL_ECS_THRESHOLD_COUNT_DEFAULT    3 /* 3: 256, 4: 1024, 5: 4096 */
 483 #define CXL_ECS_MODE_DEFAULT    0
 484 #define CXL_ECS_NUM_MEDIA_FRUS   3 /* Default */
 485
 486 #define DCD_MAX_NUM_REGION 8
 487
 488 typedef struct CXLDCExtentRaw {
 489     uint64_t start_dpa;
 490     uint64_t len;
 491     uint8_t tag[0x10];
 492     uint16_t shared_seq;
 493     uint8_t rsvd[0x6];
 494 } QEMU_PACKED CXLDCExtentRaw;
 495
 496 typedef struct CXLDCExtent {
 497     uint64_t start_dpa;
 498     uint64_t len;
 499     uint8_t tag[0x10];
 500     uint16_t shared_seq;
 501     uint8_t rsvd[0x6];
 502
 503     QTAILQ_ENTRY(CXLDCExtent) node;
 504 } CXLDCExtent;
 505 typedef QTAILQ_HEAD(, CXLDCExtent) CXLDCExtentList;
 506
 507 typedef struct CXLDCExtentGroup {
 508     CXLDCExtentList list;
 509     QTAILQ_ENTRY(CXLDCExtentGroup) node;
 510 } CXLDCExtentGroup;
 511 typedef QTAILQ_HEAD(, CXLDCExtentGroup) CXLDCExtentGroupList;
 512
 513 typedef struct CXLDCRegion {
 514     uint64_t base;       /* aligned to 256*MiB */
 515     uint64_t decode_len; /* aligned to 256*MiB */
 516     uint64_t len;
 517     uint64_t block_size;
 518     uint32_t dsmadhandle;
 519     uint8_t flags;
 520     unsigned long *blk_bitmap;
 521 } CXLDCRegion;
 522
 523 typedef struct CXLSetFeatureInfo {
 524     QemuUUID uuid;
 525     uint8_t data_transfer_flag;
 526     bool data_saved_across_reset;
 527     uint16_t data_offset;
 528     size_t data_size;
 529 } CXLSetFeatureInfo;
 530
 531 struct CXLType3Dev {
 532     /* Private */
 533     PCIDevice parent_obj;
 534
 535     /* Properties */
 536     HostMemoryBackend *hostmem; /* deprecated */
 537     HostMemoryBackend *hostvmem;
 538     HostMemoryBackend *hostpmem;
 539     HostMemoryBackend *lsa;
 540     uint64_t sn;
 541
 542     /* State */
 543     AddressSpace hostvmem_as;
 544     AddressSpace hostpmem_as;
 545     CXLComponentState cxl_cstate;
 546     CXLDeviceState cxl_dstate;
 547     CXLCCI cci; /* Primary PCI mailbox CCI */
 548     /* Always initialized as no way to know if a VDM might show up */
 549     CXLCCI vdm_fm_owned_ld_mctp_cci;
 550     CXLCCI ld0_cci;
 551
 552     /* DOE */
 553     DOECap doe_cdat;
 554
 555     /* Error injection */
 556     CXLErrorList error_list;
 557
 558     /* Poison Injection - cache */
 559     CXLPoisonList poison_list;
 560     unsigned int poison_list_cnt;
 561     bool poison_list_overflowed;
 562     uint64_t poison_list_overflow_ts;
 563     /* Poison Injection - backup */
 564     CXLPoisonList poison_list_bkp;
 565     CXLPoisonList scan_media_results;
 566     bool scan_media_hasrun;
 567
 568     CXLSetFeatureInfo set_feat_info;
 569
 570     /* Patrol scrub control attributes */
 571     CXLMemPatrolScrubReadAttrs patrol_scrub_attrs;
 572     CXLMemPatrolScrubWriteAttrs patrol_scrub_wr_attrs;
 573     /* ECS control attributes */
 574     CXLMemECSReadAttrs ecs_attrs[CXL_ECS_NUM_MEDIA_FRUS];
 575     CXLMemECSWriteAttrs ecs_wr_attrs[CXL_ECS_NUM_MEDIA_FRUS];
 576
 577     struct dynamic_capacity {
 578         HostMemoryBackend *host_dc;
 579         AddressSpace host_dc_as;
 580         /*
 581          * total_capacity is equivalent to the dynamic capability
 582          * memory region size.
 583          */
 584         uint64_t total_capacity; /* 256M aligned */
 585         CXLDCExtentList extents;
 586         CXLDCExtentGroupList extents_pending;
 587         uint32_t total_extent_count;
 588         uint32_t ext_list_gen_seq;
 589
 590         uint8_t num_regions; /* 0-8 regions */
 591         CXLDCRegion regions[DCD_MAX_NUM_REGION];
 592     } dc;
 593 };
 594
 595 #define TYPE_CXL_TYPE3 "cxl-type3"
 596 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3)
 597
 598 struct CXLType3Class {
 599     /* Private */
 600     PCIDeviceClass parent_class;
 601
 602     /* public */
 603     uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
 604
 605     uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
 606                         uint64_t offset);
 607     void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
 608                     uint64_t offset);
 609     bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset,
 610                           uint8_t *data);
 611 };
 612
 613 struct CSWMBCCIDev {
 614     PCIDevice parent_obj;
 615     PCIDevice *target;
 616     CXLComponentState cxl_cstate;
 617     CXLDeviceState cxl_dstate;
 618     CXLCCI *cci;
 619 };
 620
 621 #define TYPE_CXL_SWITCH_MAILBOX_CCI "cxl-switch-mailbox-cci"
 622 OBJECT_DECLARE_TYPE(CSWMBCCIDev, CSWMBCCIClass, CXL_SWITCH_MAILBOX_CCI)
 623
 624 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
 625                            unsigned size, MemTxAttrs attrs);
 626 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
 627                             unsigned size, MemTxAttrs attrs);
 628
 629 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds);
 630
 631 void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num);
 632 bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogType log_type,
 633                       CXLEventRecordRaw *event);
 634 CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl,
 635                                  uint8_t log_type, int max_recs,
 636                                  size_t *len);
 637 CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds,
 638                                    CXLClearEventPayload *pl);
 639 void cxl_discard_all_event_records(CXLDeviceState *cxlds);
 640
 641 void cxl_event_irq_assert(CXLType3Dev *ct3d);
 642
 643 void cxl_set_poison_list_overflowed(CXLType3Dev *ct3d);
 644 void cxl_clear_poison_list_overflowed(CXLType3Dev *ct3d);
 645
 646 CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len);
 647
 648 void cxl_remove_extent_from_extent_list(CXLDCExtentList *list,
 649                                         CXLDCExtent *extent);
 650 void cxl_insert_extent_to_extent_list(CXLDCExtentList *list, uint64_t dpa,
 651                                       uint64_t len, uint8_t *tag,
 652                                       uint16_t shared_seq);
 653 bool test_any_bits_set(const unsigned long *addr, unsigned long nr,
 654                        unsigned long size);
 655 bool cxl_extents_contains_dpa_range(CXLDCExtentList *list,
 656                                     uint64_t dpa, uint64_t len);
 657 CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,
 658                                                     uint64_t dpa,
 659                                                     uint64_t len,
 660                                                     uint8_t *tag,
 661                                                     uint16_t shared_seq);
 662 void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list,
 663                                        CXLDCExtentGroup *group);
 664 void cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list);
 665 void ct3_set_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
 666                                  uint64_t len);
 667 void ct3_clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
 668                                    uint64_t len);
 669 bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa,
 670                                   uint64_t len);
 671 #endif