include/hw/misc/aspeed_sdmc.h

   1 /*
   2  * ASPEED SDRAM Memory Controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9 #ifndef ASPEED_SDMC_H
  10 #define ASPEED_SDMC_H
  11
  12 #include "hw/sysbus.h"
  13 #include "qom/object.h"
  14
  15 #define TYPE_ASPEED_SDMC "aspeed.sdmc"
  16 OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC)
  17 #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
  18 #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
  19 #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
  20 #define TYPE_ASPEED_2700_SDMC TYPE_ASPEED_SDMC "-ast2700"
  21
  22 /*
  23  * SDMC has 174 documented registers. In addition the u-boot device tree
  24  * describes the following regions:
  25  *  - PHY status regs at offset 0x400, length 0x200
  26  *  - PHY setting regs at offset 0x100, length 0x300
  27  *
  28  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
  29  * system: one is in the SDRAM MC (memory controller) which is used in run
  30  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
  31  * training.
  32  */
  33 #define ASPEED_SDMC_NR_REGS (0x1000 >> 2)
  34
  35 struct AspeedSDMCState {
  36     /*< private >*/
  37     SysBusDevice parent_obj;
  38
  39     /*< public >*/
  40     MemoryRegion iomem;
  41
  42     uint32_t regs[ASPEED_SDMC_NR_REGS];
  43     uint64_t ram_size;
  44     uint64_t max_ram_size;
  45     bool unlocked;
  46 };
  47
  48
  49 struct AspeedSDMCClass {
  50     SysBusDeviceClass parent_class;
  51
  52     uint64_t max_ram_size;
  53     const uint64_t *valid_ram_sizes;
  54     uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
  55     void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
  56     bool is_bus64bit;
  57 };
  58
  59 #endif /* ASPEED_SDMC_H */