include/hw/misc/imx7_src.h

   1 /*
   2  * IMX7 System Reset Controller
   3  *
   4  * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef IMX7_SRC_H
  11 #define IMX7_SRC_H
  12
  13 #include "hw/sysbus.h"
  14 #include "qemu/bitops.h"
  15 #include "qom/object.h"
  16
  17 #define SRC_SCR 0
  18 #define SRC_A7RCR0 1
  19 #define SRC_A7RCR1 2
  20 #define SRC_M4RCR 3
  21 #define SRC_ERCR 5
  22 #define SRC_HSICPHY_RCR 7
  23 #define SRC_USBOPHY1_RCR 8
  24 #define SRC_USBOPHY2_RCR 9
  25 #define SRC_MPIPHY_RCR 10
  26 #define SRC_PCIEPHY_RCR 11
  27 #define SRC_SBMR1 22
  28 #define SRC_SRSR 23
  29 #define SRC_SISR 26
  30 #define SRC_SIMR 27
  31 #define SRC_SBMR2 28
  32 #define SRC_GPR1 29
  33 #define SRC_GPR2 30
  34 #define SRC_GPR3 31
  35 #define SRC_GPR4 32
  36 #define SRC_GPR5 33
  37 #define SRC_GPR6 34
  38 #define SRC_GPR7 35
  39 #define SRC_GPR8 36
  40 #define SRC_GPR9 37
  41 #define SRC_GPR10 38
  42 #define SRC_MAX 39
  43
  44 /* SRC_A7SCR1 */
  45 #define R_CORE1_ENABLE_SHIFT     1
  46 #define R_CORE1_ENABLE_LENGTH    1
  47 /* SRC_A7SCR0 */
  48 #define R_CORE1_RST_SHIFT        5
  49 #define R_CORE1_RST_LENGTH       1
  50 #define R_CORE0_RST_SHIFT        4
  51 #define R_CORE0_RST_LENGTH       1
  52
  53 #define TYPE_IMX7_SRC "imx7.src"
  54 OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
  55
  56 struct IMX7SRCState {
  57     /* <private> */
  58     SysBusDevice parent_obj;
  59
  60     /* <public> */
  61     MemoryRegion iomem;
  62
  63     uint32_t regs[SRC_MAX];
  64 };
  65
  66 #endif /* IMX7_SRC_H */