include/hw/misc/xlnx-versal-cfu.h

   1 /*
   2  * QEMU model of the CFU Configuration Unit.
   3  *
   4  * Copyright (C) 2023, Advanced Micro Devices, Inc.
   5  *
   6  * Written by Francisco Iglesias <francisco.iglesias@amd.com>
   7  *
   8  * SPDX-License-Identifier: GPL-2.0-or-later
   9  *
  10  * References:
  11  * [1] Versal ACAP Technical Reference Manual,
  12  *     https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
  13  *
  14  * [2] Versal ACAP Register Reference,
  15  *     https://docs.xilinx.com/r/en-US/am012-versal-register-reference/CFU_CSR-Module
  16  */
  17 #ifndef HW_MISC_XLNX_VERSAL_CFU_APB_H
  18 #define HW_MISC_XLNX_VERSAL_CFU_APB_H
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/register.h"
  22 #include "hw/misc/xlnx-cfi-if.h"
  23 #include "qemu/fifo32.h"
  24
  25 #define TYPE_XLNX_VERSAL_CFU_APB "xlnx-versal-cfu-apb"
  26 OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUAPB, XLNX_VERSAL_CFU_APB)
  27
  28 #define TYPE_XLNX_VERSAL_CFU_FDRO "xlnx-versal-cfu-fdro"
  29 OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUFDRO, XLNX_VERSAL_CFU_FDRO)
  30
  31 #define TYPE_XLNX_VERSAL_CFU_SFR "xlnx-versal-cfu-sfr"
  32 OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFUSFR, XLNX_VERSAL_CFU_SFR)
  33
  34 REG32(CFU_ISR, 0x0)
  35     FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
  36     FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
  37     FIELD(CFU_ISR, SLVERR, 7, 1)
  38     FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
  39     FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
  40     FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
  41     FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
  42     FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
  43     FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
  44     FIELD(CFU_ISR, SEU_ENDOFCALIB, 0, 1)
  45 REG32(CFU_IMR, 0x4)
  46     FIELD(CFU_IMR, USR_GTS_EVENT, 9, 1)
  47     FIELD(CFU_IMR, USR_GSR_EVENT, 8, 1)
  48     FIELD(CFU_IMR, SLVERR, 7, 1)
  49     FIELD(CFU_IMR, DECOMP_ERROR, 6, 1)
  50     FIELD(CFU_IMR, BAD_CFI_PACKET, 5, 1)
  51     FIELD(CFU_IMR, AXI_ALIGN_ERROR, 4, 1)
  52     FIELD(CFU_IMR, CFI_ROW_ERROR, 3, 1)
  53     FIELD(CFU_IMR, CRC32_ERROR, 2, 1)
  54     FIELD(CFU_IMR, CRC8_ERROR, 1, 1)
  55     FIELD(CFU_IMR, SEU_ENDOFCALIB, 0, 1)
  56 REG32(CFU_IER, 0x8)
  57     FIELD(CFU_IER, USR_GTS_EVENT, 9, 1)
  58     FIELD(CFU_IER, USR_GSR_EVENT, 8, 1)
  59     FIELD(CFU_IER, SLVERR, 7, 1)
  60     FIELD(CFU_IER, DECOMP_ERROR, 6, 1)
  61     FIELD(CFU_IER, BAD_CFI_PACKET, 5, 1)
  62     FIELD(CFU_IER, AXI_ALIGN_ERROR, 4, 1)
  63     FIELD(CFU_IER, CFI_ROW_ERROR, 3, 1)
  64     FIELD(CFU_IER, CRC32_ERROR, 2, 1)
  65     FIELD(CFU_IER, CRC8_ERROR, 1, 1)
  66     FIELD(CFU_IER, SEU_ENDOFCALIB, 0, 1)
  67 REG32(CFU_IDR, 0xc)
  68     FIELD(CFU_IDR, USR_GTS_EVENT, 9, 1)
  69     FIELD(CFU_IDR, USR_GSR_EVENT, 8, 1)
  70     FIELD(CFU_IDR, SLVERR, 7, 1)
  71     FIELD(CFU_IDR, DECOMP_ERROR, 6, 1)
  72     FIELD(CFU_IDR, BAD_CFI_PACKET, 5, 1)
  73     FIELD(CFU_IDR, AXI_ALIGN_ERROR, 4, 1)
  74     FIELD(CFU_IDR, CFI_ROW_ERROR, 3, 1)
  75     FIELD(CFU_IDR, CRC32_ERROR, 2, 1)
  76     FIELD(CFU_IDR, CRC8_ERROR, 1, 1)
  77     FIELD(CFU_IDR, SEU_ENDOFCALIB, 0, 1)
  78 REG32(CFU_ITR, 0x10)
  79     FIELD(CFU_ITR, USR_GTS_EVENT, 9, 1)
  80     FIELD(CFU_ITR, USR_GSR_EVENT, 8, 1)
  81     FIELD(CFU_ITR, SLVERR, 7, 1)
  82     FIELD(CFU_ITR, DECOMP_ERROR, 6, 1)
  83     FIELD(CFU_ITR, BAD_CFI_PACKET, 5, 1)
  84     FIELD(CFU_ITR, AXI_ALIGN_ERROR, 4, 1)
  85     FIELD(CFU_ITR, CFI_ROW_ERROR, 3, 1)
  86     FIELD(CFU_ITR, CRC32_ERROR, 2, 1)
  87     FIELD(CFU_ITR, CRC8_ERROR, 1, 1)
  88     FIELD(CFU_ITR, SEU_ENDOFCALIB, 0, 1)
  89 REG32(CFU_PROTECT, 0x14)
  90     FIELD(CFU_PROTECT, ACTIVE, 0, 1)
  91 REG32(CFU_FGCR, 0x18)
  92     FIELD(CFU_FGCR, GCLK_CAL, 14, 1)
  93     FIELD(CFU_FGCR, SC_HBC_TRIGGER, 13, 1)
  94     FIELD(CFU_FGCR, GLOW, 12, 1)
  95     FIELD(CFU_FGCR, GPWRDWN, 11, 1)
  96     FIELD(CFU_FGCR, GCAP, 10, 1)
  97     FIELD(CFU_FGCR, GSCWE, 9, 1)
  98     FIELD(CFU_FGCR, GHIGH_B, 8, 1)
  99     FIELD(CFU_FGCR, GMC_B, 7, 1)
 100     FIELD(CFU_FGCR, GWE, 6, 1)
 101     FIELD(CFU_FGCR, GRESTORE, 5, 1)
 102     FIELD(CFU_FGCR, GTS_CFG_B, 4, 1)
 103     FIELD(CFU_FGCR, GLUTMASK, 3, 1)
 104     FIELD(CFU_FGCR, EN_GLOBS_B, 2, 1)
 105     FIELD(CFU_FGCR, EOS, 1, 1)
 106     FIELD(CFU_FGCR, INIT_COMPLETE, 0, 1)
 107 REG32(CFU_CTL, 0x1c)
 108     FIELD(CFU_CTL, GSR_GSC, 15, 1)
 109     FIELD(CFU_CTL, SLVERR_EN, 14, 1)
 110     FIELD(CFU_CTL, CRC32_RESET, 13, 1)
 111     FIELD(CFU_CTL, AXI_ERROR_EN, 12, 1)
 112     FIELD(CFU_CTL, FLUSH_AXI, 11, 1)
 113     FIELD(CFU_CTL, SSI_PER_SLR_PR, 10, 1)
 114     FIELD(CFU_CTL, GCAP_CLK_EN, 9, 1)
 115     FIELD(CFU_CTL, STATUS_SYNC_DISABLE, 8, 1)
 116     FIELD(CFU_CTL, IGNORE_CFI_ERROR, 7, 1)
 117     FIELD(CFU_CTL, CFRAME_DISABLE, 6, 1)
 118     FIELD(CFU_CTL, QWORD_CNT_RESET, 5, 1)
 119     FIELD(CFU_CTL, CRC8_DISABLE, 4, 1)
 120     FIELD(CFU_CTL, CRC32_CHECK, 3, 1)
 121     FIELD(CFU_CTL, DECOMPRESS, 2, 1)
 122     FIELD(CFU_CTL, SEU_GO, 1, 1)
 123     FIELD(CFU_CTL, CFI_LOCAL_RESET, 0, 1)
 124 REG32(CFU_CRAM_RW, 0x20)
 125     FIELD(CFU_CRAM_RW, RFIFO_AFULL_DEPTH, 18, 9)
 126     FIELD(CFU_CRAM_RW, RD_WAVE_CNT_LEFT, 12, 6)
 127     FIELD(CFU_CRAM_RW, RD_WAVE_CNT, 6, 6)
 128     FIELD(CFU_CRAM_RW, WR_WAVE_CNT, 0, 6)
 129 REG32(CFU_MASK, 0x28)
 130 REG32(CFU_CRC_EXPECT, 0x2c)
 131 REG32(CFU_CFRAME_LEFT_T0, 0x60)
 132     FIELD(CFU_CFRAME_LEFT_T0, NUM, 0, 20)
 133 REG32(CFU_CFRAME_LEFT_T1, 0x64)
 134     FIELD(CFU_CFRAME_LEFT_T1, NUM, 0, 20)
 135 REG32(CFU_CFRAME_LEFT_T2, 0x68)
 136     FIELD(CFU_CFRAME_LEFT_T2, NUM, 0, 20)
 137 REG32(CFU_ROW_RANGE, 0x6c)
 138     FIELD(CFU_ROW_RANGE, HALF_FSR, 5, 1)
 139     FIELD(CFU_ROW_RANGE, NUM, 0, 5)
 140 REG32(CFU_STATUS, 0x100)
 141     FIELD(CFU_STATUS, SEU_WRITE_ERROR, 30, 1)
 142     FIELD(CFU_STATUS, FRCNT_ERROR, 29, 1)
 143     FIELD(CFU_STATUS, RSVD_ERROR, 28, 1)
 144     FIELD(CFU_STATUS, FDRO_ERROR, 27, 1)
 145     FIELD(CFU_STATUS, FDRI_ERROR, 26, 1)
 146     FIELD(CFU_STATUS, FDRI_READ_ERROR, 25, 1)
 147     FIELD(CFU_STATUS, READ_FDRI_ERROR, 24, 1)
 148     FIELD(CFU_STATUS, READ_SFR_ERROR, 23, 1)
 149     FIELD(CFU_STATUS, READ_STREAM_ERROR, 22, 1)
 150     FIELD(CFU_STATUS, UNKNOWN_STREAM_PKT, 21, 1)
 151     FIELD(CFU_STATUS, USR_GTS, 20, 1)
 152     FIELD(CFU_STATUS, USR_GSR, 19, 1)
 153     FIELD(CFU_STATUS, AXI_BAD_WSTRB, 18, 1)
 154     FIELD(CFU_STATUS, AXI_BAD_AR_SIZE, 17, 1)
 155     FIELD(CFU_STATUS, AXI_BAD_AW_SIZE, 16, 1)
 156     FIELD(CFU_STATUS, AXI_BAD_ARADDR, 15, 1)
 157     FIELD(CFU_STATUS, AXI_BAD_AWADDR, 14, 1)
 158     FIELD(CFU_STATUS, SCAN_CLEAR_PASS, 13, 1)
 159     FIELD(CFU_STATUS, HC_SEC_ERROR, 12, 1)
 160     FIELD(CFU_STATUS, GHIGH_B_ISHIGH, 11, 1)
 161     FIELD(CFU_STATUS, GHIGH_B_ISLOW, 10, 1)
 162     FIELD(CFU_STATUS, GMC_B_ISHIGH, 9, 1)
 163     FIELD(CFU_STATUS, GMC_B_ISLOW, 8, 1)
 164     FIELD(CFU_STATUS, GPWRDWN_B_ISHIGH, 7, 1)
 165     FIELD(CFU_STATUS, CFI_SEU_CRC_ERROR, 6, 1)
 166     FIELD(CFU_STATUS, CFI_SEU_ECC_ERROR, 5, 1)
 167     FIELD(CFU_STATUS, CFI_SEU_HEARTBEAT, 4, 1)
 168     FIELD(CFU_STATUS, SCAN_CLEAR_DONE, 3, 1)
 169     FIELD(CFU_STATUS, HC_COMPLETE, 2, 1)
 170     FIELD(CFU_STATUS, CFI_CFRAME_BUSY, 1, 1)
 171     FIELD(CFU_STATUS, CFU_STREAM_BUSY, 0, 1)
 172 REG32(CFU_INTERNAL_STATUS, 0x104)
 173     FIELD(CFU_INTERNAL_STATUS, SSI_EOS, 22, 1)
 174     FIELD(CFU_INTERNAL_STATUS, SSI_GWE, 21, 1)
 175     FIELD(CFU_INTERNAL_STATUS, RFIFO_EMPTY, 20, 1)
 176     FIELD(CFU_INTERNAL_STATUS, RFIFO_FULL, 19, 1)
 177     FIELD(CFU_INTERNAL_STATUS, SEL_SFR, 18, 1)
 178     FIELD(CFU_INTERNAL_STATUS, STREAM_CFRAME, 17, 1)
 179     FIELD(CFU_INTERNAL_STATUS, FDRI_PHASE, 16, 1)
 180     FIELD(CFU_INTERNAL_STATUS, CFI_PIPE_EN, 15, 1)
 181     FIELD(CFU_INTERNAL_STATUS, AWFIFO_DCNT, 10, 5)
 182     FIELD(CFU_INTERNAL_STATUS, WFIFO_DCNT, 5, 5)
 183     FIELD(CFU_INTERNAL_STATUS, REPAIR_BUSY, 4, 1)
 184     FIELD(CFU_INTERNAL_STATUS, TRIMU_BUSY, 3, 1)
 185     FIELD(CFU_INTERNAL_STATUS, TRIMB_BUSY, 2, 1)
 186     FIELD(CFU_INTERNAL_STATUS, HCLEANR_BUSY, 1, 1)
 187     FIELD(CFU_INTERNAL_STATUS, HCLEAN_BUSY, 0, 1)
 188 REG32(CFU_QWORD_CNT, 0x108)
 189 REG32(CFU_CRC_LIVE, 0x10c)
 190 REG32(CFU_PENDING_READ_CNT, 0x110)
 191     FIELD(CFU_PENDING_READ_CNT, NUM, 0, 25)
 192 REG32(CFU_FDRI_CNT, 0x114)
 193 REG32(CFU_ECO1, 0x118)
 194 REG32(CFU_ECO2, 0x11c)
 195
 196 #define R_MAX (R_CFU_ECO2 + 1)
 197
 198 #define NUM_STREAM 2
 199 #define WFIFO_SZ 4
 200
 201 struct XlnxVersalCFUAPB {
 202     SysBusDevice parent_obj;
 203     MemoryRegion iomem;
 204     MemoryRegion iomem_stream[NUM_STREAM];
 205     qemu_irq irq_cfu_imr;
 206
 207     /* 128-bit wfifo.  */
 208     uint32_t wfifo[WFIFO_SZ];
 209
 210     uint32_t regs[R_MAX];
 211     RegisterInfo regs_info[R_MAX];
 212
 213     uint8_t fdri_row_addr;
 214
 215     struct {
 216         XlnxCfiIf *cframe[15];
 217     } cfg;
 218 };
 219
 220
 221 struct XlnxVersalCFUFDRO {
 222     SysBusDevice parent_obj;
 223     MemoryRegion iomem_fdro;
 224
 225     Fifo32 fdro_data;
 226 };
 227
 228 struct XlnxVersalCFUSFR {
 229     SysBusDevice parent_obj;
 230     MemoryRegion iomem_sfr;
 231
 232     /* 128-bit wfifo. */
 233     uint32_t wfifo[WFIFO_SZ];
 234
 235     struct {
 236         XlnxVersalCFUAPB *cfu;
 237     } cfg;
 238 };
 239
 240 /**
 241  * This is a helper function for updating a CFI data write fifo, an array of 4
 242  * uint32_t and 128 bits of data that are allowed to be written through 4
 243  * sequential 32 bit accesses. After the last index has been written into the
 244  * write fifo (wfifo), the data is copied to and returned in a secondary fifo
 245  * provided to the function (wfifo_ret), and the write fifo is cleared
 246  * (zeroized).
 247  *
 248  * @addr: the address used when calculating the wfifo array index to update
 249  * @value: the value to write into the wfifo array
 250  * @wfifo: the wfifo to update
 251  * @wfifo_out: will return the wfifo data when all 128 bits have been written
 252  *
 253  * @return: true if all 128 bits have been updated.
 254  */
 255 bool update_wfifo(hwaddr addr, uint64_t value,
 256                   uint32_t *wfifo, uint32_t *wfifo_ret);
 257
 258 #endif