include/hw/pci-host/designware.h

   1 /*
   2  * Copyright (c) 2017, Impinj, Inc.
   3  *
   4  * Designware PCIe IP block emulation
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef DESIGNWARE_H
  22 #define DESIGNWARE_H
  23
  24 #include "hw/sysbus.h"
  25 #include "hw/pci/pci_bridge.h"
  26 #include "qom/object.h"
  27
  28 #define TYPE_DESIGNWARE_PCIE_HOST "designware-pcie-host"
  29 OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST)
  30
  31 #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root"
  32 OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT)
  33
  34 typedef struct DesignwarePCIEViewport {
  35     DesignwarePCIERoot *root;
  36
  37     MemoryRegion cfg;
  38     MemoryRegion mem;
  39
  40     uint64_t base;
  41     uint64_t target;
  42     uint32_t limit;
  43     uint32_t cr[2];
  44
  45     bool inbound;
  46 } DesignwarePCIEViewport;
  47
  48 typedef struct DesignwarePCIEMSIBank {
  49     uint32_t enable;
  50     uint32_t mask;
  51     uint32_t status;
  52 } DesignwarePCIEMSIBank;
  53
  54 typedef struct DesignwarePCIEMSI {
  55     uint64_t     base;
  56     MemoryRegion iomem;
  57
  58 #define DESIGNWARE_PCIE_NUM_MSI_BANKS        1
  59
  60     DesignwarePCIEMSIBank intr[DESIGNWARE_PCIE_NUM_MSI_BANKS];
  61 } DesignwarePCIEMSI;
  62
  63 struct DesignwarePCIERoot {
  64     PCIBridge parent_obj;
  65
  66     uint32_t atu_viewport;
  67
  68 #define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND    0
  69 #define DESIGNWARE_PCIE_VIEWPORT_INBOUND     1
  70 #define DESIGNWARE_PCIE_NUM_VIEWPORTS        4
  71
  72     DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS];
  73     DesignwarePCIEMSI msi;
  74 };
  75
  76 struct DesignwarePCIEHost {
  77     PCIHostState parent_obj;
  78
  79     DesignwarePCIERoot root;
  80
  81     struct {
  82         AddressSpace address_space;
  83         MemoryRegion address_space_root;
  84
  85         MemoryRegion memory;
  86         MemoryRegion io;
  87
  88         qemu_irq     irqs[4];
  89     } pci;
  90
  91     MemoryRegion mmio;
  92 };
  93
  94 #endif /* DESIGNWARE_H */