include/hw/pci-host/pnv_phb4.h

   1 /*
   2  * QEMU PowerPC PowerNV (POWER9) PHB4 model
   3  *
   4  * Copyright (c) 2018-2020, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef PCI_HOST_PNV_PHB4_H
  11 #define PCI_HOST_PNV_PHB4_H
  12
  13 #include "hw/pci-host/pnv_phb.h"
  14 #include "hw/pci/pci_bus.h"
  15 #include "hw/ppc/pnv.h"
  16 #include "hw/ppc/xive.h"
  17 #include "qom/object.h"
  18
  19 typedef struct PnvPhb4PecStack PnvPhb4PecStack;
  20 typedef struct PnvPHB4 PnvPHB4;
  21
  22 /*
  23  * We have one such address space wrapper per possible device under
  24  * the PHB since they need to be assigned statically at qemu device
  25  * creation time. The relationship to a PE is done later
  26  * dynamically. This means we can potentially create a lot of these
  27  * guys. Q35 stores them as some kind of radix tree but we never
  28  * really need to do fast lookups so instead we simply keep a QLIST of
  29  * them for now, we can add the radix if needed later on.
  30  *
  31  * We do cache the PE number to speed things up a bit though.
  32  */
  33 typedef struct PnvPhb4DMASpace {
  34     PCIBus *bus;
  35     uint8_t devfn;
  36     int pe_num;         /* Cached PE number */
  37 #define PHB_INVALID_PE (-1)
  38     PnvPHB4 *phb;
  39     AddressSpace dma_as;
  40     IOMMUMemoryRegion dma_mr;
  41     MemoryRegion msi32_mr;
  42     MemoryRegion msi64_mr;
  43     QLIST_ENTRY(PnvPhb4DMASpace) list;
  44 } PnvPhb4DMASpace;
  45
  46 /*
  47  * PHB4 PCIe Root Bus
  48  */
  49 #define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
  50 struct PnvPHB4RootBus {
  51     PCIBus parent;
  52
  53     uint32_t chip_id;
  54     uint32_t phb_id;
  55 };
  56 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_BUS)
  57
  58 /*
  59  * PHB4 PCIe Host Bridge for PowerNV machines (POWER9)
  60  */
  61 #define TYPE_PNV_PHB4 "pnv-phb4"
  62 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4)
  63
  64 #define PNV_PHB4_MAX_LSIs          8
  65 #define PNV_PHB4_MAX_INTs          4096
  66 #define PNV_PHB4_MAX_MIST          (PNV_PHB4_MAX_INTs >> 2)
  67 #define PNV_PHB4_MAX_MMIO_WINDOWS  32
  68 #define PNV_PHB4_MIN_MMIO_WINDOWS  16
  69 #define PNV_PHB4_NUM_REGS          (0x3000 >> 3)
  70 #define PNV_PHB4_MAX_PEs           512
  71 #define PNV_PHB4_MAX_TVEs          (PNV_PHB4_MAX_PEs * 2)
  72 #define PNV_PHB4_MAX_PEEVs         (PNV_PHB4_MAX_PEs / 64)
  73 #define PNV_PHB4_MAX_MBEs          (PNV_PHB4_MAX_MMIO_WINDOWS * 2)
  74
  75 #define PNV_PHB4_VERSION           0x000000a400000002ull
  76 #define PNV_PHB4_DEVICE_ID         0x04c1
  77
  78 #define PCI_MMIO_TOTAL_SIZE        (0x1ull << 60)
  79
  80 struct PnvPHB4 {
  81     DeviceState parent;
  82
  83     PnvPHB *phb_base;
  84
  85     uint32_t chip_id;
  86     uint32_t phb_id;
  87
  88     /* The owner PEC */
  89     PnvPhb4PecState *pec;
  90
  91     char bus_path[8];
  92
  93     /* Main register images */
  94     uint64_t regs[PNV_PHB4_NUM_REGS];
  95     MemoryRegion mr_regs;
  96
  97     /* Extra SCOM-only register */
  98     uint64_t scom_hv_ind_addr_reg;
  99
 100     /*
 101      * Geometry of the PHB. There are two types, small and big PHBs, a
 102      * number of resources (number of PEs, windows etc...) are doubled
 103      * for a big PHB
 104      */
 105     bool big_phb;
 106
 107     /* Memory regions for MMIO space */
 108     MemoryRegion mr_mmio[PNV_PHB4_MAX_MMIO_WINDOWS];
 109
 110     /* PCI side space */
 111     MemoryRegion pci_mmio;
 112     MemoryRegion pci_io;
 113
 114     /* PCI registers (excluding pass-through) */
 115 #define PHB4_PEC_PCI_STK_REGS_COUNT  0xf
 116     uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT];
 117     MemoryRegion pci_regs_mr;
 118
 119     /* Nest registers */
 120 #define PHB4_PEC_NEST_STK_REGS_COUNT  0x18
 121     uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT];
 122     MemoryRegion nest_regs_mr;
 123
 124     /* PHB pass-through XSCOM */
 125     MemoryRegion phb_regs_mr;
 126
 127     /* Memory windows from PowerBus to PHB */
 128     MemoryRegion phbbar;
 129     MemoryRegion intbar;
 130     MemoryRegion mmbar0;
 131     MemoryRegion mmbar1;
 132     uint64_t mmio0_base;
 133     uint64_t mmio0_size;
 134     uint64_t mmio1_base;
 135     uint64_t mmio1_size;
 136
 137     /* On-chip IODA tables */
 138     uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs];
 139     uint64_t ioda_MIST[PNV_PHB4_MAX_MIST];
 140     uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs];
 141     uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs];
 142     uint64_t ioda_MDT[PNV_PHB4_MAX_PEs];
 143     uint64_t ioda_PEEV[PNV_PHB4_MAX_PEEVs];
 144
 145     /*
 146      * The internal PESTA/B is 2 bits per PE split into two tables, we
 147      * store them in a single array here to avoid wasting space.
 148      */
 149     uint8_t  ioda_PEST_AB[PNV_PHB4_MAX_PEs];
 150
 151     /* P9 Interrupt generation */
 152     XiveSource xsrc;
 153     qemu_irq *qirqs;
 154
 155     QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces;
 156 };
 157
 158 void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf);
 159 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
 160 PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);
 161 void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);
 162 extern const MemoryRegionOps pnv_phb4_xscom_ops;
 163
 164 /*
 165  * PHB4 PEC (PCI Express Controller)
 166  */
 167 #define TYPE_PNV_PHB4_PEC "pnv-phb4-pec"
 168 OBJECT_DECLARE_TYPE(PnvPhb4PecState, PnvPhb4PecClass, PNV_PHB4_PEC)
 169
 170 struct PnvPhb4PecState {
 171     DeviceState parent;
 172
 173     /* PEC number in chip */
 174     uint32_t index;
 175     uint32_t chip_id;
 176
 177     /* Nest registers, excuding per-stack */
 178 #define PHB4_PEC_NEST_REGS_COUNT    0xf
 179     uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT];
 180     MemoryRegion nest_regs_mr;
 181
 182     /* PCI registers, excluding per-stack */
 183 #define PHB4_PEC_PCI_REGS_COUNT     0x3
 184     uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT];
 185     MemoryRegion pci_regs_mr;
 186
 187     /* PHBs */
 188     uint32_t num_phbs;
 189 #define MAX_PHBS_PER_PEC        3
 190     PnvPHB *phbs[MAX_PHBS_PER_PEC];
 191
 192     PnvChip *chip;
 193 };
 194
 195
 196 struct PnvPhb4PecClass {
 197     DeviceClass parent_class;
 198
 199     uint32_t (*xscom_nest_base)(PnvPhb4PecState *pec);
 200     uint32_t xscom_nest_size;
 201     uint32_t (*xscom_pci_base)(PnvPhb4PecState *pec);
 202     uint32_t xscom_pci_size;
 203     const char *compat;
 204     int compat_size;
 205     const char *stk_compat;
 206     int stk_compat_size;
 207     uint64_t version;
 208     const char *phb_type;
 209     const uint32_t *num_phbs;
 210 };
 211
 212 /*
 213  * POWER10 definitions
 214  */
 215
 216 #define TYPE_PNV_PHB5 "pnv-phb5"
 217 #define PNV_PHB5(obj) \
 218     OBJECT_CHECK(PnvPhb4, (obj), TYPE_PNV_PHB5)
 219
 220 #define PNV_PHB5_VERSION           0x000000a500000002ull
 221
 222 #define TYPE_PNV_PHB5_PEC "pnv-phb5-pec"
 223 #define PNV_PHB5_PEC(obj) \
 224     OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC)
 225
 226 #endif /* PCI_HOST_PNV_PHB4_H */