include/hw/pci-host/q35.h

   1 /*
   2  * q35.h
   3  *
   4  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see <http://www.gnu.org/licenses/>
  20  */
  21
  22 #ifndef HW_Q35_H
  23 #define HW_Q35_H
  24
  25 #include "hw/pci/pci_device.h"
  26 #include "hw/pci/pcie_host.h"
  27 #include "hw/pci-host/pam.h"
  28 #include "qemu/units.h"
  29 #include "qemu/range.h"
  30 #include "qom/object.h"
  31
  32 #define TYPE_Q35_HOST_DEVICE "q35-pcihost"
  33 OBJECT_DECLARE_SIMPLE_TYPE(Q35PCIHost, Q35_HOST_DEVICE)
  34
  35 #define TYPE_MCH_PCI_DEVICE "mch"
  36 OBJECT_DECLARE_SIMPLE_TYPE(MCHPCIState, MCH_PCI_DEVICE)
  37
  38 struct MCHPCIState {
  39     /*< private >*/
  40     PCIDevice parent_obj;
  41     /*< public >*/
  42
  43     MemoryRegion *ram_memory;
  44     MemoryRegion *pci_address_space;
  45     MemoryRegion *system_memory;
  46     MemoryRegion *address_space_io;
  47     PAMMemoryRegion pam_regions[PAM_REGIONS_COUNT];
  48     MemoryRegion smram_region, open_high_smram;
  49     MemoryRegion smram, low_smram, high_smram;
  50     MemoryRegion tseg_blackhole, tseg_window;
  51     MemoryRegion smbase_blackhole, smbase_window;
  52     bool has_smram_at_smbase;
  53     bool has_smm_ranges;
  54     Range pci_hole;
  55     uint64_t below_4g_mem_size;
  56     uint64_t above_4g_mem_size;
  57     uint64_t pci_hole64_size;
  58     uint16_t ext_tseg_mbytes;
  59 };
  60
  61 struct Q35PCIHost {
  62     /*< private >*/
  63     PCIExpressHost parent_obj;
  64     /*< public >*/
  65
  66     bool pci_hole64_fix;
  67     MCHPCIState mch;
  68 };
  69
  70 #define Q35_MASK(bit, ms_bit, ls_bit) \
  71 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
  72
  73 /*
  74  * gmch part
  75  */
  76
  77 /* PCI configuration */
  78 #define MCH_HOST_BRIDGE                        "MCH"
  79
  80 #define MCH_HOST_BRIDGE_CONFIG_ADDR            0xcf8
  81 #define MCH_HOST_BRIDGE_CONFIG_DATA            0xcfc
  82
  83 /* D0:F0 configuration space */
  84 #define MCH_HOST_BRIDGE_REVISION_DEFAULT       0x0
  85
  86 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES        0x50
  87 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE   2
  88 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY  0xffff
  89 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX    0xfff
  90
  91 #define MCH_HOST_BRIDGE_SMBASE_SIZE            (128 * KiB)
  92 #define MCH_HOST_BRIDGE_SMBASE_ADDR            0x30000
  93 #define MCH_HOST_BRIDGE_F_SMBASE               0x9c
  94 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY         0xff
  95 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM        0x01
  96 #define MCH_HOST_BRIDGE_F_SMBASE_LCK           0x02
  97
  98 #define MCH_HOST_BRIDGE_PCIEXBAR               0x60    /* 64bit register */
  99 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE          8       /* 64bit register */
 100 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT       0xb0000000
 101 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX           (0x10000000) /* 256M */
 102 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK         Q35_MASK(64, 35, 28)
 103 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK      ((uint64_t)(1 << 26))
 104 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK       ((uint64_t)(1 << 25))
 105 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK   ((uint64_t)(0x3 << 1))
 106 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M   ((uint64_t)(0x0 << 1))
 107 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M   ((uint64_t)(0x1 << 1))
 108 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M    ((uint64_t)(0x2 << 1))
 109 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD    ((uint64_t)(0x3 << 1))
 110 #define MCH_HOST_BRIDGE_PCIEXBAREN             ((uint64_t)1)
 111
 112 #define MCH_HOST_BRIDGE_PAM_NB                 7
 113 #define MCH_HOST_BRIDGE_PAM_SIZE               7
 114 #define MCH_HOST_BRIDGE_PAM0                   0x90
 115 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA          0xf0000
 116 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE          0x10000 /* 16KB */
 117 #define MCH_HOST_BRIDGE_PAM1                   0x91
 118 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA         0xc0000
 119 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE         0x04000
 120 #define MCH_HOST_BRIDGE_PAM2                   0x92
 121 #define MCH_HOST_BRIDGE_PAM3                   0x93
 122 #define MCH_HOST_BRIDGE_PAM4                   0x94
 123 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA        0xe0000
 124 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE        0x04000
 125 #define MCH_HOST_BRIDGE_PAM5                   0x95
 126 #define MCH_HOST_BRIDGE_PAM6                   0x96
 127 #define MCH_HOST_BRIDGE_PAM_WE_HI              ((uint8_t)(0x2 << 4))
 128 #define MCH_HOST_BRIDGE_PAM_RE_HI              ((uint8_t)(0x1 << 4))
 129 #define MCH_HOST_BRIDGE_PAM_HI_MASK            ((uint8_t)(0x3 << 4))
 130 #define MCH_HOST_BRIDGE_PAM_WE_LO              ((uint8_t)0x2)
 131 #define MCH_HOST_BRIDGE_PAM_RE_LO              ((uint8_t)0x1)
 132 #define MCH_HOST_BRIDGE_PAM_LO_MASK            ((uint8_t)0x3)
 133 #define MCH_HOST_BRIDGE_PAM_WE                 ((uint8_t)0x2)
 134 #define MCH_HOST_BRIDGE_PAM_RE                 ((uint8_t)0x1)
 135 #define MCH_HOST_BRIDGE_PAM_MASK               ((uint8_t)0x3)
 136
 137 #define MCH_HOST_BRIDGE_SMRAM                  0x9d
 138 #define MCH_HOST_BRIDGE_SMRAM_SIZE             2
 139 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN           ((uint8_t)(1 << 6))
 140 #define MCH_HOST_BRIDGE_SMRAM_D_CLS            ((uint8_t)(1 << 5))
 141 #define MCH_HOST_BRIDGE_SMRAM_D_LCK            ((uint8_t)(1 << 4))
 142 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
 143 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
 144 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
 145 #define MCH_HOST_BRIDGE_SMRAM_C_BASE           0xa0000
 146 #define MCH_HOST_BRIDGE_SMRAM_C_END            0xc0000
 147 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE           0x20000
 148 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END  0x100000
 149 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT           \
 150     MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
 151 #define MCH_HOST_BRIDGE_SMRAM_WMASK             \
 152     (MCH_HOST_BRIDGE_SMRAM_D_OPEN |             \
 153      MCH_HOST_BRIDGE_SMRAM_D_CLS |              \
 154      MCH_HOST_BRIDGE_SMRAM_D_LCK |              \
 155      MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
 156 #define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK         \
 157     MCH_HOST_BRIDGE_SMRAM_D_CLS
 158
 159 #define MCH_HOST_BRIDGE_ESMRAMC                0x9e
 160 #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME       ((uint8_t)(1 << 7))
 161 #define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR        ((uint8_t)(1 << 6))
 162 #define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE       ((uint8_t)(1 << 5))
 163 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L1          ((uint8_t)(1 << 4))
 164 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L2          ((uint8_t)(1 << 3))
 165 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK   ((uint8_t)(0x3 << 1))
 166 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB    ((uint8_t)(0x0 << 1))
 167 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB    ((uint8_t)(0x1 << 1))
 168 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB    ((uint8_t)(0x2 << 1))
 169 #define MCH_HOST_BRIDGE_ESMRAMC_T_EN           ((uint8_t)1)
 170 #define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
 171     (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
 172      MCH_HOST_BRIDGE_ESMRAMC_SM_L1 |    \
 173      MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
 174 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK               \
 175     (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME |             \
 176      MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK |         \
 177      MCH_HOST_BRIDGE_ESMRAMC_T_EN)
 178 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK     0
 179
 180 /* D1:F0 PCIE* port*/
 181 #define MCH_PCIE_DEV                           1
 182 #define MCH_PCIE_FUNC                          0
 183
 184 /*
 185  * Arbitrary but unique BNF number for IOAPIC device.
 186  *
 187  * TODO: make sure there would have no conflict with real PCI bus
 188  */
 189 #define Q35_PSEUDO_BUS_PLATFORM         (0xff)
 190 #define Q35_PSEUDO_DEVFN_IOAPIC         (0x00)
 191
 192 #endif /* HW_Q35_H */