include/hw/pci/pci_device.h

   1 #ifndef QEMU_PCI_DEVICE_H
   2 #define QEMU_PCI_DEVICE_H
   3
   4 #include "hw/pci/pci.h"
   5 #include "hw/pci/pcie.h"
   6 #include "hw/pci/pcie_doe.h"
   7
   8 #define TYPE_PCI_DEVICE "pci-device"
   9 typedef struct PCIDeviceClass PCIDeviceClass;
  10 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
  11                      PCI_DEVICE, TYPE_PCI_DEVICE)
  12
  13 /*
  14  * Implemented by devices that can be plugged on CXL buses. In the spec, this is
  15  * actually a "CXL Component, but we name it device to match the PCI naming.
  16  */
  17 #define INTERFACE_CXL_DEVICE "cxl-device"
  18
  19 /* Implemented by devices that can be plugged on PCI Express buses */
  20 #define INTERFACE_PCIE_DEVICE "pci-express-device"
  21
  22 /* Implemented by devices that can be plugged on Conventional PCI buses */
  23 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
  24
  25 struct PCIDeviceClass {
  26     DeviceClass parent_class;
  27
  28     void (*realize)(PCIDevice *dev, Error **errp);
  29     PCIUnregisterFunc *exit;
  30     PCIConfigReadFunc *config_read;
  31     PCIConfigWriteFunc *config_write;
  32
  33     uint16_t vendor_id;
  34     uint16_t device_id;
  35     uint8_t revision;
  36     uint16_t class_id;
  37     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
  38     uint16_t subsystem_id;              /* only for header type = 0 */
  39
  40     const char *romfile;                /* rom bar */
  41 };
  42
  43 enum PCIReqIDType {
  44     PCI_REQ_ID_INVALID = 0,
  45     PCI_REQ_ID_BDF,
  46     PCI_REQ_ID_SECONDARY_BUS,
  47     PCI_REQ_ID_MAX,
  48 };
  49 typedef enum PCIReqIDType PCIReqIDType;
  50
  51 struct PCIReqIDCache {
  52     PCIDevice *dev;
  53     PCIReqIDType type;
  54 };
  55 typedef struct PCIReqIDCache PCIReqIDCache;
  56
  57 struct PCIDevice {
  58     DeviceState qdev;
  59     bool partially_hotplugged;
  60     bool has_power;
  61
  62     /* PCI config space */
  63     uint8_t *config;
  64
  65     /*
  66      * Used to enable config checks on load. Note that writable bits are
  67      * never checked even if set in cmask.
  68      */
  69     uint8_t *cmask;
  70
  71     /* Used to implement R/W bytes */
  72     uint8_t *wmask;
  73
  74     /* Used to implement RW1C(Write 1 to Clear) bytes */
  75     uint8_t *w1cmask;
  76
  77     /* Used to allocate config space for capabilities. */
  78     uint8_t *used;
  79
  80     /* the following fields are read only */
  81     int32_t devfn;
  82     /*
  83      * Cached device to fetch requester ID from, to avoid the PCI tree
  84      * walking every time we invoke PCI request (e.g., MSI). For
  85      * conventional PCI root complex, this field is meaningless.
  86      */
  87     PCIReqIDCache requester_id_cache;
  88     char name[64];
  89     PCIIORegion io_regions[PCI_NUM_REGIONS];
  90     AddressSpace bus_master_as;
  91     MemoryRegion bus_master_container_region;
  92     MemoryRegion bus_master_enable_region;
  93
  94     /* do not access the following fields */
  95     PCIConfigReadFunc *config_read;
  96     PCIConfigWriteFunc *config_write;
  97
  98     /* Legacy PCI VGA regions */
  99     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 100     bool has_vga;
 101
 102     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 103     uint8_t irq_state;
 104
 105     /* Capability bits */
 106     uint32_t cap_present;
 107
 108     /* Offset of MSI-X capability in config space */
 109     uint8_t msix_cap;
 110
 111     /* MSI-X entries */
 112     int msix_entries_nr;
 113
 114     /* Space to store MSIX table & pending bit array */
 115     uint8_t *msix_table;
 116     uint8_t *msix_pba;
 117
 118     /* May be used by INTx or MSI during interrupt notification */
 119     void *irq_opaque;
 120
 121     MSITriggerFunc *msi_trigger;
 122     MSIPrepareMessageFunc *msi_prepare_message;
 123     MSIxPrepareMessageFunc *msix_prepare_message;
 124
 125     /* MemoryRegion container for msix exclusive BAR setup */
 126     MemoryRegion msix_exclusive_bar;
 127     /* Memory Regions for MSIX table and pending bit entries. */
 128     MemoryRegion msix_table_mmio;
 129     MemoryRegion msix_pba_mmio;
 130     /* Reference-count for entries actually in use by driver. */
 131     unsigned *msix_entry_used;
 132     /* MSIX function mask set or MSIX disabled */
 133     bool msix_function_masked;
 134     /* Version id needed for VMState */
 135     int32_t version_id;
 136
 137     /* Offset of MSI capability in config space */
 138     uint8_t msi_cap;
 139
 140     /* PCI Express */
 141     PCIExpressDevice exp;
 142
 143     /* SHPC */
 144     SHPCDevice *shpc;
 145
 146     /* Location of option rom */
 147     char *romfile;
 148     uint32_t romsize;
 149     bool has_rom;
 150     MemoryRegion rom;
 151     uint32_t rom_bar;
 152
 153     /* INTx routing notifier */
 154     PCIINTxRoutingNotifier intx_routing_notifier;
 155
 156     /* MSI-X notifiers */
 157     MSIVectorUseNotifier msix_vector_use_notifier;
 158     MSIVectorReleaseNotifier msix_vector_release_notifier;
 159     MSIVectorPollNotifier msix_vector_poll_notifier;
 160
 161     /* SPDM */
 162     uint16_t spdm_port;
 163
 164     /* DOE */
 165     DOECap doe_spdm;
 166
 167     /* ID of standby device in net_failover pair */
 168     char *failover_pair_id;
 169     uint32_t acpi_index;
 170
 171     /* Maximum DMA bounce buffer size used for indirect memory map requests */
 172     uint32_t max_bounce_buffer_size;
 173 };
 174
 175 static inline int pci_intx(PCIDevice *pci_dev)
 176 {
 177     return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
 178 }
 179
 180 static inline int pci_is_cxl(const PCIDevice *d)
 181 {
 182     return d->cap_present & QEMU_PCIE_CAP_CXL;
 183 }
 184
 185 static inline int pci_is_express(const PCIDevice *d)
 186 {
 187     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 188 }
 189
 190 static inline int pci_is_express_downstream_port(const PCIDevice *d)
 191 {
 192     uint8_t type;
 193
 194     if (!pci_is_express(d) || !d->exp.exp_cap) {
 195         return 0;
 196     }
 197
 198     type = pcie_cap_get_type(d);
 199
 200     return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
 201 }
 202
 203 static inline int pci_is_vf(const PCIDevice *d)
 204 {
 205     return d->exp.sriov_vf.pf != NULL;
 206 }
 207
 208 static inline uint32_t pci_config_size(const PCIDevice *d)
 209 {
 210     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 211 }
 212
 213 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 214 {
 215     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
 216 }
 217
 218 uint16_t pci_requester_id(PCIDevice *dev);
 219
 220 /* DMA access functions */
 221 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 222 {
 223     return &dev->bus_master_as;
 224 }
 225
 226 /**
 227  * pci_dma_rw: Read from or write to an address space from PCI device.
 228  *
 229  * Return a MemTxResult indicating whether the operation succeeded
 230  * or failed (eg unassigned memory, device rejected the transaction,
 231  * IOMMU fault).
 232  *
 233  * @dev: #PCIDevice doing the memory access
 234  * @addr: address within the #PCIDevice address space
 235  * @buf: buffer with the data transferred
 236  * @len: the number of bytes to read or write
 237  * @dir: indicates the transfer direction
 238  */
 239 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 240                                      void *buf, dma_addr_t len,
 241                                      DMADirection dir, MemTxAttrs attrs)
 242 {
 243     return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
 244                          dir, attrs);
 245 }
 246
 247 /**
 248  * pci_dma_read: Read from an address space from PCI device.
 249  *
 250  * Return a MemTxResult indicating whether the operation succeeded
 251  * or failed (eg unassigned memory, device rejected the transaction,
 252  * IOMMU fault).  Called within RCU critical section.
 253  *
 254  * @dev: #PCIDevice doing the memory access
 255  * @addr: address within the #PCIDevice address space
 256  * @buf: buffer with the data transferred
 257  * @len: length of the data transferred
 258  */
 259 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 260                                        void *buf, dma_addr_t len)
 261 {
 262     return pci_dma_rw(dev, addr, buf, len,
 263                       DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
 264 }
 265
 266 /**
 267  * pci_dma_write: Write to address space from PCI device.
 268  *
 269  * Return a MemTxResult indicating whether the operation succeeded
 270  * or failed (eg unassigned memory, device rejected the transaction,
 271  * IOMMU fault).
 272  *
 273  * @dev: #PCIDevice doing the memory access
 274  * @addr: address within the #PCIDevice address space
 275  * @buf: buffer with the data transferred
 276  * @len: the number of bytes to write
 277  */
 278 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 279                                         const void *buf, dma_addr_t len)
 280 {
 281     return pci_dma_rw(dev, addr, (void *) buf, len,
 282                       DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
 283 }
 284
 285 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
 286     static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
 287                                                dma_addr_t addr, \
 288                                                uint##_bits##_t *val, \
 289                                                MemTxAttrs attrs) \
 290     { \
 291         return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
 292     } \
 293     static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
 294                                                dma_addr_t addr, \
 295                                                uint##_bits##_t val, \
 296                                                MemTxAttrs attrs) \
 297     { \
 298         return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
 299     }
 300
 301 PCI_DMA_DEFINE_LDST(ub, b, 8);
 302 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 303 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 304 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 305 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 306 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 307 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 308
 309 #undef PCI_DMA_DEFINE_LDST
 310
 311 /**
 312  * pci_dma_map: Map device PCI address space range into host virtual address
 313  * @dev: #PCIDevice to be accessed
 314  * @addr: address within that device's address space
 315  * @plen: pointer to length of buffer; updated on return to indicate
 316  *        if only a subset of the requested range has been mapped
 317  * @dir: indicates the transfer direction
 318  *
 319  * Return: A host pointer, or %NULL if the resources needed to
 320  *         perform the mapping are exhausted (in that case *@plen
 321  *         is set to zero).
 322  */
 323 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 324                                 dma_addr_t *plen, DMADirection dir)
 325 {
 326     return dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
 327                           MEMTXATTRS_UNSPECIFIED);
 328 }
 329
 330 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 331                                  DMADirection dir, dma_addr_t access_len)
 332 {
 333     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 334 }
 335
 336 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 337                                        int alloc_hint)
 338 {
 339     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 340 }
 341
 342 extern const VMStateDescription vmstate_pci_device;
 343
 344 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 345     .name       = (stringify(_field)),                               \
 346     .size       = sizeof(PCIDevice),                                 \
 347     .vmsd       = &vmstate_pci_device,                               \
 348     .flags      = VMS_STRUCT,                                        \
 349     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 350 }
 351
 352 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 353     .name       = (stringify(_field)),                               \
 354     .size       = sizeof(PCIDevice),                                 \
 355     .vmsd       = &vmstate_pci_device,                               \
 356     .flags      = VMS_STRUCT | VMS_POINTER,                          \
 357     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 358 }
 359
 360 #endif