include/hw/pci/pcie_doe.h

   1 /*
   2  * PCIe Data Object Exchange
   3  *
   4  * Copyright (C) 2021 Avery Design Systems, Inc.
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef PCIE_DOE_H
  11 #define PCIE_DOE_H
  12
  13 #include "qemu/range.h"
  14 #include "hw/register.h"
  15
  16 /*
  17  * Reference:
  18  * PCIe r6.0 - 7.9.24 Data Object Exchange Extended Capability
  19  */
  20 /* Capabilities Register - r6.0 7.9.24.2 */
  21 #define PCI_EXP_DOE_CAP             0x04
  22 REG32(PCI_DOE_CAP_REG, 0)
  23     FIELD(PCI_DOE_CAP_REG, INTR_SUPP, 0, 1)
  24     FIELD(PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, 1, 11)
  25
  26 /* Control Register - r6.0 7.9.24.3 */
  27 #define PCI_EXP_DOE_CTRL            0x08
  28 REG32(PCI_DOE_CAP_CONTROL, 0)
  29     FIELD(PCI_DOE_CAP_CONTROL, DOE_ABORT, 0, 1)
  30     FIELD(PCI_DOE_CAP_CONTROL, DOE_INTR_EN, 1, 1)
  31     FIELD(PCI_DOE_CAP_CONTROL, DOE_GO, 31, 1)
  32
  33 /* Status Register - r6.0 7.9.24.4 */
  34 #define PCI_EXP_DOE_STATUS          0x0c
  35 REG32(PCI_DOE_CAP_STATUS, 0)
  36     FIELD(PCI_DOE_CAP_STATUS, DOE_BUSY, 0, 1)
  37     FIELD(PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, 1, 1)
  38     FIELD(PCI_DOE_CAP_STATUS, DOE_ERROR, 2, 1)
  39     FIELD(PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, 31, 1)
  40
  41 /* Write Data Mailbox Register - r6.0 7.9.24.5 */
  42 #define PCI_EXP_DOE_WR_DATA_MBOX    0x10
  43
  44 /* Read Data Mailbox Register - 7.9.xx.6 */
  45 #define PCI_EXP_DOE_RD_DATA_MBOX    0x14
  46
  47 /* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */
  48 #define PCI_SIG_DOE_DISCOVERY       0x00
  49 #define PCI_SIG_DOE_CMA             0x01
  50 #define PCI_SIG_DOE_SECURED_CMA     0x02
  51
  52 #define PCI_DOE_DW_SIZE_MAX         (1 << 18)
  53 #define PCI_DOE_PROTOCOL_NUM_MAX    256
  54
  55 #define DATA_OBJ_BUILD_HEADER1(v, p)    (((p) << 16) | (v))
  56 #define DATA_OBJ_LEN_MASK(len)          ((len) & (PCI_DOE_DW_SIZE_MAX - 1))
  57
  58 typedef struct DOEHeader DOEHeader;
  59 typedef struct DOEProtocol DOEProtocol;
  60 typedef struct DOECap DOECap;
  61
  62 struct DOEHeader {
  63     uint16_t vendor_id;
  64     uint8_t data_obj_type;
  65     uint8_t reserved;
  66     uint32_t length;
  67 } QEMU_PACKED;
  68
  69 /* Protocol infos and rsp function callback */
  70 struct DOEProtocol {
  71     uint16_t vendor_id;
  72     uint8_t data_obj_type;
  73     bool (*handle_request)(DOECap *);
  74 };
  75
  76 struct DOECap {
  77     /* Owner */
  78     PCIDevice *pdev;
  79
  80     uint16_t offset;
  81
  82     struct {
  83         bool intr;
  84         uint16_t vec;
  85     } cap;
  86
  87     struct {
  88         bool abort;
  89         bool intr;
  90         bool go;
  91     } ctrl;
  92
  93     struct {
  94         bool busy;
  95         bool intr;
  96         bool error;
  97         bool ready;
  98     } status;
  99
 100     uint32_t *write_mbox;
 101     uint32_t *read_mbox;
 102
 103     /* Mailbox position indicator */
 104     uint32_t read_mbox_idx;
 105     uint32_t read_mbox_len;
 106     uint32_t write_mbox_len;
 107
 108     /* Protocols and its callback response */
 109     DOEProtocol *protocols;
 110     uint16_t protocol_num;
 111
 112     /* Used for spdm-socket */
 113     int spdm_socket;
 114 };
 115
 116 void pcie_doe_init(PCIDevice *pdev, DOECap *doe_cap, uint16_t offset,
 117                    DOEProtocol *protocols, bool intr, uint16_t vec);
 118 void pcie_doe_fini(DOECap *doe_cap);
 119 bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size,
 120                           uint32_t *buf);
 121 void pcie_doe_write_config(DOECap *doe_cap, uint32_t addr,
 122                            uint32_t val, int size);
 123 uint32_t pcie_doe_build_protocol(DOEProtocol *p);
 124 void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap);
 125 void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp);
 126 uint32_t pcie_doe_get_obj_len(void *obj);
 127 #endif /* PCIE_DOE_H */