include/hw/ppc/pnv.h

   1 /*
   2  * QEMU PowerPC PowerNV various definitions
   3  *
   4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_H
  21 #define PPC_PNV_H
  22
  23 #include "cpu.h"
  24 #include "hw/boards.h"
  25 #include "hw/sysbus.h"
  26 #include "hw/ipmi/ipmi.h"
  27 #include "hw/ppc/pnv_pnor.h"
  28
  29 #define TYPE_PNV_CHIP "pnv-chip"
  30
  31 typedef struct PnvCore PnvCore;
  32 typedef struct PnvChip PnvChip;
  33 typedef struct Pnv8Chip Pnv8Chip;
  34 typedef struct Pnv9Chip Pnv9Chip;
  35 typedef struct Pnv10Chip Pnv10Chip;
  36
  37 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
  38 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
  39
  40 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
  41 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
  42                          TYPE_PNV_CHIP_POWER8E)
  43
  44 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
  45 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
  46                          TYPE_PNV_CHIP_POWER8)
  47
  48 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
  49 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
  50                          TYPE_PNV_CHIP_POWER8NVL)
  51
  52 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2")
  53 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
  54                          TYPE_PNV_CHIP_POWER9)
  55
  56 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
  57 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
  58                          TYPE_PNV_CHIP_POWER10)
  59
  60 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
  61 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
  62
  63 typedef struct PnvPHB PnvPHB;
  64
  65 #define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
  66 typedef struct PnvMachineClass PnvMachineClass;
  67 typedef struct PnvMachineState PnvMachineState;
  68 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
  69                      PNV_MACHINE, TYPE_PNV_MACHINE)
  70
  71
  72 struct PnvMachineClass {
  73     /*< private >*/
  74     MachineClass parent_class;
  75
  76     /*< public >*/
  77     const char *compat;
  78     int compat_size;
  79     int max_smt_threads;
  80     bool has_lpar_per_thread;
  81     bool quirk_tb_big_core;
  82
  83     void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
  84     void (*i2c_init)(PnvMachineState *pnv);
  85 };
  86
  87 struct PnvMachineState {
  88     /*< private >*/
  89     MachineState parent_obj;
  90
  91     uint32_t     initrd_base;
  92     long         initrd_size;
  93
  94     uint32_t     num_chips;
  95     PnvChip      **chips;
  96
  97     ISABus       *isa_bus;
  98     uint32_t     cpld_irqstate;
  99
 100     IPMIBmc      *bmc;
 101     Notifier     powerdown_notifier;
 102
 103     PnvPnor      *pnor;
 104
 105     hwaddr       fw_load_addr;
 106
 107     bool         big_core;
 108     bool         lpar_per_core;
 109 };
 110
 111 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
 112 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
 113
 114 #define PNV_FDT_ADDR          0x01000000
 115 #define PNV_TIMEBASE_FREQ     512000000ULL
 116
 117 void pnv_cpu_do_nmi_resume(CPUState *cs);
 118
 119 /*
 120  * BMC helpers
 121  */
 122 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
 123 void pnv_bmc_powerdown(IPMIBmc *bmc);
 124 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
 125 IPMIBmc *pnv_bmc_find(Error **errp);
 126 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
 127
 128 /*
 129  * POWER8 MMIO base addresses
 130  */
 131 #define PNV_XSCOM_SIZE        0x800000000ull
 132 #define PNV_XSCOM_BASE(chip)                                            \
 133     (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
 134
 135 #define PNV_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
 136 #define PNV_OCC_COMMON_AREA_BASE    0x7fff800000ull
 137 #define PNV_OCC_SENSOR_BASE(chip)   (PNV_OCC_COMMON_AREA_BASE + \
 138     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
 139
 140 #define PNV_HOMER_SIZE              0x0000000000400000ull
 141 #define PNV_HOMER_BASE(chip)                                            \
 142     (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
 143
 144
 145 /*
 146  * XSCOM 0x20109CA defines the ICP BAR:
 147  *
 148  * 0:29   : bits 14 to 43 of address to define 1 MB region.
 149  * 30     : 1 to enable ICP to receive loads/stores against its BAR region
 150  * 31:63  : Constant 0
 151  *
 152  * Usually defined as :
 153  *
 154  *      0xffffe00200000000 -> 0x0003ffff80000000
 155  *      0xffffe00600000000 -> 0x0003ffff80100000
 156  *      0xffffe02200000000 -> 0x0003ffff80800000
 157  *      0xffffe02600000000 -> 0x0003ffff80900000
 158  */
 159 #define PNV_ICP_SIZE         0x0000000000100000ull
 160 #define PNV_ICP_BASE(chip)                                              \
 161     (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
 162
 163
 164 #define PNV_PSIHB_SIZE       0x0000000000100000ull
 165 #define PNV_PSIHB_BASE(chip) \
 166     (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
 167
 168 #define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
 169 #define PNV_PSIHB_FSP_BASE(chip) \
 170     (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
 171      PNV_PSIHB_FSP_SIZE)
 172
 173 /*
 174  * POWER9 MMIO base addresses
 175  */
 176 #define PNV9_CHIP_BASE(chip, base)   \
 177     ((base) + ((uint64_t) (chip)->chip_id << 42))
 178
 179 #define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
 180 #define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
 181
 182 #define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
 183 #define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
 184
 185 #define PNV9_LPCM_SIZE               0x0000000100000000ull
 186 #define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
 187
 188 #define PNV9_PSIHB_SIZE              0x0000000000100000ull
 189 #define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
 190
 191 #define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
 192 #define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
 193
 194 #define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
 195 #define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
 196
 197 #define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
 198 #define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
 199
 200 #define PNV9_XSCOM_SIZE              0x0000000400000000ull
 201 #define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
 202
 203 #define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
 204 #define PNV9_OCC_COMMON_AREA_BASE    0x203fff800000ull
 205 #define PNV9_OCC_SENSOR_BASE(chip)   (PNV9_OCC_COMMON_AREA_BASE +       \
 206     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
 207
 208 #define PNV9_HOMER_SIZE              0x0000000000400000ull
 209 #define PNV9_HOMER_BASE(chip)                                           \
 210     (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
 211
 212 /*
 213  * POWER10 MMIO base addresses - 16TB stride per chip
 214  */
 215 #define PNV10_CHIP_BASE(chip, base)   \
 216     ((base) + ((uint64_t) (chip)->chip_id << 44))
 217
 218 #define PNV10_XSCOM_SIZE             0x0000000400000000ull
 219 #define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
 220
 221 #define PNV10_LPCM_SIZE             0x0000000100000000ull
 222 #define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
 223
 224 #define PNV10_XIVE2_IC_SIZE         0x0000000002000000ull
 225 #define PNV10_XIVE2_IC_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
 226
 227 #define PNV10_PSIHB_ESB_SIZE        0x0000000000100000ull
 228 #define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
 229
 230 #define PNV10_PSIHB_SIZE            0x0000000000100000ull
 231 #define PNV10_PSIHB_BASE(chip)      PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
 232
 233 #define PNV10_XIVE2_TM_SIZE         0x0000000000040000ull
 234 #define PNV10_XIVE2_TM_BASE(chip)   PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
 235
 236 #define PNV10_XIVE2_NVC_SIZE        0x0000000008000000ull
 237 #define PNV10_XIVE2_NVC_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
 238
 239 #define PNV10_XIVE2_NVPG_SIZE       0x0000010000000000ull
 240 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
 241
 242 #define PNV10_XIVE2_ESB_SIZE        0x0000010000000000ull
 243 #define PNV10_XIVE2_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
 244
 245 #define PNV10_XIVE2_END_SIZE        0x0000020000000000ull
 246 #define PNV10_XIVE2_END_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
 247
 248 #define PNV10_OCC_COMMON_AREA_SIZE  0x0000000000800000ull
 249 #define PNV10_OCC_COMMON_AREA_BASE  0x300fff800000ull
 250 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE +       \
 251     PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
 252
 253 #define PNV10_HOMER_SIZE              0x0000000000400000ull
 254 #define PNV10_HOMER_BASE(chip)                                           \
 255     (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
 256
 257 #endif /* PPC_PNV_H */