include/hw/ppc/pnv_chip.h

   1 #ifndef PPC_PNV_CHIP_H
   2 #define PPC_PNV_CHIP_H
   3
   4 #include "hw/pci-host/pnv_phb4.h"
   5 #include "hw/ppc/pnv_adu.h"
   6 #include "hw/ppc/pnv_chiptod.h"
   7 #include "hw/ppc/pnv_core.h"
   8 #include "hw/ppc/pnv_homer.h"
   9 #include "hw/ppc/pnv_n1_chiplet.h"
  10 #include "hw/ssi/pnv_spi.h"
  11 #include "hw/ppc/pnv_lpc.h"
  12 #include "hw/ppc/pnv_occ.h"
  13 #include "hw/ppc/pnv_psi.h"
  14 #include "hw/ppc/pnv_sbe.h"
  15 #include "hw/ppc/pnv_xive.h"
  16 #include "hw/ppc/pnv_i2c.h"
  17 #include "hw/sysbus.h"
  18
  19 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
  20                     PNV_CHIP)
  21
  22 struct PnvChip {
  23     /*< private >*/
  24     SysBusDevice parent_obj;
  25
  26     /*< public >*/
  27     uint32_t     chip_id;
  28     uint64_t     ram_start;
  29     uint64_t     ram_size;
  30
  31     bool         big_core;
  32     bool         lpar_per_core;
  33     uint32_t     nr_cores;
  34     uint32_t     nr_threads;
  35     uint64_t     cores_mask;
  36     PnvCore      **cores;
  37
  38     uint32_t     num_pecs;
  39
  40     MemoryRegion xscom_mmio;
  41     MemoryRegion xscom;
  42     AddressSpace xscom_as;
  43
  44     MemoryRegion *fw_mr;
  45     gchar        *dt_isa_nodename;
  46 };
  47
  48 #define TYPE_PNV8_CHIP "pnv8-chip"
  49 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
  50                          TYPE_PNV8_CHIP)
  51
  52 struct Pnv8Chip {
  53     /*< private >*/
  54     PnvChip      parent_obj;
  55
  56     /*< public >*/
  57     MemoryRegion icp_mmio;
  58
  59     PnvLpcController lpc;
  60     Pnv8Psi      psi;
  61     PnvOCC       occ;
  62     PnvHomer     homer;
  63
  64 #define PNV8_CHIP_PHB3_MAX 4
  65     /*
  66      * The array is used to allow quick access to the phbs by
  67      * pnv_ics_get_child() and pnv_ics_resend_child().
  68      */
  69     PnvPHB       *phbs[PNV8_CHIP_PHB3_MAX];
  70     uint32_t     num_phbs;
  71
  72     XICSFabric    *xics;
  73 };
  74
  75 #define TYPE_PNV9_CHIP "pnv9-chip"
  76 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
  77                          TYPE_PNV9_CHIP)
  78
  79 struct Pnv9Chip {
  80     /*< private >*/
  81     PnvChip      parent_obj;
  82
  83     /*< public >*/
  84     PnvADU       adu;
  85     PnvXive      xive;
  86     Pnv9Psi      psi;
  87     PnvLpcController lpc;
  88     PnvChipTOD   chiptod;
  89     PnvOCC       occ;
  90     PnvSBE       sbe;
  91     PnvHomer     homer;
  92
  93     uint32_t     nr_quads;
  94     PnvQuad      *quads;
  95
  96 #define PNV9_CHIP_MAX_PEC 3
  97     PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
  98
  99 #define PNV9_CHIP_MAX_I2C 4
 100     PnvI2C      i2c[PNV9_CHIP_MAX_I2C];
 101 };
 102
 103 /*
 104  * A SMT8 fused core is a pair of SMT4 cores.
 105  */
 106 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
 107 #define PNV9_PIR2CHIP(pir)      (((pir) >> 8) & 0x7f)
 108
 109 #define TYPE_PNV10_CHIP "pnv10-chip"
 110 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
 111                          TYPE_PNV10_CHIP)
 112
 113 struct Pnv10Chip {
 114     /*< private >*/
 115     PnvChip      parent_obj;
 116
 117     /*< public >*/
 118     PnvADU       adu;
 119     PnvXive2     xive;
 120     Pnv9Psi      psi;
 121     PnvLpcController lpc;
 122     PnvChipTOD   chiptod;
 123     PnvOCC       occ;
 124     PnvSBE       sbe;
 125     PnvHomer     homer;
 126     PnvN1Chiplet     n1_chiplet;
 127 #define PNV10_CHIP_MAX_PIB_SPIC 6
 128     PnvSpi pib_spic[PNV10_CHIP_MAX_PIB_SPIC];
 129
 130     uint32_t     nr_quads;
 131     PnvQuad      *quads;
 132
 133 #define PNV10_CHIP_MAX_PEC 2
 134     PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
 135
 136 #define PNV10_CHIP_MAX_I2C 4
 137     PnvI2C       i2c[PNV10_CHIP_MAX_I2C];
 138 };
 139
 140 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
 141 #define PNV10_PIR2CHIP(pir)      (((pir) >> 8) & 0x7f)
 142 #define PNV10_PIR2THREAD(pir)    (((pir) & 0x7f))
 143
 144 struct PnvChipClass {
 145     /*< private >*/
 146     SysBusDeviceClass parent_class;
 147
 148     /*< public >*/
 149     uint64_t     chip_cfam_id;
 150     uint64_t     cores_mask;
 151     uint32_t     num_pecs;
 152     uint32_t     num_phbs;
 153
 154     uint32_t     i2c_num_engines;
 155     const int    *i2c_ports_per_engine;
 156
 157     DeviceRealize parent_realize;
 158
 159     /* Get PIR and TIR values for a CPU thread identified by core/thread id */
 160     void (*get_pir_tir)(PnvChip *chip, uint32_t core_id, uint32_t thread_id,
 161                          uint32_t *pir, uint32_t *tir);
 162     void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
 163     void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
 164     void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
 165     void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, GString *buf);
 166     ISABus *(*isa_create)(PnvChip *chip, Error **errp);
 167     void (*dt_populate)(PnvChip *chip, void *fdt);
 168     void (*pic_print_info)(PnvChip *chip, GString *buf);
 169     uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
 170     uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
 171 };
 172
 173 #endif