include/hw/ppc/pnv_lpc.h

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016-2022, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_LPC_H
  21 #define PPC_PNV_LPC_H
  22
  23 #include "exec/memory.h"
  24 #include "hw/ppc/pnv.h"
  25 #include "hw/qdev-core.h"
  26 #include "hw/isa/isa.h" /* For ISA_NUM_IRQS */
  27
  28 #define TYPE_PNV_LPC "pnv-lpc"
  29 typedef struct PnvLpcClass PnvLpcClass;
  30 typedef struct PnvLpcController PnvLpcController;
  31 DECLARE_OBJ_CHECKERS(PnvLpcController, PnvLpcClass,
  32                      PNV_LPC, TYPE_PNV_LPC)
  33 #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
  34 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV8_LPC,
  35                          TYPE_PNV8_LPC)
  36
  37 #define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
  38 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV9_LPC,
  39                          TYPE_PNV9_LPC)
  40
  41 #define TYPE_PNV10_LPC TYPE_PNV_LPC "-POWER10"
  42 DECLARE_INSTANCE_CHECKER(PnvLpcController, PNV10_LPC,
  43                          TYPE_PNV10_LPC)
  44
  45 struct PnvLpcController {
  46     DeviceState parent;
  47
  48     uint64_t eccb_stat_reg;
  49     uint32_t eccb_data_reg;
  50
  51     /* OPB bus */
  52     MemoryRegion opb_mr;
  53     AddressSpace opb_as;
  54
  55     /* ISA IO and Memory space */
  56     MemoryRegion isa_io;
  57     MemoryRegion isa_mem;
  58     MemoryRegion isa_fw;
  59
  60     /* Windows from OPB to ISA (aliases) */
  61     MemoryRegion opb_isa_io;
  62     MemoryRegion opb_isa_mem;
  63     MemoryRegion opb_isa_fw;
  64
  65     /* Registers */
  66     MemoryRegion lpc_hc_regs;
  67     MemoryRegion opb_master_regs;
  68
  69     /* OPB Master LS registers */
  70     uint32_t opb_irq_route0;
  71     uint32_t opb_irq_route1;
  72     uint32_t opb_irq_stat;
  73     uint32_t opb_irq_mask;
  74     uint32_t opb_irq_pol;
  75     uint32_t opb_irq_input;
  76
  77     /* LPC device IRQ state */
  78     uint32_t lpc_hc_irq_inputs;
  79
  80     /* LPC HC registers */
  81     uint32_t lpc_hc_fw_seg_idsel;
  82     uint32_t lpc_hc_fw_rd_acc_size;
  83     uint32_t lpc_hc_irqser_ctrl;
  84     uint32_t lpc_hc_irqmask;
  85     uint32_t lpc_hc_irqstat;
  86     uint32_t lpc_hc_error_addr;
  87
  88     /* XSCOM registers */
  89     MemoryRegion xscom_regs;
  90
  91     /*
  92      * In P8, ISA irqs are combined with internal sources to drive the
  93      * LPCHC interrupt output. P9 ISA irqs raise one of 4 lines that
  94      * drive PSI SERIRQ irqs, routing according to OPB routing registers.
  95      */
  96     bool psi_has_serirq;
  97
  98     /* PSI to generate interrupts */
  99     qemu_irq psi_irq_lpchc;
 100
 101     /* P9 serirq lines and irq routing table */
 102     qemu_irq psi_irq_serirq[4];
 103     int irq_to_serirq_route[ISA_NUM_IRQS];
 104 };
 105
 106 struct PnvLpcClass {
 107     DeviceClass parent_class;
 108
 109     DeviceRealize parent_realize;
 110 };
 111
 112 bool pnv_lpc_opb_read(PnvLpcController *lpc, uint32_t addr,
 113                       uint8_t *data, int sz);
 114 bool pnv_lpc_opb_write(PnvLpcController *lpc, uint32_t addr,
 115                        uint8_t *data, int sz);
 116
 117 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
 118 int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset,
 119                uint64_t lpcm_addr, uint64_t lpcm_size);
 120
 121 #endif /* PPC_PNV_LPC_H */