include/hw/ppc/pnv_psi.h

   1 /*
   2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
   3  *
   4  * Copyright (c) 2015-2022, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PPC_PNV_PSI_H
  21 #define PPC_PNV_PSI_H
  22
  23 #include "hw/sysbus.h"
  24 #include "hw/ppc/xics.h"
  25 #include "hw/ppc/xive.h"
  26 #include "hw/qdev-core.h"
  27
  28 #define TYPE_PNV_PSI "pnv-psi"
  29 OBJECT_DECLARE_TYPE(PnvPsi, PnvPsiClass,
  30                     PNV_PSI)
  31
  32 #define PSIHB_XSCOM_MAX         0x20
  33
  34 struct PnvPsi {
  35     DeviceState parent;
  36
  37     MemoryRegion regs_mr;
  38     uint64_t bar;
  39
  40     /* FSP region not supported */
  41     /* MemoryRegion fsp_mr; */
  42     uint64_t fsp_bar;
  43
  44     /* Interrupt generation */
  45     qemu_irq *qirqs;
  46
  47     /* Registers */
  48     uint64_t regs[PSIHB_XSCOM_MAX];
  49
  50     MemoryRegion xscom_regs;
  51 };
  52
  53 #define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
  54 OBJECT_DECLARE_SIMPLE_TYPE(Pnv8Psi, PNV8_PSI)
  55
  56 struct Pnv8Psi {
  57     PnvPsi   parent;
  58
  59     ICSState ics;
  60 };
  61
  62 #define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
  63 OBJECT_DECLARE_SIMPLE_TYPE(Pnv9Psi, PNV9_PSI)
  64
  65 struct Pnv9Psi {
  66     PnvPsi   parent;
  67
  68     XiveSource source;
  69 };
  70
  71 #define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
  72
  73
  74 struct PnvPsiClass {
  75     SysBusDeviceClass parent_class;
  76
  77     uint32_t xscom_pcba;
  78     uint32_t xscom_size;
  79     uint64_t bar_mask;
  80     const char *compat;
  81     int compat_size;
  82 };
  83
  84 /* The PSI and FSP interrupts are muxed on the same IRQ number */
  85 typedef enum PnvPsiIrq {
  86     PSIHB_IRQ_FSP, /* internal use only */
  87     PSIHB_IRQ_OCC,
  88     PSIHB_IRQ_FSI,
  89     PSIHB_IRQ_LPC_I2C,
  90     PSIHB_IRQ_LOCAL_ERR,
  91     PSIHB_IRQ_EXTERNAL,
  92 } PnvPsiIrq;
  93
  94 #define PSI_NUM_INTERRUPTS 6
  95
  96 /* P9 PSI Interrupts */
  97 #define PSIHB9_IRQ_PSI          0
  98 #define PSIHB9_IRQ_OCC          1
  99 #define PSIHB9_IRQ_FSI          2
 100 #define PSIHB9_IRQ_LPCHC        3
 101 #define PSIHB9_IRQ_LOCAL_ERR    4
 102 #define PSIHB9_IRQ_GLOBAL_ERR   5
 103 #define PSIHB9_IRQ_TPM          6
 104 #define PSIHB9_IRQ_LPC_SIRQ0    7
 105 #define PSIHB9_IRQ_LPC_SIRQ1    8
 106 #define PSIHB9_IRQ_LPC_SIRQ2    9
 107 #define PSIHB9_IRQ_LPC_SIRQ3    10
 108 #define PSIHB9_IRQ_SBE_I2C      11
 109 #define PSIHB9_IRQ_DIO          12
 110 #define PSIHB9_IRQ_PSU          13
 111 #define PSIHB9_NUM_IRQS         14
 112
 113 void pnv_psi_pic_print_info(Pnv9Psi *psi, GString *buf);
 114
 115 #endif /* PPC_PNV_PSI_H */