2 * sPAPR CPU core device.
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
9 #ifndef HW_SPAPR_CPU_CORE_H
10 #define HW_SPAPR_CPU_CORE_H
12 #include "hw/cpu/core.h"
13 #include "hw/qdev-core.h"
14 #include "target/ppc/cpu-qom.h"
15 #include "target/ppc/cpu.h"
16 #include "qom/object.h"
18 #define TYPE_SPAPR_CPU_CORE "spapr-cpu-core"
19 OBJECT_DECLARE_TYPE(SpaprCpuCore
, SpaprCpuCoreClass
,
22 #define SPAPR_CPU_CORE_TYPE_NAME(model) model "-" TYPE_SPAPR_CPU_CORE
31 bool pre_3_0_migration
; /* older machine don't know about SpaprCpuState */
34 struct SpaprCpuCoreClass
{
35 DeviceClass parent_class
;
39 const char *spapr_get_cpu_core_type(const char *cpu_type
);
40 void spapr_cpu_set_entry_state(PowerPCCPU
*cpu
, target_ulong nip
,
41 target_ulong r1
, target_ulong r3
,
44 struct nested_ppc_state
;
46 typedef struct SpaprCpuState
{
48 uint64_t slb_shadow_addr
, slb_shadow_size
;
49 uint64_t dtl_addr
, dtl_size
;
50 bool prod
; /* not migrated, only used to improve dispatch latencies */
52 struct XiveTCTX
*tctx
;
54 /* Fields for nested-HV support */
55 bool in_nested
; /* true while the L2 is executing */
56 struct nested_ppc_state
*nested_host_state
; /* holds the L1 state while L2 executes */
59 static inline SpaprCpuState
*spapr_cpu_state(PowerPCCPU
*cpu
)
61 return (SpaprCpuState
*)cpu
->machine_data
;