include/hw/riscv/boot.h

   1 /*
   2  * QEMU RISC-V Boot Helper
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef RISCV_BOOT_H
  21 #define RISCV_BOOT_H
  22
  23 #include "exec/cpu-defs.h"
  24 #include "hw/loader.h"
  25 #include "hw/riscv/riscv_hart.h"
  26
  27 #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
  28 #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
  29
  30 bool riscv_is_32bit(RISCVHartArrayState *harts);
  31
  32 char *riscv_plic_hart_config_string(int hart_count);
  33
  34 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
  35                                           target_ulong firmware_end_addr);
  36 target_ulong riscv_find_and_load_firmware(MachineState *machine,
  37                                           const char *default_machine_firmware,
  38                                           hwaddr *firmware_load_addr,
  39                                           symbol_fn_t sym_cb);
  40 const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
  41 char *riscv_find_firmware(const char *firmware_filename,
  42                           const char *default_machine_firmware);
  43 target_ulong riscv_load_firmware(const char *firmware_filename,
  44                                  hwaddr *firmware_load_addr,
  45                                  symbol_fn_t sym_cb);
  46 target_ulong riscv_load_kernel(MachineState *machine,
  47                                RISCVHartArrayState *harts,
  48                                target_ulong firmware_end_addr,
  49                                bool load_initrd,
  50                                symbol_fn_t sym_cb);
  51 uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size,
  52                                 MachineState *ms);
  53 void riscv_load_fdt(hwaddr fdt_addr, void *fdt);
  54 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
  55                                hwaddr saddr,
  56                                hwaddr rom_base, hwaddr rom_size,
  57                                uint64_t kernel_entry,
  58                                uint64_t fdt_load_addr);
  59 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
  60                                   hwaddr rom_size,
  61                                   uint32_t reset_vec_size,
  62                                   uint64_t kernel_entry);
  63 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr);
  64 void riscv_setup_firmware_boot(MachineState *machine);
  65
  66 #endif /* RISCV_BOOT_H */