include/hw/ssi/xilinx_spips.h

   1 /*
   2  * Header file for the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef XILINX_SPIPS_H
  26 #define XILINX_SPIPS_H
  27
  28 #include "hw/ssi/ssi.h"
  29 #include "qemu/fifo32.h"
  30 #include "hw/stream.h"
  31 #include "hw/sysbus.h"
  32 #include "qom/object.h"
  33
  34 typedef struct XilinxSPIPS XilinxSPIPS;
  35
  36 /* For SPIPS, QSPIPS.  */
  37 #define XLNX_SPIPS_R_MAX        (0x100 / 4)
  38 /* For ZYNQMP_QSPIPS.  */
  39 #define XLNX_ZYNQMP_SPIPS_R_MAX (0x200 / 4)
  40
  41 /* Bite off 4k chunks at a time */
  42 #define LQSPI_CACHE_SIZE 1024
  43
  44 #define QSPI_DMA_MAX_BURST_SIZE 2048
  45
  46 typedef enum {
  47     READ = 0x3,         READ_4 = 0x13,
  48     FAST_READ = 0xb,    FAST_READ_4 = 0x0c,
  49     DOR = 0x3b,         DOR_4 = 0x3c,
  50     QOR = 0x6b,         QOR_4 = 0x6c,
  51     DIOR = 0xbb,        DIOR_4 = 0xbc,
  52     QIOR = 0xeb,        QIOR_4 = 0xec,
  53
  54     PP = 0x2,           PP_4 = 0x12,
  55     DPP = 0xa2,
  56     QPP = 0x32,         QPP_4 = 0x34,
  57 } FlashCMD;
  58
  59 struct XilinxSPIPS {
  60     SysBusDevice parent_obj;
  61
  62     MemoryRegion iomem;
  63     MemoryRegion mmlqspi;
  64
  65     qemu_irq irq;
  66     int irqline;
  67
  68     uint8_t num_cs;
  69     uint8_t num_busses;
  70
  71     uint8_t snoop_state;
  72     int cmd_dummies;
  73     uint8_t link_state;
  74     uint8_t link_state_next;
  75     uint8_t link_state_next_when;
  76     qemu_irq *cs_lines;
  77     bool *cs_lines_state;
  78     SSIBus **spi;
  79
  80     Fifo8 rx_fifo;
  81     Fifo8 tx_fifo;
  82
  83     uint8_t num_txrx_bytes;
  84     uint32_t rx_discard;
  85
  86     uint32_t regs[XLNX_SPIPS_R_MAX];
  87
  88     bool man_start_com;
  89 };
  90
  91 struct XilinxQSPIPS {
  92     XilinxSPIPS parent_obj;
  93
  94     uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
  95     hwaddr lqspi_cached_addr;
  96     Error *migration_blocker;
  97     bool mmio_execution_enabled;
  98 };
  99 typedef struct XilinxQSPIPS XilinxQSPIPS;
 100
 101 struct XlnxZynqMPQSPIPS {
 102     XilinxQSPIPS parent_obj;
 103
 104     StreamSink *dma;
 105     int gqspi_irqline;
 106
 107     uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
 108
 109     /* GQSPI has separate tx/rx fifos */
 110     Fifo8 rx_fifo_g;
 111     Fifo8 tx_fifo_g;
 112     Fifo32 fifo_g;
 113     /*
 114      * At the end of each generic command, misaligned extra bytes are discard
 115      * or padded to tx and rx respectively to round it out (and avoid need for
 116      * individual byte access. Since we use byte fifos, keep track of the
 117      * alignment WRT to word access.
 118      */
 119     uint8_t rx_fifo_g_align;
 120     uint8_t tx_fifo_g_align;
 121     bool man_start_com_g;
 122     uint32_t dma_burst_size;
 123     uint8_t dma_buf[QSPI_DMA_MAX_BURST_SIZE];
 124 };
 125
 126 struct XilinxSPIPSClass {
 127     SysBusDeviceClass parent_class;
 128
 129     const MemoryRegionOps *reg_ops;
 130     uint64_t reg_size;
 131
 132     uint32_t rx_fifo_size;
 133     uint32_t tx_fifo_size;
 134 };
 135
 136 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 137 #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 138 #define TYPE_XLNX_ZYNQMP_QSPIPS "xlnx.usmp-gqspi"
 139
 140 OBJECT_DECLARE_TYPE(XilinxSPIPS, XilinxSPIPSClass, XILINX_SPIPS)
 141
 142 OBJECT_DECLARE_SIMPLE_TYPE(XilinxQSPIPS, XILINX_QSPIPS)
 143
 144 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPQSPIPS, XLNX_ZYNQMP_QSPIPS)
 145
 146 #endif /* XILINX_SPIPS_H */