Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / include / hw / virtio / virtio-gpu.h
blobe343110e23db5a95334009190cd24faed8f23898
1 /*
2 * Virtio GPU Device
4 * Copyright Red Hat, Inc. 2013-2014
6 * Authors:
7 * Dave Airlie <airlied@redhat.com>
8 * Gerd Hoffmann <kraxel@redhat.com>
10 * This work is licensed under the terms of the GNU GPL, version 2.
11 * See the COPYING file in the top-level directory.
14 #ifndef HW_VIRTIO_GPU_H
15 #define HW_VIRTIO_GPU_H
17 #include "qemu/queue.h"
18 #include "ui/qemu-pixman.h"
19 #include "ui/console.h"
20 #include "hw/virtio/virtio.h"
21 #include "qemu/log.h"
22 #include "sysemu/vhost-user-backend.h"
24 #include "standard-headers/linux/virtio_gpu.h"
25 #include "standard-headers/linux/virtio_ids.h"
26 #include "qom/object.h"
28 #define TYPE_VIRTIO_GPU_BASE "virtio-gpu-base"
29 OBJECT_DECLARE_TYPE(VirtIOGPUBase, VirtIOGPUBaseClass,
30 VIRTIO_GPU_BASE)
32 #define TYPE_VIRTIO_GPU "virtio-gpu-device"
33 OBJECT_DECLARE_TYPE(VirtIOGPU, VirtIOGPUClass, VIRTIO_GPU)
35 #define TYPE_VIRTIO_GPU_GL "virtio-gpu-gl-device"
36 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPUGL, VIRTIO_GPU_GL)
38 #define TYPE_VHOST_USER_GPU "vhost-user-gpu"
39 OBJECT_DECLARE_SIMPLE_TYPE(VhostUserGPU, VHOST_USER_GPU)
41 #define TYPE_VIRTIO_GPU_RUTABAGA "virtio-gpu-rutabaga-device"
42 OBJECT_DECLARE_SIMPLE_TYPE(VirtIOGPURutabaga, VIRTIO_GPU_RUTABAGA)
44 struct virtio_gpu_simple_resource {
45 uint32_t resource_id;
46 uint32_t width;
47 uint32_t height;
48 uint32_t format;
49 uint64_t *addrs;
50 struct iovec *iov;
51 unsigned int iov_cnt;
52 uint32_t scanout_bitmask;
53 pixman_image_t *image;
54 qemu_pixman_shareable share_handle;
55 uint64_t hostmem;
57 uint64_t blob_size;
58 void *blob;
59 int dmabuf_fd;
60 uint8_t *remapped;
62 QTAILQ_ENTRY(virtio_gpu_simple_resource) next;
65 struct virtio_gpu_framebuffer {
66 pixman_format_code_t format;
67 uint32_t bytes_pp;
68 uint32_t width, height;
69 uint32_t stride;
70 uint32_t offset;
73 struct virtio_gpu_scanout {
74 QemuConsole *con;
75 DisplaySurface *ds;
76 uint32_t width, height;
77 int x, y;
78 int invalidate;
79 uint32_t resource_id;
80 struct virtio_gpu_update_cursor cursor;
81 QEMUCursor *current_cursor;
82 struct virtio_gpu_framebuffer fb;
85 struct virtio_gpu_requested_state {
86 uint16_t width_mm, height_mm;
87 uint32_t width, height;
88 uint32_t refresh_rate;
89 int x, y;
92 enum virtio_gpu_base_conf_flags {
93 VIRTIO_GPU_FLAG_VIRGL_ENABLED = 1,
94 VIRTIO_GPU_FLAG_STATS_ENABLED,
95 VIRTIO_GPU_FLAG_EDID_ENABLED,
96 VIRTIO_GPU_FLAG_DMABUF_ENABLED,
97 VIRTIO_GPU_FLAG_BLOB_ENABLED,
98 VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED,
99 VIRTIO_GPU_FLAG_RUTABAGA_ENABLED,
102 #define virtio_gpu_virgl_enabled(_cfg) \
103 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VIRGL_ENABLED))
104 #define virtio_gpu_stats_enabled(_cfg) \
105 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_STATS_ENABLED))
106 #define virtio_gpu_edid_enabled(_cfg) \
107 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_EDID_ENABLED))
108 #define virtio_gpu_dmabuf_enabled(_cfg) \
109 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED))
110 #define virtio_gpu_blob_enabled(_cfg) \
111 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED))
112 #define virtio_gpu_context_init_enabled(_cfg) \
113 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED))
114 #define virtio_gpu_rutabaga_enabled(_cfg) \
115 (_cfg.flags & (1 << VIRTIO_GPU_FLAG_RUTABAGA_ENABLED))
116 #define virtio_gpu_hostmem_enabled(_cfg) \
117 (_cfg.hostmem > 0)
119 struct virtio_gpu_base_conf {
120 uint32_t max_outputs;
121 uint32_t flags;
122 uint32_t xres;
123 uint32_t yres;
124 uint64_t hostmem;
127 struct virtio_gpu_ctrl_command {
128 VirtQueueElement elem;
129 VirtQueue *vq;
130 struct virtio_gpu_ctrl_hdr cmd_hdr;
131 uint32_t error;
132 bool finished;
133 QTAILQ_ENTRY(virtio_gpu_ctrl_command) next;
136 struct VirtIOGPUBase {
137 VirtIODevice parent_obj;
139 Error *migration_blocker;
141 struct virtio_gpu_base_conf conf;
142 struct virtio_gpu_config virtio_config;
143 const GraphicHwOps *hw_ops;
145 int renderer_blocked;
146 int enable;
148 MemoryRegion hostmem;
150 struct virtio_gpu_scanout scanout[VIRTIO_GPU_MAX_SCANOUTS];
152 int enabled_output_bitmask;
153 struct virtio_gpu_requested_state req_state[VIRTIO_GPU_MAX_SCANOUTS];
156 struct VirtIOGPUBaseClass {
157 VirtioDeviceClass parent;
159 void (*gl_flushed)(VirtIOGPUBase *g);
162 #define VIRTIO_GPU_BASE_PROPERTIES(_state, _conf) \
163 DEFINE_PROP_UINT32("max_outputs", _state, _conf.max_outputs, 1), \
164 DEFINE_PROP_BIT("edid", _state, _conf.flags, \
165 VIRTIO_GPU_FLAG_EDID_ENABLED, true), \
166 DEFINE_PROP_UINT32("xres", _state, _conf.xres, 1280), \
167 DEFINE_PROP_UINT32("yres", _state, _conf.yres, 800)
169 typedef struct VGPUDMABuf {
170 QemuDmaBuf *buf;
171 uint32_t scanout_id;
172 QTAILQ_ENTRY(VGPUDMABuf) next;
173 } VGPUDMABuf;
175 struct VirtIOGPU {
176 VirtIOGPUBase parent_obj;
178 uint8_t scanout_vmstate_version;
179 uint64_t conf_max_hostmem;
181 VirtQueue *ctrl_vq;
182 VirtQueue *cursor_vq;
184 QEMUBH *ctrl_bh;
185 QEMUBH *cursor_bh;
186 QEMUBH *reset_bh;
187 QemuCond reset_cond;
188 bool reset_finished;
190 QTAILQ_HEAD(, virtio_gpu_simple_resource) reslist;
191 QTAILQ_HEAD(, virtio_gpu_ctrl_command) cmdq;
192 QTAILQ_HEAD(, virtio_gpu_ctrl_command) fenceq;
194 uint64_t hostmem;
196 bool processing_cmdq;
197 QEMUTimer *fence_poll;
198 QEMUTimer *print_stats;
200 uint32_t inflight;
201 struct {
202 uint32_t max_inflight;
203 uint32_t requests;
204 uint32_t req_3d;
205 uint32_t bytes_3d;
206 } stats;
208 struct {
209 QTAILQ_HEAD(, VGPUDMABuf) bufs;
210 VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS];
211 } dmabuf;
214 struct VirtIOGPUClass {
215 VirtIOGPUBaseClass parent;
217 void (*handle_ctrl)(VirtIODevice *vdev, VirtQueue *vq);
218 void (*process_cmd)(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
219 void (*update_cursor_data)(VirtIOGPU *g,
220 struct virtio_gpu_scanout *s,
221 uint32_t resource_id);
222 void (*resource_destroy)(VirtIOGPU *g,
223 struct virtio_gpu_simple_resource *res,
224 Error **errp);
227 struct VirtIOGPUGL {
228 struct VirtIOGPU parent_obj;
230 bool renderer_inited;
231 bool renderer_reset;
234 struct VhostUserGPU {
235 VirtIOGPUBase parent_obj;
237 VhostUserBackend *vhost;
238 int vhost_gpu_fd; /* closed by the chardev */
239 CharBackend vhost_chr;
240 QemuDmaBuf *dmabuf[VIRTIO_GPU_MAX_SCANOUTS];
241 bool backend_blocked;
244 #define MAX_SLOTS 4096
246 struct MemoryRegionInfo {
247 int used;
248 MemoryRegion mr;
249 uint32_t resource_id;
252 struct rutabaga;
254 struct VirtIOGPURutabaga {
255 VirtIOGPU parent_obj;
256 struct MemoryRegionInfo memory_regions[MAX_SLOTS];
257 uint64_t capset_mask;
258 char *wayland_socket_path;
259 char *wsi;
260 bool headless;
261 uint32_t num_capsets;
262 struct rutabaga *rutabaga;
265 #define VIRTIO_GPU_FILL_CMD(out) do { \
266 size_t virtiogpufillcmd_s_ = \
267 iov_to_buf(cmd->elem.out_sg, cmd->elem.out_num, 0, \
268 &out, sizeof(out)); \
269 if (virtiogpufillcmd_s_ != sizeof(out)) { \
270 qemu_log_mask(LOG_GUEST_ERROR, \
271 "%s: command size incorrect %zu vs %zu\n", \
272 __func__, virtiogpufillcmd_s_, sizeof(out)); \
273 return; \
275 } while (0)
277 /* virtio-gpu-base.c */
278 bool virtio_gpu_base_device_realize(DeviceState *qdev,
279 VirtIOHandleOutput ctrl_cb,
280 VirtIOHandleOutput cursor_cb,
281 Error **errp);
282 void virtio_gpu_base_device_unrealize(DeviceState *qdev);
283 void virtio_gpu_base_reset(VirtIOGPUBase *g);
284 void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g,
285 struct virtio_gpu_resp_display_info *dpy_info);
287 void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout,
288 struct virtio_gpu_resp_edid *edid);
289 /* virtio-gpu.c */
290 struct virtio_gpu_simple_resource *
291 virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id);
293 void virtio_gpu_ctrl_response(VirtIOGPU *g,
294 struct virtio_gpu_ctrl_command *cmd,
295 struct virtio_gpu_ctrl_hdr *resp,
296 size_t resp_len);
297 void virtio_gpu_ctrl_response_nodata(VirtIOGPU *g,
298 struct virtio_gpu_ctrl_command *cmd,
299 enum virtio_gpu_ctrl_type type);
300 void virtio_gpu_get_display_info(VirtIOGPU *g,
301 struct virtio_gpu_ctrl_command *cmd);
302 void virtio_gpu_get_edid(VirtIOGPU *g,
303 struct virtio_gpu_ctrl_command *cmd);
304 int virtio_gpu_create_mapping_iov(VirtIOGPU *g,
305 uint32_t nr_entries, uint32_t offset,
306 struct virtio_gpu_ctrl_command *cmd,
307 uint64_t **addr, struct iovec **iov,
308 uint32_t *niov);
309 void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g,
310 struct iovec *iov, uint32_t count);
311 void virtio_gpu_cleanup_mapping(VirtIOGPU *g,
312 struct virtio_gpu_simple_resource *res);
313 void virtio_gpu_process_cmdq(VirtIOGPU *g);
314 void virtio_gpu_device_realize(DeviceState *qdev, Error **errp);
315 void virtio_gpu_reset(VirtIODevice *vdev);
316 void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd);
317 void virtio_gpu_update_cursor_data(VirtIOGPU *g,
318 struct virtio_gpu_scanout *s,
319 uint32_t resource_id);
321 /* virtio-gpu-udmabuf.c */
322 bool virtio_gpu_have_udmabuf(void);
323 void virtio_gpu_init_udmabuf(struct virtio_gpu_simple_resource *res);
324 void virtio_gpu_fini_udmabuf(struct virtio_gpu_simple_resource *res);
325 int virtio_gpu_update_dmabuf(VirtIOGPU *g,
326 uint32_t scanout_id,
327 struct virtio_gpu_simple_resource *res,
328 struct virtio_gpu_framebuffer *fb,
329 struct virtio_gpu_rect *r);
331 /* virtio-gpu-3d.c */
332 void virtio_gpu_virgl_process_cmd(VirtIOGPU *g,
333 struct virtio_gpu_ctrl_command *cmd);
334 void virtio_gpu_virgl_fence_poll(VirtIOGPU *g);
335 void virtio_gpu_virgl_reset_scanout(VirtIOGPU *g);
336 void virtio_gpu_virgl_reset(VirtIOGPU *g);
337 int virtio_gpu_virgl_init(VirtIOGPU *g);
338 int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g);
340 #endif