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Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / target / arm / tcg / cpu32.c
blob20c2737f17bcfb3135ea0c969f5f8e0f4b4eaba9
1 /*
2 * QEMU ARM TCG-only CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
14 #include "internals.h"
15 #include "target/arm/idau.h"
16 #if !defined(CONFIG_USER_ONLY)
17 #include "hw/boards.h"
18 #endif
19 #include "cpregs.h"
20
21
22 /* Share AArch32 -cpu max features with AArch64. */
23 void aa32_max_features(ARMCPU *cpu)
24 {
25 uint32_t t;
26
27 /* Add additional features supported by QEMU */
28 t = cpu->isar.id_isar5;
29 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
30 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
31 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
32 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
33 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
34 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
35 cpu->isar.id_isar5 = t;
36
37 t = cpu->isar.id_isar6;
38 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
39 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
40 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
41 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
42 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
43 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
44 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
45 cpu->isar.id_isar6 = t;
46
47 t = cpu->isar.mvfr1;
48 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
49 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
50 cpu->isar.mvfr1 = t;
51
52 t = cpu->isar.mvfr2;
53 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
54 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
55 cpu->isar.mvfr2 = t;
56
57 t = cpu->isar.id_mmfr3;
58 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
59 cpu->isar.id_mmfr3 = t;
60
61 t = cpu->isar.id_mmfr4;
62 t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
63 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
64 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
65 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
66 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
67 cpu->isar.id_mmfr4 = t;
68
69 t = cpu->isar.id_mmfr5;
70 t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
71 cpu->isar.id_mmfr5 = t;
72
73 t = cpu->isar.id_pfr0;
74 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
75 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
76 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
77 cpu->isar.id_pfr0 = t;
78
79 t = cpu->isar.id_pfr2;
80 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
81 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
82 cpu->isar.id_pfr2 = t;
83
84 t = cpu->isar.id_dfr0;
85 t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
86 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
87 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
88 cpu->isar.id_dfr0 = t;
89
90 /* Debug ID registers. */
91
92 /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */
93 t = 0x00008000;
94 t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
95 t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
96 t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
97 t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
98 t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
99 t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
100 cpu->isar.dbgdidr = t;
101
102 t = 0;
103 t = FIELD_DP32(t, DBGDEVID, PCSAMPLE, 3);
104 t = FIELD_DP32(t, DBGDEVID, WPADDRMASK, 1);
105 t = FIELD_DP32(t, DBGDEVID, BPADDRMASK, 15);
106 t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0);
107 t = FIELD_DP32(t, DBGDEVID, VIRTEXTNS, 1);
108 t = FIELD_DP32(t, DBGDEVID, DOUBLELOCK, 1);
109 t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0);
110 t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0);
111 cpu->isar.dbgdevid = t;
112
113 /* Bits[31:4] are RES0. */
114 t = 0;
115 t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
116 cpu->isar.dbgdevid1 = t;
117
118 t = cpu->isar.id_dfr1;
119 t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
120 cpu->isar.id_dfr1 = t;
121 }
122
123 /* CPU models. These are not needed for the AArch64 linux-user build. */
124 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
125
126 static void arm926_initfn(Object *obj)
127 {
128 ARMCPU *cpu = ARM_CPU(obj);
129
130 cpu->dtb_compatible = "arm,arm926";
131 set_feature(&cpu->env, ARM_FEATURE_V5);
132 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
133 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
134 cpu->midr = 0x41069265;
135 cpu->reset_fpsid = 0x41011090;
136 cpu->ctr = 0x1dd20d2;
137 cpu->reset_sctlr = 0x00090078;
138
139 /*
140 * ARMv5 does not have the ID_ISAR registers, but we can still
141 * set the field to indicate Jazelle support within QEMU.
142 */
143 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
144 /*
145 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
146 * support even though ARMv5 doesn't have this register.
147 */
148 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
149 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
150 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
151 }
152
153 static void arm946_initfn(Object *obj)
154 {
155 ARMCPU *cpu = ARM_CPU(obj);
156
157 cpu->dtb_compatible = "arm,arm946";
158 set_feature(&cpu->env, ARM_FEATURE_V5);
159 set_feature(&cpu->env, ARM_FEATURE_PMSA);
160 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
161 cpu->midr = 0x41059461;
162 cpu->ctr = 0x0f004006;
163 cpu->reset_sctlr = 0x00000078;
164 }
165
166 static void arm1026_initfn(Object *obj)
167 {
168 ARMCPU *cpu = ARM_CPU(obj);
169
170 cpu->dtb_compatible = "arm,arm1026";
171 set_feature(&cpu->env, ARM_FEATURE_V5);
172 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
173 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
174 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
175 cpu->midr = 0x4106a262;
176 cpu->reset_fpsid = 0x410110a0;
177 cpu->ctr = 0x1dd20d2;
178 cpu->reset_sctlr = 0x00090078;
179 cpu->reset_auxcr = 1;
180
181 /*
182 * ARMv5 does not have the ID_ISAR registers, but we can still
183 * set the field to indicate Jazelle support within QEMU.
184 */
185 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
186 /*
187 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
188 * support even though ARMv5 doesn't have this register.
189 */
190 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
191 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
192 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
193
194 {
195 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
196 ARMCPRegInfo ifar = {
197 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
198 .access = PL1_RW,
199 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
200 .resetvalue = 0
201 };
202 define_one_arm_cp_reg(cpu, &ifar);
203 }
204 }
205
206 static void arm1136_r2_initfn(Object *obj)
207 {
208 ARMCPU *cpu = ARM_CPU(obj);
209 /*
210 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
211 * older core than plain "arm1136". In particular this does not
212 * have the v6K features.
213 * These ID register values are correct for 1136 but may be wrong
214 * for 1136_r2 (in particular r0p2 does not actually implement most
215 * of the ID registers).
216 */
217
218 cpu->dtb_compatible = "arm,arm1136";
219 set_feature(&cpu->env, ARM_FEATURE_V6);
220 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
221 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
222 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
223 cpu->midr = 0x4107b362;
224 cpu->reset_fpsid = 0x410120b4;
225 cpu->isar.mvfr0 = 0x11111111;
226 cpu->isar.mvfr1 = 0x00000000;
227 cpu->ctr = 0x1dd20d2;
228 cpu->reset_sctlr = 0x00050078;
229 cpu->isar.id_pfr0 = 0x111;
230 cpu->isar.id_pfr1 = 0x1;
231 cpu->isar.id_dfr0 = 0x2;
232 cpu->id_afr0 = 0x3;
233 cpu->isar.id_mmfr0 = 0x01130003;
234 cpu->isar.id_mmfr1 = 0x10030302;
235 cpu->isar.id_mmfr2 = 0x01222110;
236 cpu->isar.id_isar0 = 0x00140011;
237 cpu->isar.id_isar1 = 0x12002111;
238 cpu->isar.id_isar2 = 0x11231111;
239 cpu->isar.id_isar3 = 0x01102131;
240 cpu->isar.id_isar4 = 0x141;
241 cpu->reset_auxcr = 7;
242 }
243
244 static void arm1136_initfn(Object *obj)
245 {
246 ARMCPU *cpu = ARM_CPU(obj);
247
248 cpu->dtb_compatible = "arm,arm1136";
249 set_feature(&cpu->env, ARM_FEATURE_V6K);
250 set_feature(&cpu->env, ARM_FEATURE_V6);
251 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
252 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
253 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
254 cpu->midr = 0x4117b363;
255 cpu->reset_fpsid = 0x410120b4;
256 cpu->isar.mvfr0 = 0x11111111;
257 cpu->isar.mvfr1 = 0x00000000;
258 cpu->ctr = 0x1dd20d2;
259 cpu->reset_sctlr = 0x00050078;
260 cpu->isar.id_pfr0 = 0x111;
261 cpu->isar.id_pfr1 = 0x1;
262 cpu->isar.id_dfr0 = 0x2;
263 cpu->id_afr0 = 0x3;
264 cpu->isar.id_mmfr0 = 0x01130003;
265 cpu->isar.id_mmfr1 = 0x10030302;
266 cpu->isar.id_mmfr2 = 0x01222110;
267 cpu->isar.id_isar0 = 0x00140011;
268 cpu->isar.id_isar1 = 0x12002111;
269 cpu->isar.id_isar2 = 0x11231111;
270 cpu->isar.id_isar3 = 0x01102131;
271 cpu->isar.id_isar4 = 0x141;
272 cpu->reset_auxcr = 7;
273 }
274
275 static void arm1176_initfn(Object *obj)
276 {
277 ARMCPU *cpu = ARM_CPU(obj);
278
279 cpu->dtb_compatible = "arm,arm1176";
280 set_feature(&cpu->env, ARM_FEATURE_V6K);
281 set_feature(&cpu->env, ARM_FEATURE_VAPA);
282 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
283 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
284 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
285 set_feature(&cpu->env, ARM_FEATURE_EL3);
286 cpu->midr = 0x410fb767;
287 cpu->reset_fpsid = 0x410120b5;
288 cpu->isar.mvfr0 = 0x11111111;
289 cpu->isar.mvfr1 = 0x00000000;
290 cpu->ctr = 0x1dd20d2;
291 cpu->reset_sctlr = 0x00050078;
292 cpu->isar.id_pfr0 = 0x111;
293 cpu->isar.id_pfr1 = 0x11;
294 cpu->isar.id_dfr0 = 0x33;
295 cpu->id_afr0 = 0;
296 cpu->isar.id_mmfr0 = 0x01130003;
297 cpu->isar.id_mmfr1 = 0x10030302;
298 cpu->isar.id_mmfr2 = 0x01222100;
299 cpu->isar.id_isar0 = 0x0140011;
300 cpu->isar.id_isar1 = 0x12002111;
301 cpu->isar.id_isar2 = 0x11231121;
302 cpu->isar.id_isar3 = 0x01102131;
303 cpu->isar.id_isar4 = 0x01141;
304 cpu->reset_auxcr = 7;
305 }
306
307 static void arm11mpcore_initfn(Object *obj)
308 {
309 ARMCPU *cpu = ARM_CPU(obj);
310
311 cpu->dtb_compatible = "arm,arm11mpcore";
312 set_feature(&cpu->env, ARM_FEATURE_V6K);
313 set_feature(&cpu->env, ARM_FEATURE_VAPA);
314 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
315 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
316 cpu->midr = 0x410fb022;
317 cpu->reset_fpsid = 0x410120b4;
318 cpu->isar.mvfr0 = 0x11111111;
319 cpu->isar.mvfr1 = 0x00000000;
320 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
321 cpu->isar.id_pfr0 = 0x111;
322 cpu->isar.id_pfr1 = 0x1;
323 cpu->isar.id_dfr0 = 0;
324 cpu->id_afr0 = 0x2;
325 cpu->isar.id_mmfr0 = 0x01100103;
326 cpu->isar.id_mmfr1 = 0x10020302;
327 cpu->isar.id_mmfr2 = 0x01222000;
328 cpu->isar.id_isar0 = 0x00100011;
329 cpu->isar.id_isar1 = 0x12002111;
330 cpu->isar.id_isar2 = 0x11221011;
331 cpu->isar.id_isar3 = 0x01102131;
332 cpu->isar.id_isar4 = 0x141;
333 cpu->reset_auxcr = 1;
334 }
335
336 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
337 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
338 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
339 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
340 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
341 };
342
343 static void cortex_a8_initfn(Object *obj)
344 {
345 ARMCPU *cpu = ARM_CPU(obj);
346
347 cpu->dtb_compatible = "arm,cortex-a8";
348 set_feature(&cpu->env, ARM_FEATURE_V7);
349 set_feature(&cpu->env, ARM_FEATURE_NEON);
350 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
351 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
352 set_feature(&cpu->env, ARM_FEATURE_EL3);
353 set_feature(&cpu->env, ARM_FEATURE_PMU);
354 cpu->midr = 0x410fc080;
355 cpu->reset_fpsid = 0x410330c0;
356 cpu->isar.mvfr0 = 0x11110222;
357 cpu->isar.mvfr1 = 0x00011111;
358 cpu->ctr = 0x82048004;
359 cpu->reset_sctlr = 0x00c50078;
360 cpu->isar.id_pfr0 = 0x1031;
361 cpu->isar.id_pfr1 = 0x11;
362 cpu->isar.id_dfr0 = 0x400;
363 cpu->id_afr0 = 0;
364 cpu->isar.id_mmfr0 = 0x31100003;
365 cpu->isar.id_mmfr1 = 0x20000000;
366 cpu->isar.id_mmfr2 = 0x01202000;
367 cpu->isar.id_mmfr3 = 0x11;
368 cpu->isar.id_isar0 = 0x00101111;
369 cpu->isar.id_isar1 = 0x12112111;
370 cpu->isar.id_isar2 = 0x21232031;
371 cpu->isar.id_isar3 = 0x11112131;
372 cpu->isar.id_isar4 = 0x00111142;
373 cpu->isar.dbgdidr = 0x15141000;
374 cpu->clidr = (1 << 27) | (2 << 24) | 3;
375 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
376 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
377 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
378 cpu->reset_auxcr = 2;
379 cpu->isar.reset_pmcr_el0 = 0x41002000;
380 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
381 }
382
383 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
384 /*
385 * power_control should be set to maximum latency. Again,
386 * default to 0 and set by private hook
387 */
388 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
389 .access = PL1_RW, .resetvalue = 0,
390 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
392 .access = PL1_RW, .resetvalue = 0,
393 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
394 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
395 .access = PL1_RW, .resetvalue = 0,
396 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
398 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
399 /* TLB lockdown control */
400 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
401 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
402 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
403 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
404 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
406 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
407 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
408 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
409 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
410 };
411
412 static void cortex_a9_initfn(Object *obj)
413 {
414 ARMCPU *cpu = ARM_CPU(obj);
415
416 cpu->dtb_compatible = "arm,cortex-a9";
417 set_feature(&cpu->env, ARM_FEATURE_V7);
418 set_feature(&cpu->env, ARM_FEATURE_NEON);
419 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
420 set_feature(&cpu->env, ARM_FEATURE_EL3);
421 set_feature(&cpu->env, ARM_FEATURE_PMU);
422 /*
423 * Note that A9 supports the MP extensions even for
424 * A9UP and single-core A9MP (which are both different
425 * and valid configurations; we don't model A9UP).
426 */
427 set_feature(&cpu->env, ARM_FEATURE_V7MP);
428 set_feature(&cpu->env, ARM_FEATURE_CBAR);
429 cpu->midr = 0x410fc090;
430 cpu->reset_fpsid = 0x41033090;
431 cpu->isar.mvfr0 = 0x11110222;
432 cpu->isar.mvfr1 = 0x01111111;
433 cpu->ctr = 0x80038003;
434 cpu->reset_sctlr = 0x00c50078;
435 cpu->isar.id_pfr0 = 0x1031;
436 cpu->isar.id_pfr1 = 0x11;
437 cpu->isar.id_dfr0 = 0x000;
438 cpu->id_afr0 = 0;
439 cpu->isar.id_mmfr0 = 0x00100103;
440 cpu->isar.id_mmfr1 = 0x20000000;
441 cpu->isar.id_mmfr2 = 0x01230000;
442 cpu->isar.id_mmfr3 = 0x00002111;
443 cpu->isar.id_isar0 = 0x00101111;
444 cpu->isar.id_isar1 = 0x13112111;
445 cpu->isar.id_isar2 = 0x21232041;
446 cpu->isar.id_isar3 = 0x11112131;
447 cpu->isar.id_isar4 = 0x00111142;
448 cpu->isar.dbgdidr = 0x35141000;
449 cpu->clidr = (1 << 27) | (1 << 24) | 3;
450 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
451 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
452 cpu->isar.reset_pmcr_el0 = 0x41093000;
453 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
454 }
455
456 #ifndef CONFIG_USER_ONLY
457 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
458 {
459 MachineState *ms = MACHINE(qdev_get_machine());
460
461 /*
462 * Linux wants the number of processors from here.
463 * Might as well set the interrupt-controller bit too.
464 */
465 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
466 }
467 #endif
468
469 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
470 #ifndef CONFIG_USER_ONLY
471 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
472 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
473 .writefn = arm_cp_write_ignore, },
474 #endif
475 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
476 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
477 };
478
479 static void cortex_a7_initfn(Object *obj)
480 {
481 ARMCPU *cpu = ARM_CPU(obj);
482
483 cpu->dtb_compatible = "arm,cortex-a7";
484 set_feature(&cpu->env, ARM_FEATURE_V7VE);
485 set_feature(&cpu->env, ARM_FEATURE_NEON);
486 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
487 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
488 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
489 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
490 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
491 set_feature(&cpu->env, ARM_FEATURE_EL2);
492 set_feature(&cpu->env, ARM_FEATURE_EL3);
493 set_feature(&cpu->env, ARM_FEATURE_PMU);
494 cpu->midr = 0x410fc075;
495 cpu->reset_fpsid = 0x41023075;
496 cpu->isar.mvfr0 = 0x10110222;
497 cpu->isar.mvfr1 = 0x11111111;
498 cpu->ctr = 0x84448003;
499 cpu->reset_sctlr = 0x00c50078;
500 cpu->isar.id_pfr0 = 0x00001131;
501 cpu->isar.id_pfr1 = 0x00011011;
502 cpu->isar.id_dfr0 = 0x02010555;
503 cpu->id_afr0 = 0x00000000;
504 cpu->isar.id_mmfr0 = 0x10101105;
505 cpu->isar.id_mmfr1 = 0x40000000;
506 cpu->isar.id_mmfr2 = 0x01240000;
507 cpu->isar.id_mmfr3 = 0x02102211;
508 /*
509 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
510 * table 4-41 gives 0x02101110, which includes the arm div insns.
511 */
512 cpu->isar.id_isar0 = 0x02101110;
513 cpu->isar.id_isar1 = 0x13112111;
514 cpu->isar.id_isar2 = 0x21232041;
515 cpu->isar.id_isar3 = 0x11112131;
516 cpu->isar.id_isar4 = 0x10011142;
517 cpu->isar.dbgdidr = 0x3515f005;
518 cpu->isar.dbgdevid = 0x01110f13;
519 cpu->isar.dbgdevid1 = 0x1;
520 cpu->clidr = 0x0a200023;
521 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
522 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
523 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
524 cpu->isar.reset_pmcr_el0 = 0x41072000;
525 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
526 }
527
528 static void cortex_a15_initfn(Object *obj)
529 {
530 ARMCPU *cpu = ARM_CPU(obj);
531
532 cpu->dtb_compatible = "arm,cortex-a15";
533 set_feature(&cpu->env, ARM_FEATURE_V7VE);
534 set_feature(&cpu->env, ARM_FEATURE_NEON);
535 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
536 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
537 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
538 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
539 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
540 set_feature(&cpu->env, ARM_FEATURE_EL2);
541 set_feature(&cpu->env, ARM_FEATURE_EL3);
542 set_feature(&cpu->env, ARM_FEATURE_PMU);
543 /* r4p0 cpu, not requiring expensive tlb flush errata */
544 cpu->midr = 0x414fc0f0;
545 cpu->revidr = 0x0;
546 cpu->reset_fpsid = 0x410430f0;
547 cpu->isar.mvfr0 = 0x10110222;
548 cpu->isar.mvfr1 = 0x11111111;
549 cpu->ctr = 0x8444c004;
550 cpu->reset_sctlr = 0x00c50078;
551 cpu->isar.id_pfr0 = 0x00001131;
552 cpu->isar.id_pfr1 = 0x00011011;
553 cpu->isar.id_dfr0 = 0x02010555;
554 cpu->id_afr0 = 0x00000000;
555 cpu->isar.id_mmfr0 = 0x10201105;
556 cpu->isar.id_mmfr1 = 0x20000000;
557 cpu->isar.id_mmfr2 = 0x01240000;
558 cpu->isar.id_mmfr3 = 0x02102211;
559 cpu->isar.id_isar0 = 0x02101110;
560 cpu->isar.id_isar1 = 0x13112111;
561 cpu->isar.id_isar2 = 0x21232041;
562 cpu->isar.id_isar3 = 0x11112131;
563 cpu->isar.id_isar4 = 0x10011142;
564 cpu->isar.dbgdidr = 0x3515f021;
565 cpu->isar.dbgdevid = 0x01110f13;
566 cpu->isar.dbgdevid1 = 0x0;
567 cpu->clidr = 0x0a200023;
568 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
569 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
570 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
571 cpu->isar.reset_pmcr_el0 = 0x410F3000;
572 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
573 }
574
575 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
576 /* Dummy the TCM region regs for the moment */
577 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
578 .access = PL1_RW, .type = ARM_CP_CONST },
579 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
580 .access = PL1_RW, .type = ARM_CP_CONST },
581 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
582 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
583 };
584
585 static void cortex_r5_initfn(Object *obj)
586 {
587 ARMCPU *cpu = ARM_CPU(obj);
588
589 set_feature(&cpu->env, ARM_FEATURE_V7);
590 set_feature(&cpu->env, ARM_FEATURE_V7MP);
591 set_feature(&cpu->env, ARM_FEATURE_PMSA);
592 set_feature(&cpu->env, ARM_FEATURE_PMU);
593 cpu->midr = 0x411fc153; /* r1p3 */
594 cpu->isar.id_pfr0 = 0x0131;
595 cpu->isar.id_pfr1 = 0x001;
596 cpu->isar.id_dfr0 = 0x010400;
597 cpu->id_afr0 = 0x0;
598 cpu->isar.id_mmfr0 = 0x0210030;
599 cpu->isar.id_mmfr1 = 0x00000000;
600 cpu->isar.id_mmfr2 = 0x01200000;
601 cpu->isar.id_mmfr3 = 0x0211;
602 cpu->isar.id_isar0 = 0x02101111;
603 cpu->isar.id_isar1 = 0x13112111;
604 cpu->isar.id_isar2 = 0x21232141;
605 cpu->isar.id_isar3 = 0x01112131;
606 cpu->isar.id_isar4 = 0x0010142;
607 cpu->isar.id_isar5 = 0x0;
608 cpu->isar.id_isar6 = 0x0;
609 cpu->mp_is_up = true;
610 cpu->pmsav7_dregion = 16;
611 cpu->isar.reset_pmcr_el0 = 0x41151800;
612 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
613 }
614
615 static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
616 { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15,
617 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
618 { .name = "IMP_ATCMREGIONR",
619 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
620 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
621 { .name = "IMP_BTCMREGIONR",
622 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
623 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
624 { .name = "IMP_CTCMREGIONR",
625 .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2,
626 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
627 { .name = "IMP_CSCTLR",
628 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0,
629 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
630 { .name = "IMP_BPCTLR",
631 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1,
632 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
633 { .name = "IMP_MEMPROTCLR",
634 .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2,
635 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
636 { .name = "IMP_SLAVEPCTLR",
637 .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0,
638 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
639 { .name = "IMP_PERIPHREGIONR",
640 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
641 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
642 { .name = "IMP_FLASHIFREGIONR",
643 .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1,
644 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
645 { .name = "IMP_BUILDOPTR",
646 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
647 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
648 { .name = "IMP_PINOPTR",
649 .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
650 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
651 { .name = "IMP_QOSR",
652 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1,
653 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
654 { .name = "IMP_BUSTIMEOUTR",
655 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2,
656 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
657 { .name = "IMP_INTMONR",
658 .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4,
659 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
660 { .name = "IMP_ICERR0",
661 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0,
662 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
663 { .name = "IMP_ICERR1",
664 .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1,
665 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
666 { .name = "IMP_DCERR0",
667 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0,
668 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
669 { .name = "IMP_DCERR1",
670 .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1,
671 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
672 { .name = "IMP_TCMERR0",
673 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0,
674 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
675 { .name = "IMP_TCMERR1",
676 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1,
677 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
678 { .name = "IMP_TCMSYNDR0",
679 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2,
680 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
681 { .name = "IMP_TCMSYNDR1",
682 .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3,
683 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
684 { .name = "IMP_FLASHERR0",
685 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0,
686 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
687 { .name = "IMP_FLASHERR1",
688 .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1,
689 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
690 { .name = "IMP_CDBGDR0",
691 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0,
692 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
693 { .name = "IMP_CBDGBR1",
694 .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1,
695 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
696 { .name = "IMP_TESTR0",
697 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0,
698 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
699 { .name = "IMP_TESTR1",
700 .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1,
701 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
702 { .name = "IMP_CDBGDCI",
703 .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0,
704 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
705 { .name = "IMP_CDBGDCT",
706 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0,
707 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
708 { .name = "IMP_CDBGICT",
709 .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1,
710 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
711 { .name = "IMP_CDBGDCD",
712 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0,
713 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
714 { .name = "IMP_CDBGICD",
715 .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1,
716 .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
717 };
718
719
720 static void cortex_r52_initfn(Object *obj)
721 {
722 ARMCPU *cpu = ARM_CPU(obj);
723
724 set_feature(&cpu->env, ARM_FEATURE_V8);
725 set_feature(&cpu->env, ARM_FEATURE_EL2);
726 set_feature(&cpu->env, ARM_FEATURE_PMSA);
727 set_feature(&cpu->env, ARM_FEATURE_NEON);
728 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
729 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
730 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
731 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
732 cpu->midr = 0x411fd133; /* r1p3 */
733 cpu->revidr = 0x00000000;
734 cpu->reset_fpsid = 0x41034023;
735 cpu->isar.mvfr0 = 0x10110222;
736 cpu->isar.mvfr1 = 0x12111111;
737 cpu->isar.mvfr2 = 0x00000043;
738 cpu->ctr = 0x8144c004;
739 cpu->reset_sctlr = 0x30c50838;
740 cpu->isar.id_pfr0 = 0x00000131;
741 cpu->isar.id_pfr1 = 0x10111001;
742 cpu->isar.id_dfr0 = 0x03010006;
743 cpu->id_afr0 = 0x00000000;
744 cpu->isar.id_mmfr0 = 0x00211040;
745 cpu->isar.id_mmfr1 = 0x40000000;
746 cpu->isar.id_mmfr2 = 0x01200000;
747 cpu->isar.id_mmfr3 = 0xf0102211;
748 cpu->isar.id_mmfr4 = 0x00000010;
749 cpu->isar.id_isar0 = 0x02101110;
750 cpu->isar.id_isar1 = 0x13112111;
751 cpu->isar.id_isar2 = 0x21232142;
752 cpu->isar.id_isar3 = 0x01112131;
753 cpu->isar.id_isar4 = 0x00010142;
754 cpu->isar.id_isar5 = 0x00010001;
755 cpu->isar.dbgdidr = 0x77168000;
756 cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
757 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
758 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
759
760 cpu->pmsav7_dregion = 16;
761 cpu->pmsav8r_hdregion = 16;
762
763 define_arm_cp_regs(cpu, cortex_r52_cp_reginfo);
764 }
765
766 static void cortex_r5f_initfn(Object *obj)
767 {
768 ARMCPU *cpu = ARM_CPU(obj);
769
770 cortex_r5_initfn(obj);
771 cpu->isar.mvfr0 = 0x10110221;
772 cpu->isar.mvfr1 = 0x00000011;
773 }
774
775 static void ti925t_initfn(Object *obj)
776 {
777 ARMCPU *cpu = ARM_CPU(obj);
778 set_feature(&cpu->env, ARM_FEATURE_V4T);
779 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
780 cpu->midr = ARM_CPUID_TI925T;
781 cpu->ctr = 0x5109149;
782 cpu->reset_sctlr = 0x00000070;
783 }
784
785 static void sa1100_initfn(Object *obj)
786 {
787 ARMCPU *cpu = ARM_CPU(obj);
788
789 cpu->dtb_compatible = "intel,sa1100";
790 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
791 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
792 cpu->midr = 0x4401A11B;
793 cpu->reset_sctlr = 0x00000070;
794 }
795
796 static void sa1110_initfn(Object *obj)
797 {
798 ARMCPU *cpu = ARM_CPU(obj);
799 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
800 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
801 cpu->midr = 0x6901B119;
802 cpu->reset_sctlr = 0x00000070;
803 }
804
805 static void pxa250_initfn(Object *obj)
806 {
807 ARMCPU *cpu = ARM_CPU(obj);
808
809 cpu->dtb_compatible = "marvell,xscale";
810 set_feature(&cpu->env, ARM_FEATURE_V5);
811 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
812 cpu->midr = 0x69052100;
813 cpu->ctr = 0xd172172;
814 cpu->reset_sctlr = 0x00000078;
815 }
816
817 static void pxa255_initfn(Object *obj)
818 {
819 ARMCPU *cpu = ARM_CPU(obj);
820
821 cpu->dtb_compatible = "marvell,xscale";
822 set_feature(&cpu->env, ARM_FEATURE_V5);
823 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
824 cpu->midr = 0x69052d00;
825 cpu->ctr = 0xd172172;
826 cpu->reset_sctlr = 0x00000078;
827 }
828
829 static void pxa260_initfn(Object *obj)
830 {
831 ARMCPU *cpu = ARM_CPU(obj);
832
833 cpu->dtb_compatible = "marvell,xscale";
834 set_feature(&cpu->env, ARM_FEATURE_V5);
835 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
836 cpu->midr = 0x69052903;
837 cpu->ctr = 0xd172172;
838 cpu->reset_sctlr = 0x00000078;
839 }
840
841 static void pxa261_initfn(Object *obj)
842 {
843 ARMCPU *cpu = ARM_CPU(obj);
844
845 cpu->dtb_compatible = "marvell,xscale";
846 set_feature(&cpu->env, ARM_FEATURE_V5);
847 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
848 cpu->midr = 0x69052d05;
849 cpu->ctr = 0xd172172;
850 cpu->reset_sctlr = 0x00000078;
851 }
852
853 static void pxa262_initfn(Object *obj)
854 {
855 ARMCPU *cpu = ARM_CPU(obj);
856
857 cpu->dtb_compatible = "marvell,xscale";
858 set_feature(&cpu->env, ARM_FEATURE_V5);
859 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
860 cpu->midr = 0x69052d06;
861 cpu->ctr = 0xd172172;
862 cpu->reset_sctlr = 0x00000078;
863 }
864
865 static void pxa270a0_initfn(Object *obj)
866 {
867 ARMCPU *cpu = ARM_CPU(obj);
868
869 cpu->dtb_compatible = "marvell,xscale";
870 set_feature(&cpu->env, ARM_FEATURE_V5);
871 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
872 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
873 cpu->midr = 0x69054110;
874 cpu->ctr = 0xd172172;
875 cpu->reset_sctlr = 0x00000078;
876 }
877
878 static void pxa270a1_initfn(Object *obj)
879 {
880 ARMCPU *cpu = ARM_CPU(obj);
881
882 cpu->dtb_compatible = "marvell,xscale";
883 set_feature(&cpu->env, ARM_FEATURE_V5);
884 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
885 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
886 cpu->midr = 0x69054111;
887 cpu->ctr = 0xd172172;
888 cpu->reset_sctlr = 0x00000078;
889 }
890
891 static void pxa270b0_initfn(Object *obj)
892 {
893 ARMCPU *cpu = ARM_CPU(obj);
894
895 cpu->dtb_compatible = "marvell,xscale";
896 set_feature(&cpu->env, ARM_FEATURE_V5);
897 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
898 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
899 cpu->midr = 0x69054112;
900 cpu->ctr = 0xd172172;
901 cpu->reset_sctlr = 0x00000078;
902 }
903
904 static void pxa270b1_initfn(Object *obj)
905 {
906 ARMCPU *cpu = ARM_CPU(obj);
907
908 cpu->dtb_compatible = "marvell,xscale";
909 set_feature(&cpu->env, ARM_FEATURE_V5);
910 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
911 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
912 cpu->midr = 0x69054113;
913 cpu->ctr = 0xd172172;
914 cpu->reset_sctlr = 0x00000078;
915 }
916
917 static void pxa270c0_initfn(Object *obj)
918 {
919 ARMCPU *cpu = ARM_CPU(obj);
920
921 cpu->dtb_compatible = "marvell,xscale";
922 set_feature(&cpu->env, ARM_FEATURE_V5);
923 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
924 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
925 cpu->midr = 0x69054114;
926 cpu->ctr = 0xd172172;
927 cpu->reset_sctlr = 0x00000078;
928 }
929
930 static void pxa270c5_initfn(Object *obj)
931 {
932 ARMCPU *cpu = ARM_CPU(obj);
933
934 cpu->dtb_compatible = "marvell,xscale";
935 set_feature(&cpu->env, ARM_FEATURE_V5);
936 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
937 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
938 cpu->midr = 0x69054117;
939 cpu->ctr = 0xd172172;
940 cpu->reset_sctlr = 0x00000078;
941 }
942
943 #ifndef TARGET_AARCH64
944 /*
945 * -cpu max: a CPU with as many features enabled as our emulation supports.
946 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
947 * this only needs to handle 32 bits, and need not care about KVM.
948 */
949 static void arm_max_initfn(Object *obj)
950 {
951 ARMCPU *cpu = ARM_CPU(obj);
952
953 /* aarch64_a57_initfn, advertising none of the aarch64 features */
954 cpu->dtb_compatible = "arm,cortex-a57";
955 set_feature(&cpu->env, ARM_FEATURE_V8);
956 set_feature(&cpu->env, ARM_FEATURE_NEON);
957 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
958 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
959 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
960 set_feature(&cpu->env, ARM_FEATURE_EL2);
961 set_feature(&cpu->env, ARM_FEATURE_EL3);
962 set_feature(&cpu->env, ARM_FEATURE_PMU);
963 cpu->midr = 0x411fd070;
964 cpu->revidr = 0x00000000;
965 cpu->reset_fpsid = 0x41034070;
966 cpu->isar.mvfr0 = 0x10110222;
967 cpu->isar.mvfr1 = 0x12111111;
968 cpu->isar.mvfr2 = 0x00000043;
969 cpu->ctr = 0x8444c004;
970 cpu->reset_sctlr = 0x00c50838;
971 cpu->isar.id_pfr0 = 0x00000131;
972 cpu->isar.id_pfr1 = 0x00011011;
973 cpu->isar.id_dfr0 = 0x03010066;
974 cpu->id_afr0 = 0x00000000;
975 cpu->isar.id_mmfr0 = 0x10101105;
976 cpu->isar.id_mmfr1 = 0x40000000;
977 cpu->isar.id_mmfr2 = 0x01260000;
978 cpu->isar.id_mmfr3 = 0x02102211;
979 cpu->isar.id_isar0 = 0x02101110;
980 cpu->isar.id_isar1 = 0x13112111;
981 cpu->isar.id_isar2 = 0x21232042;
982 cpu->isar.id_isar3 = 0x01112131;
983 cpu->isar.id_isar4 = 0x00011142;
984 cpu->isar.id_isar5 = 0x00011121;
985 cpu->isar.id_isar6 = 0;
986 cpu->isar.reset_pmcr_el0 = 0x41013000;
987 cpu->clidr = 0x0a200023;
988 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
989 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
990 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
991 define_cortex_a72_a57_a53_cp_reginfo(cpu);
992
993 aa32_max_features(cpu);
994
995 #ifdef CONFIG_USER_ONLY
996 /*
997 * Break with true ARMv8 and add back old-style VFP short-vector support.
998 * Only do this for user-mode, where -cpu max is the default, so that
999 * older v6 and v7 programs are more likely to work without adjustment.
1000 */
1001 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1002 #endif
1003 }
1004 #endif /* !TARGET_AARCH64 */
1005
1006 static const ARMCPUInfo arm_tcg_cpus[] = {
1007 { .name = "arm926", .initfn = arm926_initfn },
1008 { .name = "arm946", .initfn = arm946_initfn },
1009 { .name = "arm1026", .initfn = arm1026_initfn },
1010 /*
1011 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1012 * older core than plain "arm1136". In particular this does not
1013 * have the v6K features.
1014 */
1015 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1016 { .name = "arm1136", .initfn = arm1136_initfn },
1017 { .name = "arm1176", .initfn = arm1176_initfn },
1018 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1019 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1020 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1021 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1022 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1023 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1024 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1025 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1026 { .name = "ti925t", .initfn = ti925t_initfn },
1027 { .name = "sa1100", .initfn = sa1100_initfn },
1028 { .name = "sa1110", .initfn = sa1110_initfn },
1029 { .name = "pxa250", .initfn = pxa250_initfn },
1030 { .name = "pxa255", .initfn = pxa255_initfn },
1031 { .name = "pxa260", .initfn = pxa260_initfn },
1032 { .name = "pxa261", .initfn = pxa261_initfn },
1033 { .name = "pxa262", .initfn = pxa262_initfn },
1034 /* "pxa270" is an alias for "pxa270-a0" */
1035 { .name = "pxa270", .initfn = pxa270a0_initfn },
1036 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1037 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1038 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1039 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1040 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1041 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1042 #ifndef TARGET_AARCH64
1043 { .name = "max", .initfn = arm_max_initfn },
1044 #endif
1045 #ifdef CONFIG_USER_ONLY
1046 { .name = "any", .initfn = arm_max_initfn },
1047 #endif
1048 };
1049
1050 static const TypeInfo idau_interface_type_info = {
1051 .name = TYPE_IDAU_INTERFACE,
1052 .parent = TYPE_INTERFACE,
1053 .class_size = sizeof(IDAUInterfaceClass),
1054 };
1055
1056 static void arm_tcg_cpu_register_types(void)
1057 {
1058 size_t i;
1059
1060 type_register_static(&idau_interface_type_info);
1061 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1062 arm_cpu_register(&arm_tcg_cpus[i]);
1063 }
1064 }
1065
1066 type_init(arm_tcg_cpu_register_types)
1067
1068 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
armbru's QEMU hackery