Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / target / hppa / gdbstub.c
blob0daa52f7af2b9a1a36370acb94b4054d1f25aa6a
1 /*
2 * HPPA gdb server stub
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "gdbstub/helpers.h"
25 * GDB 15 only supports PA1.0 via the remote protocol, and ignores
26 * any provided xml. Which means that any attempt to provide more
27 * data results in "Remote 'g' packet reply is too long".
30 int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
32 CPUHPPAState *env = cpu_env(cs);
33 uint32_t val;
35 switch (n) {
36 case 0:
37 val = cpu_hppa_get_psw(env);
38 break;
39 case 1 ... 31:
40 val = env->gr[n];
41 break;
42 case 32:
43 val = env->cr[CR_SAR];
44 break;
45 case 33:
46 val = env->iaoq_f;
47 break;
48 case 34:
49 val = env->iasq_f >> 32;
50 break;
51 case 35:
52 val = env->iaoq_b;
53 break;
54 case 36:
55 val = env->iasq_b >> 32;
56 break;
57 case 37:
58 val = env->cr[CR_EIEM];
59 break;
60 case 38:
61 val = env->cr[CR_IIR];
62 break;
63 case 39:
64 val = env->cr[CR_ISR];
65 break;
66 case 40:
67 val = env->cr[CR_IOR];
68 break;
69 case 41:
70 val = env->cr[CR_IPSW];
71 break;
72 case 43:
73 val = env->sr[4] >> 32;
74 break;
75 case 44:
76 val = env->sr[0] >> 32;
77 break;
78 case 45:
79 val = env->sr[1] >> 32;
80 break;
81 case 46:
82 val = env->sr[2] >> 32;
83 break;
84 case 47:
85 val = env->sr[3] >> 32;
86 break;
87 case 48:
88 val = env->sr[5] >> 32;
89 break;
90 case 49:
91 val = env->sr[6] >> 32;
92 break;
93 case 50:
94 val = env->sr[7] >> 32;
95 break;
96 case 51:
97 val = env->cr[CR_RC];
98 break;
99 case 52:
100 val = env->cr[CR_PID1];
101 break;
102 case 53:
103 val = env->cr[CR_PID2];
104 break;
105 case 54:
106 val = env->cr[CR_SCRCCR];
107 break;
108 case 55:
109 val = env->cr[CR_PID3];
110 break;
111 case 56:
112 val = env->cr[CR_PID4];
113 break;
114 case 57:
115 val = env->cr[24];
116 break;
117 case 58:
118 val = env->cr[25];
119 break;
120 case 59:
121 val = env->cr[26];
122 break;
123 case 60:
124 val = env->cr[27];
125 break;
126 case 61:
127 val = env->cr[28];
128 break;
129 case 62:
130 val = env->cr[29];
131 break;
132 case 63:
133 val = env->cr[30];
134 break;
135 case 64 ... 127:
136 val = extract64(env->fr[(n - 64) / 2], (n & 1 ? 0 : 32), 32);
137 break;
138 default:
139 if (n < 128) {
140 val = 0;
141 } else {
142 return 0;
144 break;
147 return gdb_get_reg32(mem_buf, val);
150 int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
152 CPUHPPAState *env = cpu_env(cs);
153 uint32_t val = ldl_p(mem_buf);
155 switch (n) {
156 case 0:
157 cpu_hppa_put_psw(env, val);
158 break;
159 case 1 ... 31:
160 env->gr[n] = val;
161 break;
162 case 32:
163 env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31);
164 break;
165 case 33:
166 #ifdef CONFIG_USER_ONLY
167 val |= PRIV_USER;
168 #endif
169 env->iaoq_f = val;
170 break;
171 case 34:
172 env->iasq_f = (uint64_t)val << 32;
173 break;
174 case 35:
175 #ifdef CONFIG_USER_ONLY
176 val |= PRIV_USER;
177 #endif
178 env->iaoq_b = val;
179 break;
180 case 36:
181 env->iasq_b = (uint64_t)val << 32;
182 break;
183 case 37:
184 env->cr[CR_EIEM] = val;
185 break;
186 case 38:
187 env->cr[CR_IIR] = val;
188 break;
189 case 39:
190 env->cr[CR_ISR] = val;
191 break;
192 case 40:
193 env->cr[CR_IOR] = val;
194 break;
195 case 41:
196 env->cr[CR_IPSW] = val;
197 break;
198 case 43:
199 env->sr[4] = (uint64_t)val << 32;
200 break;
201 case 44:
202 env->sr[0] = (uint64_t)val << 32;
203 break;
204 case 45:
205 env->sr[1] = (uint64_t)val << 32;
206 break;
207 case 46:
208 env->sr[2] = (uint64_t)val << 32;
209 break;
210 case 47:
211 env->sr[3] = (uint64_t)val << 32;
212 break;
213 case 48:
214 env->sr[5] = (uint64_t)val << 32;
215 break;
216 case 49:
217 env->sr[6] = (uint64_t)val << 32;
218 break;
219 case 50:
220 env->sr[7] = (uint64_t)val << 32;
221 break;
222 case 51:
223 env->cr[CR_RC] = val;
224 break;
225 case 52:
226 env->cr[CR_PID1] = val;
227 cpu_hppa_change_prot_id(env);
228 break;
229 case 53:
230 env->cr[CR_PID2] = val;
231 cpu_hppa_change_prot_id(env);
232 break;
233 case 54:
234 env->cr[CR_SCRCCR] = val;
235 break;
236 case 55:
237 env->cr[CR_PID3] = val;
238 cpu_hppa_change_prot_id(env);
239 break;
240 case 56:
241 env->cr[CR_PID4] = val;
242 cpu_hppa_change_prot_id(env);
243 break;
244 case 57:
245 env->cr[24] = val;
246 break;
247 case 58:
248 env->cr[25] = val;
249 break;
250 case 59:
251 env->cr[26] = val;
252 break;
253 case 60:
254 env->cr[27] = val;
255 break;
256 case 61:
257 env->cr[28] = val;
258 break;
259 case 62:
260 env->cr[29] = val;
261 break;
262 case 63:
263 env->cr[30] = val;
264 break;
265 case 64:
266 env->fr[0] = deposit64(env->fr[0], 32, 32, val);
267 cpu_hppa_loaded_fr0(env);
268 break;
269 case 65 ... 127:
271 uint64_t *fr = &env->fr[(n - 64) / 2];
272 *fr = deposit64(*fr, (n & 1 ? 0 : 32), 32, val);
274 break;
275 default:
276 if (n >= 128) {
277 return 0;
279 break;
281 return 4;