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Merge tag 'pull-loongarch-20241016' of https://gitlab.com/gaosong/qemu into staging
[qemu/armbru.git] / target / mips / tcg / translate.c
blobd92fc418edda59a1d9387fca1e6a5d05de147ac5
1 /*
2 * MIPS emulation for QEMU - main translation routines
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
7 * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
8 * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2.1 of the License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU Lesser General Public
22 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "translate.h"
27 #include "internal.h"
28 #include "exec/helper-proto.h"
29 #include "exec/translation-block.h"
30 #include "semihosting/semihost.h"
31 #include "trace.h"
32 #include "fpu_helper.h"
33
34 #define HELPER_H "helper.h"
35 #include "exec/helper-info.c.inc"
36 #undef HELPER_H
37
38
39 /*
40 * Many sysemu-only helpers are not reachable for user-only.
41 * Define stub generators here, so that we need not either sprinkle
42 * ifdefs through the translator, nor provide the helper function.
43 */
44 #define STUB_HELPER(NAME, ...) \
45 static inline void gen_helper_##NAME(__VA_ARGS__) \
46 { g_assert_not_reached(); }
47
48 #ifdef CONFIG_USER_ONLY
49 STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg)
50 #endif
51
52 enum {
53 /* indirect opcode tables */
54 OPC_SPECIAL = (0x00 << 26),
55 OPC_REGIMM = (0x01 << 26),
56 OPC_CP0 = (0x10 << 26),
57 OPC_CP2 = (0x12 << 26),
58 OPC_CP3 = (0x13 << 26),
59 OPC_SPECIAL2 = (0x1C << 26),
60 OPC_SPECIAL3 = (0x1F << 26),
61 /* arithmetic with immediate */
62 OPC_ADDI = (0x08 << 26),
63 OPC_ADDIU = (0x09 << 26),
64 OPC_SLTI = (0x0A << 26),
65 OPC_SLTIU = (0x0B << 26),
66 /* logic with immediate */
67 OPC_ANDI = (0x0C << 26),
68 OPC_ORI = (0x0D << 26),
69 OPC_XORI = (0x0E << 26),
70 OPC_LUI = (0x0F << 26),
71 /* arithmetic with immediate */
72 OPC_DADDI = (0x18 << 26),
73 OPC_DADDIU = (0x19 << 26),
74 /* Jump and branches */
75 OPC_J = (0x02 << 26),
76 OPC_JAL = (0x03 << 26),
77 OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
78 OPC_BEQL = (0x14 << 26),
79 OPC_BNE = (0x05 << 26),
80 OPC_BNEL = (0x15 << 26),
81 OPC_BLEZ = (0x06 << 26),
82 OPC_BLEZL = (0x16 << 26),
83 OPC_BGTZ = (0x07 << 26),
84 OPC_BGTZL = (0x17 << 26),
85 OPC_JALX = (0x1D << 26),
86 OPC_DAUI = (0x1D << 26),
87 /* Load and stores */
88 OPC_LDL = (0x1A << 26),
89 OPC_LDR = (0x1B << 26),
90 OPC_LB = (0x20 << 26),
91 OPC_LH = (0x21 << 26),
92 OPC_LWL = (0x22 << 26),
93 OPC_LW = (0x23 << 26),
94 OPC_LWPC = OPC_LW | 0x5,
95 OPC_LBU = (0x24 << 26),
96 OPC_LHU = (0x25 << 26),
97 OPC_LWR = (0x26 << 26),
98 OPC_LWU = (0x27 << 26),
99 OPC_SB = (0x28 << 26),
100 OPC_SH = (0x29 << 26),
101 OPC_SWL = (0x2A << 26),
102 OPC_SW = (0x2B << 26),
103 OPC_SDL = (0x2C << 26),
104 OPC_SDR = (0x2D << 26),
105 OPC_SWR = (0x2E << 26),
106 OPC_LL = (0x30 << 26),
107 OPC_LLD = (0x34 << 26),
108 OPC_LD = (0x37 << 26),
109 OPC_LDPC = OPC_LD | 0x5,
110 OPC_SC = (0x38 << 26),
111 OPC_SCD = (0x3C << 26),
112 OPC_SD = (0x3F << 26),
113 /* Floating point load/store */
114 OPC_LWC1 = (0x31 << 26),
115 OPC_LWC2 = (0x32 << 26),
116 OPC_LDC1 = (0x35 << 26),
117 OPC_LDC2 = (0x36 << 26),
118 OPC_SWC1 = (0x39 << 26),
119 OPC_SWC2 = (0x3A << 26),
120 OPC_SDC1 = (0x3D << 26),
121 OPC_SDC2 = (0x3E << 26),
122 /* Compact Branches */
123 OPC_BLEZALC = (0x06 << 26),
124 OPC_BGEZALC = (0x06 << 26),
125 OPC_BGEUC = (0x06 << 26),
126 OPC_BGTZALC = (0x07 << 26),
127 OPC_BLTZALC = (0x07 << 26),
128 OPC_BLTUC = (0x07 << 26),
129 OPC_BOVC = (0x08 << 26),
130 OPC_BEQZALC = (0x08 << 26),
131 OPC_BEQC = (0x08 << 26),
132 OPC_BLEZC = (0x16 << 26),
133 OPC_BGEZC = (0x16 << 26),
134 OPC_BGEC = (0x16 << 26),
135 OPC_BGTZC = (0x17 << 26),
136 OPC_BLTZC = (0x17 << 26),
137 OPC_BLTC = (0x17 << 26),
138 OPC_BNVC = (0x18 << 26),
139 OPC_BNEZALC = (0x18 << 26),
140 OPC_BNEC = (0x18 << 26),
141 OPC_BC = (0x32 << 26),
142 OPC_BEQZC = (0x36 << 26),
143 OPC_JIC = (0x36 << 26),
144 OPC_BALC = (0x3A << 26),
145 OPC_BNEZC = (0x3E << 26),
146 OPC_JIALC = (0x3E << 26),
147 /* MDMX ASE specific */
148 OPC_MDMX = (0x1E << 26),
149 /* Cache and prefetch */
150 OPC_CACHE = (0x2F << 26),
151 OPC_PREF = (0x33 << 26),
152 /* PC-relative address computation / loads */
153 OPC_PCREL = (0x3B << 26),
154 };
155
156 /* PC-relative address computation / loads */
157 #define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 << 19)))
158 #define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f << 16)))
159 enum {
160 /* Instructions determined by bits 19 and 20 */
161 OPC_ADDIUPC = OPC_PCREL | (0 << 19),
162 R6_OPC_LWPC = OPC_PCREL | (1 << 19),
163 OPC_LWUPC = OPC_PCREL | (2 << 19),
164
165 /* Instructions determined by bits 16 ... 20 */
166 OPC_AUIPC = OPC_PCREL | (0x1e << 16),
167 OPC_ALUIPC = OPC_PCREL | (0x1f << 16),
168
169 /* Other */
170 R6_OPC_LDPC = OPC_PCREL | (6 << 18),
171 };
172
173 /* MIPS special opcodes */
174 #define MASK_SPECIAL(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
175
176 enum {
177 /* Shifts */
178 OPC_SLL = 0x00 | OPC_SPECIAL,
179 /* NOP is SLL r0, r0, 0 */
180 /* SSNOP is SLL r0, r0, 1 */
181 /* EHB is SLL r0, r0, 3 */
182 OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */
183 OPC_ROTR = OPC_SRL | (1 << 21),
184 OPC_SRA = 0x03 | OPC_SPECIAL,
185 OPC_SLLV = 0x04 | OPC_SPECIAL,
186 OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
187 OPC_ROTRV = OPC_SRLV | (1 << 6),
188 OPC_SRAV = 0x07 | OPC_SPECIAL,
189 OPC_DSLLV = 0x14 | OPC_SPECIAL,
190 OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
191 OPC_DROTRV = OPC_DSRLV | (1 << 6),
192 OPC_DSRAV = 0x17 | OPC_SPECIAL,
193 OPC_DSLL = 0x38 | OPC_SPECIAL,
194 OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */
195 OPC_DROTR = OPC_DSRL | (1 << 21),
196 OPC_DSRA = 0x3B | OPC_SPECIAL,
197 OPC_DSLL32 = 0x3C | OPC_SPECIAL,
198 OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */
199 OPC_DROTR32 = OPC_DSRL32 | (1 << 21),
200 OPC_DSRA32 = 0x3F | OPC_SPECIAL,
201 /* Multiplication / division */
202 OPC_MULT = 0x18 | OPC_SPECIAL,
203 OPC_MULTU = 0x19 | OPC_SPECIAL,
204 OPC_DIV = 0x1A | OPC_SPECIAL,
205 OPC_DIVU = 0x1B | OPC_SPECIAL,
206 OPC_DMULT = 0x1C | OPC_SPECIAL,
207 OPC_DMULTU = 0x1D | OPC_SPECIAL,
208 OPC_DDIV = 0x1E | OPC_SPECIAL,
209 OPC_DDIVU = 0x1F | OPC_SPECIAL,
210
211 /* 2 registers arithmetic / logic */
212 OPC_ADD = 0x20 | OPC_SPECIAL,
213 OPC_ADDU = 0x21 | OPC_SPECIAL,
214 OPC_SUB = 0x22 | OPC_SPECIAL,
215 OPC_SUBU = 0x23 | OPC_SPECIAL,
216 OPC_AND = 0x24 | OPC_SPECIAL,
217 OPC_OR = 0x25 | OPC_SPECIAL,
218 OPC_XOR = 0x26 | OPC_SPECIAL,
219 OPC_NOR = 0x27 | OPC_SPECIAL,
220 OPC_SLT = 0x2A | OPC_SPECIAL,
221 OPC_SLTU = 0x2B | OPC_SPECIAL,
222 OPC_DADD = 0x2C | OPC_SPECIAL,
223 OPC_DADDU = 0x2D | OPC_SPECIAL,
224 OPC_DSUB = 0x2E | OPC_SPECIAL,
225 OPC_DSUBU = 0x2F | OPC_SPECIAL,
226 /* Jumps */
227 OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */
228 OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */
229 /* Traps */
230 OPC_TGE = 0x30 | OPC_SPECIAL,
231 OPC_TGEU = 0x31 | OPC_SPECIAL,
232 OPC_TLT = 0x32 | OPC_SPECIAL,
233 OPC_TLTU = 0x33 | OPC_SPECIAL,
234 OPC_TEQ = 0x34 | OPC_SPECIAL,
235 OPC_TNE = 0x36 | OPC_SPECIAL,
236 /* HI / LO registers load & stores */
237 OPC_MFHI = 0x10 | OPC_SPECIAL,
238 OPC_MTHI = 0x11 | OPC_SPECIAL,
239 OPC_MFLO = 0x12 | OPC_SPECIAL,
240 OPC_MTLO = 0x13 | OPC_SPECIAL,
241 /* Conditional moves */
242 OPC_MOVZ = 0x0A | OPC_SPECIAL,
243 OPC_MOVN = 0x0B | OPC_SPECIAL,
244
245 OPC_SELEQZ = 0x35 | OPC_SPECIAL,
246 OPC_SELNEZ = 0x37 | OPC_SPECIAL,
247
248 OPC_MOVCI = 0x01 | OPC_SPECIAL,
249
250 /* Special */
251 OPC_PMON = 0x05 | OPC_SPECIAL, /* unofficial */
252 OPC_SYSCALL = 0x0C | OPC_SPECIAL,
253 OPC_BREAK = 0x0D | OPC_SPECIAL,
254 OPC_SPIM = 0x0E | OPC_SPECIAL, /* unofficial */
255 OPC_SYNC = 0x0F | OPC_SPECIAL,
256
257 OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL,
258 OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL,
259 OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL,
260 OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL,
261 };
262
263 /*
264 * R6 Multiply and Divide instructions have the same opcode
265 * and function field as legacy OPC_MULT[U]/OPC_DIV[U]
266 */
267 #define MASK_R6_MULDIV(op) (MASK_SPECIAL(op) | (op & (0x7ff)))
268
269 enum {
270 R6_OPC_MUL = OPC_MULT | (2 << 6),
271 R6_OPC_MUH = OPC_MULT | (3 << 6),
272 R6_OPC_MULU = OPC_MULTU | (2 << 6),
273 R6_OPC_MUHU = OPC_MULTU | (3 << 6),
274 R6_OPC_DIV = OPC_DIV | (2 << 6),
275 R6_OPC_MOD = OPC_DIV | (3 << 6),
276 R6_OPC_DIVU = OPC_DIVU | (2 << 6),
277 R6_OPC_MODU = OPC_DIVU | (3 << 6),
278
279 R6_OPC_DMUL = OPC_DMULT | (2 << 6),
280 R6_OPC_DMUH = OPC_DMULT | (3 << 6),
281 R6_OPC_DMULU = OPC_DMULTU | (2 << 6),
282 R6_OPC_DMUHU = OPC_DMULTU | (3 << 6),
283 R6_OPC_DDIV = OPC_DDIV | (2 << 6),
284 R6_OPC_DMOD = OPC_DDIV | (3 << 6),
285 R6_OPC_DDIVU = OPC_DDIVU | (2 << 6),
286 R6_OPC_DMODU = OPC_DDIVU | (3 << 6),
287
288 R6_OPC_CLZ = 0x10 | OPC_SPECIAL,
289 R6_OPC_CLO = 0x11 | OPC_SPECIAL,
290 R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
291 R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
292 R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
293 };
294
295 /* REGIMM (rt field) opcodes */
296 #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16)))
297
298 enum {
299 OPC_BLTZ = (0x00 << 16) | OPC_REGIMM,
300 OPC_BLTZL = (0x02 << 16) | OPC_REGIMM,
301 OPC_BGEZ = (0x01 << 16) | OPC_REGIMM,
302 OPC_BGEZL = (0x03 << 16) | OPC_REGIMM,
303 OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM,
304 OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM,
305 OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM,
306 OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM,
307 OPC_TGEI = (0x08 << 16) | OPC_REGIMM,
308 OPC_TGEIU = (0x09 << 16) | OPC_REGIMM,
309 OPC_TLTI = (0x0A << 16) | OPC_REGIMM,
310 OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
311 OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
312 OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
313 OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM,
314 OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
315
316 OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
317 OPC_DATI = (0x1e << 16) | OPC_REGIMM,
318 };
319
320 /* Special2 opcodes */
321 #define MASK_SPECIAL2(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
322
323 enum {
324 /* Multiply & xxx operations */
325 OPC_MADD = 0x00 | OPC_SPECIAL2,
326 OPC_MADDU = 0x01 | OPC_SPECIAL2,
327 OPC_MUL = 0x02 | OPC_SPECIAL2,
328 OPC_MSUB = 0x04 | OPC_SPECIAL2,
329 OPC_MSUBU = 0x05 | OPC_SPECIAL2,
330 /* Loongson 2F */
331 OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
332 OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
333 OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
334 OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
335 OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
336 OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
337 OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
338 OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
339 OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
340 OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
341 OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
342 OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
343 /* Misc */
344 OPC_CLZ = 0x20 | OPC_SPECIAL2,
345 OPC_CLO = 0x21 | OPC_SPECIAL2,
346 OPC_DCLZ = 0x24 | OPC_SPECIAL2,
347 OPC_DCLO = 0x25 | OPC_SPECIAL2,
348 /* Special */
349 OPC_SDBBP = 0x3F | OPC_SPECIAL2,
350 };
351
352 /* Special3 opcodes */
353 #define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
354
355 enum {
356 OPC_EXT = 0x00 | OPC_SPECIAL3,
357 OPC_DEXTM = 0x01 | OPC_SPECIAL3,
358 OPC_DEXTU = 0x02 | OPC_SPECIAL3,
359 OPC_DEXT = 0x03 | OPC_SPECIAL3,
360 OPC_INS = 0x04 | OPC_SPECIAL3,
361 OPC_DINSM = 0x05 | OPC_SPECIAL3,
362 OPC_DINSU = 0x06 | OPC_SPECIAL3,
363 OPC_DINS = 0x07 | OPC_SPECIAL3,
364 OPC_FORK = 0x08 | OPC_SPECIAL3,
365 OPC_YIELD = 0x09 | OPC_SPECIAL3,
366 OPC_BSHFL = 0x20 | OPC_SPECIAL3,
367 OPC_DBSHFL = 0x24 | OPC_SPECIAL3,
368 OPC_RDHWR = 0x3B | OPC_SPECIAL3,
369 OPC_GINV = 0x3D | OPC_SPECIAL3,
370
371 /* Loongson 2E */
372 OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
373 OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
374 OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
375 OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
376 OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
377 OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
378 OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
379 OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
380 OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
381 OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
382 OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
383 OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
384
385 /* MIPS DSP Load */
386 OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
387 /* MIPS DSP Arithmetic */
388 OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
389 OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
390 OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
391 OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
392 /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
393 /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
394 OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
395 OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
396 /* MIPS DSP GPR-Based Shift Sub-class */
397 OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
398 OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
399 /* MIPS DSP Multiply Sub-class insns */
400 /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
401 /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
402 OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
403 OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
404 /* DSP Bit/Manipulation Sub-class */
405 OPC_INSV_DSP = 0x0C | OPC_SPECIAL3,
406 OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3,
407 /* MIPS DSP Append Sub-class */
408 OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3,
409 OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3,
410 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
411 OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3,
412 OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3,
413
414 /* EVA */
415 OPC_LWLE = 0x19 | OPC_SPECIAL3,
416 OPC_LWRE = 0x1A | OPC_SPECIAL3,
417 OPC_CACHEE = 0x1B | OPC_SPECIAL3,
418 OPC_SBE = 0x1C | OPC_SPECIAL3,
419 OPC_SHE = 0x1D | OPC_SPECIAL3,
420 OPC_SCE = 0x1E | OPC_SPECIAL3,
421 OPC_SWE = 0x1F | OPC_SPECIAL3,
422 OPC_SWLE = 0x21 | OPC_SPECIAL3,
423 OPC_SWRE = 0x22 | OPC_SPECIAL3,
424 OPC_PREFE = 0x23 | OPC_SPECIAL3,
425 OPC_LBUE = 0x28 | OPC_SPECIAL3,
426 OPC_LHUE = 0x29 | OPC_SPECIAL3,
427 OPC_LBE = 0x2C | OPC_SPECIAL3,
428 OPC_LHE = 0x2D | OPC_SPECIAL3,
429 OPC_LLE = 0x2E | OPC_SPECIAL3,
430 OPC_LWE = 0x2F | OPC_SPECIAL3,
431
432 /* R6 */
433 R6_OPC_PREF = 0x35 | OPC_SPECIAL3,
434 R6_OPC_CACHE = 0x25 | OPC_SPECIAL3,
435 R6_OPC_LL = 0x36 | OPC_SPECIAL3,
436 R6_OPC_SC = 0x26 | OPC_SPECIAL3,
437 R6_OPC_LLD = 0x37 | OPC_SPECIAL3,
438 R6_OPC_SCD = 0x27 | OPC_SPECIAL3,
439 };
440
441 /* Loongson EXT load/store quad word opcodes */
442 #define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x8020))
443 enum {
444 OPC_GSLQ = 0x0020 | OPC_LWC2,
445 OPC_GSLQC1 = 0x8020 | OPC_LWC2,
446 OPC_GSSHFL = OPC_LWC2,
447 OPC_GSSQ = 0x0020 | OPC_SWC2,
448 OPC_GSSQC1 = 0x8020 | OPC_SWC2,
449 OPC_GSSHFS = OPC_SWC2,
450 };
451
452 /* Loongson EXT shifted load/store opcodes */
453 #define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03f))
454 enum {
455 OPC_GSLWLC1 = 0x4 | OPC_GSSHFL,
456 OPC_GSLWRC1 = 0x5 | OPC_GSSHFL,
457 OPC_GSLDLC1 = 0x6 | OPC_GSSHFL,
458 OPC_GSLDRC1 = 0x7 | OPC_GSSHFL,
459 OPC_GSSWLC1 = 0x4 | OPC_GSSHFS,
460 OPC_GSSWRC1 = 0x5 | OPC_GSSHFS,
461 OPC_GSSDLC1 = 0x6 | OPC_GSSHFS,
462 OPC_GSSDRC1 = 0x7 | OPC_GSSHFS,
463 };
464
465 /* Loongson EXT LDC2/SDC2 opcodes */
466 #define MASK_LOONGSON_LSDC2(op) (MASK_OP_MAJOR(op) | (op & 0x7))
467
468 enum {
469 OPC_GSLBX = 0x0 | OPC_LDC2,
470 OPC_GSLHX = 0x1 | OPC_LDC2,
471 OPC_GSLWX = 0x2 | OPC_LDC2,
472 OPC_GSLDX = 0x3 | OPC_LDC2,
473 OPC_GSLWXC1 = 0x6 | OPC_LDC2,
474 OPC_GSLDXC1 = 0x7 | OPC_LDC2,
475 OPC_GSSBX = 0x0 | OPC_SDC2,
476 OPC_GSSHX = 0x1 | OPC_SDC2,
477 OPC_GSSWX = 0x2 | OPC_SDC2,
478 OPC_GSSDX = 0x3 | OPC_SDC2,
479 OPC_GSSWXC1 = 0x6 | OPC_SDC2,
480 OPC_GSSDXC1 = 0x7 | OPC_SDC2,
481 };
482
483 /* BSHFL opcodes */
484 #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
485
486 enum {
487 OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
488 OPC_SEB = (0x10 << 6) | OPC_BSHFL,
489 OPC_SEH = (0x18 << 6) | OPC_BSHFL,
490 OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
491 OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL,
492 OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL,
493 OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL,
494 OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 00000 */
495 };
496
497 /* DBSHFL opcodes */
498 #define MASK_DBSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
499
500 enum {
501 OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
502 OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
503 OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
504 OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL,
505 OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL,
506 OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL,
507 OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL,
508 OPC_DALIGN_5 = (0x0D << 6) | OPC_DBSHFL,
509 OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL,
510 OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL,
511 OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 00000 */
512 };
513
514 /* MIPS DSP REGIMM opcodes */
515 enum {
516 OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
517 OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
518 };
519
520 #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
521 /* MIPS DSP Load */
522 enum {
523 OPC_LBUX = (0x06 << 6) | OPC_LX_DSP,
524 OPC_LHX = (0x04 << 6) | OPC_LX_DSP,
525 OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
526 OPC_LDX = (0x08 << 6) | OPC_LX_DSP,
527 };
528
529 #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
530 enum {
531 /* MIPS DSP Arithmetic Sub-class */
532 OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
533 OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
534 OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
535 OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
536 OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
537 OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
538 OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
539 OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
540 OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
541 OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
542 OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
543 OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
544 OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
545 OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
546 OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
547 OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
548 OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
549 OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
550 /* MIPS DSP Multiply Sub-class insns */
551 OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP,
552 OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP,
553 OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP,
554 OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP,
555 OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP,
556 OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
557 };
558
559 #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
560 #define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
561 enum {
562 /* MIPS DSP Arithmetic Sub-class */
563 OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
564 OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
565 OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
566 OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
567 OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
568 OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
569 OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
570 OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
571 OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
572 OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
573 OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
574 OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
575 /* MIPS DSP Multiply Sub-class insns */
576 OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP,
577 OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP,
578 OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP,
579 OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP,
580 };
581
582 #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
583 enum {
584 /* MIPS DSP Arithmetic Sub-class */
585 OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
586 OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
587 OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
588 OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
589 OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
590 OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
591 OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
592 OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
593 OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
594 OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
595 OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
596 OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
597 OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
598 /* DSP Bit/Manipulation Sub-class */
599 OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP,
600 OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP,
601 OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP,
602 OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP,
603 OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP,
604 };
605
606 #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
607 enum {
608 /* MIPS DSP Arithmetic Sub-class */
609 OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
610 OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
611 OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
612 OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
613 OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
614 OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
615 OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
616 /* DSP Compare-Pick Sub-class */
617 OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP,
618 OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP,
619 OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP,
620 OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP,
621 OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP,
622 OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP,
623 OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP,
624 OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP,
625 OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP,
626 OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP,
627 OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP,
628 OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP,
629 OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP,
630 OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP,
631 OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP,
632 };
633
634 #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
635 enum {
636 /* MIPS DSP GPR-Based Shift Sub-class */
637 OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP,
638 OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP,
639 OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP,
640 OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP,
641 OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP,
642 OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP,
643 OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP,
644 OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP,
645 OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP,
646 OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP,
647 OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP,
648 OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP,
649 OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP,
650 OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP,
651 OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP,
652 OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP,
653 OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP,
654 OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP,
655 OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP,
656 OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP,
657 OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP,
658 OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP,
659 };
660
661 #define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
662 enum {
663 /* MIPS DSP Multiply Sub-class insns */
664 OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP,
665 OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP,
666 OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP,
667 OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP,
668 OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP,
669 OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP,
670 OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP,
671 OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP,
672 OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP,
673 OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP,
674 OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP,
675 OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP,
676 OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP,
677 OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP,
678 OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP,
679 OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP,
680 OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP,
681 OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP,
682 OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP,
683 OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP,
684 OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP,
685 OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP,
686 };
687
688 #define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
689 enum {
690 /* DSP Bit/Manipulation Sub-class */
691 OPC_INSV = (0x00 << 6) | OPC_INSV_DSP,
692 };
693
694 #define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
695 enum {
696 /* MIPS DSP Append Sub-class */
697 OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP,
698 OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP,
699 OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP,
700 };
701
702 #define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
703 enum {
704 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
705 OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP,
706 OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP,
707 OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP,
708 OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP,
709 OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP,
710 OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP,
711 OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP,
712 OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP,
713 OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP,
714 OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP,
715 OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP,
716 OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP,
717 OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP,
718 OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP,
719 OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP,
720 OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP,
721 OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP,
722 };
723
724 #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
725 enum {
726 /* MIPS DSP Arithmetic Sub-class */
727 OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
728 OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
729 OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
730 OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
731 OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
732 OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
733 OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
734 OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
735 OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
736 OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
737 OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
738 OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
739 OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
740 OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
741 OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
742 OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
743 OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
744 /* DSP Bit/Manipulation Sub-class */
745 OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP,
746 OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP,
747 OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP,
748 OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP,
749 OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP,
750 OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP,
751 };
752
753 #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
754 enum {
755 /* MIPS DSP Multiply Sub-class insns */
756 OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP,
757 OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP,
758 OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP,
759 OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP,
760 OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP,
761 /* MIPS DSP Arithmetic Sub-class */
762 OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP,
763 OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP,
764 OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP,
765 OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP,
766 OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP,
767 OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP,
768 OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP,
769 OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP,
770 OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP,
771 OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP,
772 OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP,
773 OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP,
774 OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP,
775 OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP,
776 OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP,
777 OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP,
778 OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP,
779 OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP,
780 OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP,
781 OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP,
782 OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP,
783 };
784
785 #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
786 enum {
787 /* DSP Compare-Pick Sub-class */
788 OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP,
789 OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP,
790 OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP,
791 OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP,
792 OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP,
793 OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP,
794 OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP,
795 OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP,
796 OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP,
797 OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP,
798 OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP,
799 OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP,
800 OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP,
801 OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP,
802 OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP,
803 OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP,
804 OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP,
805 OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP,
806 OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP,
807 /* MIPS DSP Arithmetic Sub-class */
808 OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
809 OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
810 OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
811 OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
812 OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
813 OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
814 OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
815 OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
816 };
817
818 #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
819 enum {
820 /* DSP Append Sub-class */
821 OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP,
822 OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP,
823 OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP,
824 OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP,
825 };
826
827 #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
828 enum {
829 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
830 OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP,
831 OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP,
832 OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP,
833 OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP,
834 OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP,
835 OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP,
836 OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP,
837 OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP,
838 OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP,
839 OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP,
840 OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP,
841 OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP,
842 OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP,
843 OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP,
844 OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP,
845 OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP,
846 OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP,
847 OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP,
848 OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP,
849 OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP,
850 OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP,
851 };
852
853 #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
854 enum {
855 /* DSP Bit/Manipulation Sub-class */
856 OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP,
857 };
858
859 #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
860 enum {
861 /* MIPS DSP Multiply Sub-class insns */
862 OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP,
863 OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP,
864 OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP,
865 OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP,
866 OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP,
867 OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP,
868 OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP,
869 OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP,
870 OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP,
871 OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP,
872 OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP,
873 OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP,
874 OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP,
875 OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP,
876 OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP,
877 OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP,
878 OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP,
879 OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP,
880 OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP,
881 OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP,
882 OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP,
883 OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP,
884 OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP,
885 OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP,
886 OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP,
887 OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP,
888 };
889
890 #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
891 enum {
892 /* MIPS DSP GPR-Based Shift Sub-class */
893 OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP,
894 OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP,
895 OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP,
896 OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP,
897 OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP,
898 OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP,
899 OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP,
900 OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP,
901 OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP,
902 OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP,
903 OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP,
904 OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP,
905 OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP,
906 OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP,
907 OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP,
908 OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP,
909 OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP,
910 OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP,
911 OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP,
912 OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP,
913 OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP,
914 OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP,
915 OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP,
916 OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP,
917 OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP,
918 OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP,
919 };
920
921 /* Coprocessor 0 (rs field) */
922 #define MASK_CP0(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
923
924 enum {
925 OPC_MFC0 = (0x00 << 21) | OPC_CP0,
926 OPC_DMFC0 = (0x01 << 21) | OPC_CP0,
927 OPC_MFHC0 = (0x02 << 21) | OPC_CP0,
928 OPC_MTC0 = (0x04 << 21) | OPC_CP0,
929 OPC_DMTC0 = (0x05 << 21) | OPC_CP0,
930 OPC_MTHC0 = (0x06 << 21) | OPC_CP0,
931 OPC_MFTR = (0x08 << 21) | OPC_CP0,
932 OPC_RDPGPR = (0x0A << 21) | OPC_CP0,
933 OPC_MFMC0 = (0x0B << 21) | OPC_CP0,
934 OPC_MTTR = (0x0C << 21) | OPC_CP0,
935 OPC_WRPGPR = (0x0E << 21) | OPC_CP0,
936 OPC_C0 = (0x10 << 21) | OPC_CP0,
937 OPC_C0_1 = (0x11 << 21) | OPC_CP0,
938 OPC_C0_2 = (0x12 << 21) | OPC_CP0,
939 OPC_C0_3 = (0x13 << 21) | OPC_CP0,
940 OPC_C0_4 = (0x14 << 21) | OPC_CP0,
941 OPC_C0_5 = (0x15 << 21) | OPC_CP0,
942 OPC_C0_6 = (0x16 << 21) | OPC_CP0,
943 OPC_C0_7 = (0x17 << 21) | OPC_CP0,
944 OPC_C0_8 = (0x18 << 21) | OPC_CP0,
945 OPC_C0_9 = (0x19 << 21) | OPC_CP0,
946 OPC_C0_A = (0x1A << 21) | OPC_CP0,
947 OPC_C0_B = (0x1B << 21) | OPC_CP0,
948 OPC_C0_C = (0x1C << 21) | OPC_CP0,
949 OPC_C0_D = (0x1D << 21) | OPC_CP0,
950 OPC_C0_E = (0x1E << 21) | OPC_CP0,
951 OPC_C0_F = (0x1F << 21) | OPC_CP0,
952 };
953
954 /* MFMC0 opcodes */
955 #define MASK_MFMC0(op) (MASK_CP0(op) | (op & 0xFFFF))
956
957 enum {
958 OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
959 OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0,
960 OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0,
961 OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0,
962 OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0,
963 OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0,
964 OPC_DVP = 0x04 | (0 << 3) | (1 << 5) | (0 << 11) | OPC_MFMC0,
965 OPC_EVP = 0x04 | (0 << 3) | (0 << 5) | (0 << 11) | OPC_MFMC0,
966 };
967
968 /* Coprocessor 0 (with rs == C0) */
969 #define MASK_C0(op) (MASK_CP0(op) | (op & 0x3F))
970
971 enum {
972 OPC_TLBR = 0x01 | OPC_C0,
973 OPC_TLBWI = 0x02 | OPC_C0,
974 OPC_TLBINV = 0x03 | OPC_C0,
975 OPC_TLBINVF = 0x04 | OPC_C0,
976 OPC_TLBWR = 0x06 | OPC_C0,
977 OPC_TLBP = 0x08 | OPC_C0,
978 OPC_RFE = 0x10 | OPC_C0,
979 OPC_ERET = 0x18 | OPC_C0,
980 OPC_DERET = 0x1F | OPC_C0,
981 OPC_WAIT = 0x20 | OPC_C0,
982 };
983
984 #define MASK_CP2(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)))
985
986 enum {
987 OPC_MFC2 = (0x00 << 21) | OPC_CP2,
988 OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
989 OPC_CFC2 = (0x02 << 21) | OPC_CP2,
990 OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
991 OPC_MTC2 = (0x04 << 21) | OPC_CP2,
992 OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
993 OPC_CTC2 = (0x06 << 21) | OPC_CP2,
994 OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
995 OPC_BC2 = (0x08 << 21) | OPC_CP2,
996 OPC_BC2EQZ = (0x09 << 21) | OPC_CP2,
997 OPC_BC2NEZ = (0x0D << 21) | OPC_CP2,
998 };
999
1000 #define MASK_LMMI(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | (op & 0x1F))
1001
1002 enum {
1003 OPC_PADDSH = (24 << 21) | (0x00) | OPC_CP2,
1004 OPC_PADDUSH = (25 << 21) | (0x00) | OPC_CP2,
1005 OPC_PADDH = (26 << 21) | (0x00) | OPC_CP2,
1006 OPC_PADDW = (27 << 21) | (0x00) | OPC_CP2,
1007 OPC_PADDSB = (28 << 21) | (0x00) | OPC_CP2,
1008 OPC_PADDUSB = (29 << 21) | (0x00) | OPC_CP2,
1009 OPC_PADDB = (30 << 21) | (0x00) | OPC_CP2,
1010 OPC_PADDD = (31 << 21) | (0x00) | OPC_CP2,
1011
1012 OPC_PSUBSH = (24 << 21) | (0x01) | OPC_CP2,
1013 OPC_PSUBUSH = (25 << 21) | (0x01) | OPC_CP2,
1014 OPC_PSUBH = (26 << 21) | (0x01) | OPC_CP2,
1015 OPC_PSUBW = (27 << 21) | (0x01) | OPC_CP2,
1016 OPC_PSUBSB = (28 << 21) | (0x01) | OPC_CP2,
1017 OPC_PSUBUSB = (29 << 21) | (0x01) | OPC_CP2,
1018 OPC_PSUBB = (30 << 21) | (0x01) | OPC_CP2,
1019 OPC_PSUBD = (31 << 21) | (0x01) | OPC_CP2,
1020
1021 OPC_PSHUFH = (24 << 21) | (0x02) | OPC_CP2,
1022 OPC_PACKSSWH = (25 << 21) | (0x02) | OPC_CP2,
1023 OPC_PACKSSHB = (26 << 21) | (0x02) | OPC_CP2,
1024 OPC_PACKUSHB = (27 << 21) | (0x02) | OPC_CP2,
1025 OPC_XOR_CP2 = (28 << 21) | (0x02) | OPC_CP2,
1026 OPC_NOR_CP2 = (29 << 21) | (0x02) | OPC_CP2,
1027 OPC_AND_CP2 = (30 << 21) | (0x02) | OPC_CP2,
1028 OPC_PANDN = (31 << 21) | (0x02) | OPC_CP2,
1029
1030 OPC_PUNPCKLHW = (24 << 21) | (0x03) | OPC_CP2,
1031 OPC_PUNPCKHHW = (25 << 21) | (0x03) | OPC_CP2,
1032 OPC_PUNPCKLBH = (26 << 21) | (0x03) | OPC_CP2,
1033 OPC_PUNPCKHBH = (27 << 21) | (0x03) | OPC_CP2,
1034 OPC_PINSRH_0 = (28 << 21) | (0x03) | OPC_CP2,
1035 OPC_PINSRH_1 = (29 << 21) | (0x03) | OPC_CP2,
1036 OPC_PINSRH_2 = (30 << 21) | (0x03) | OPC_CP2,
1037 OPC_PINSRH_3 = (31 << 21) | (0x03) | OPC_CP2,
1038
1039 OPC_PAVGH = (24 << 21) | (0x08) | OPC_CP2,
1040 OPC_PAVGB = (25 << 21) | (0x08) | OPC_CP2,
1041 OPC_PMAXSH = (26 << 21) | (0x08) | OPC_CP2,
1042 OPC_PMINSH = (27 << 21) | (0x08) | OPC_CP2,
1043 OPC_PMAXUB = (28 << 21) | (0x08) | OPC_CP2,
1044 OPC_PMINUB = (29 << 21) | (0x08) | OPC_CP2,
1045
1046 OPC_PCMPEQW = (24 << 21) | (0x09) | OPC_CP2,
1047 OPC_PCMPGTW = (25 << 21) | (0x09) | OPC_CP2,
1048 OPC_PCMPEQH = (26 << 21) | (0x09) | OPC_CP2,
1049 OPC_PCMPGTH = (27 << 21) | (0x09) | OPC_CP2,
1050 OPC_PCMPEQB = (28 << 21) | (0x09) | OPC_CP2,
1051 OPC_PCMPGTB = (29 << 21) | (0x09) | OPC_CP2,
1052
1053 OPC_PSLLW = (24 << 21) | (0x0A) | OPC_CP2,
1054 OPC_PSLLH = (25 << 21) | (0x0A) | OPC_CP2,
1055 OPC_PMULLH = (26 << 21) | (0x0A) | OPC_CP2,
1056 OPC_PMULHH = (27 << 21) | (0x0A) | OPC_CP2,
1057 OPC_PMULUW = (28 << 21) | (0x0A) | OPC_CP2,
1058 OPC_PMULHUH = (29 << 21) | (0x0A) | OPC_CP2,
1059
1060 OPC_PSRLW = (24 << 21) | (0x0B) | OPC_CP2,
1061 OPC_PSRLH = (25 << 21) | (0x0B) | OPC_CP2,
1062 OPC_PSRAW = (26 << 21) | (0x0B) | OPC_CP2,
1063 OPC_PSRAH = (27 << 21) | (0x0B) | OPC_CP2,
1064 OPC_PUNPCKLWD = (28 << 21) | (0x0B) | OPC_CP2,
1065 OPC_PUNPCKHWD = (29 << 21) | (0x0B) | OPC_CP2,
1066
1067 OPC_ADDU_CP2 = (24 << 21) | (0x0C) | OPC_CP2,
1068 OPC_OR_CP2 = (25 << 21) | (0x0C) | OPC_CP2,
1069 OPC_ADD_CP2 = (26 << 21) | (0x0C) | OPC_CP2,
1070 OPC_DADD_CP2 = (27 << 21) | (0x0C) | OPC_CP2,
1071 OPC_SEQU_CP2 = (28 << 21) | (0x0C) | OPC_CP2,
1072 OPC_SEQ_CP2 = (29 << 21) | (0x0C) | OPC_CP2,
1073
1074 OPC_SUBU_CP2 = (24 << 21) | (0x0D) | OPC_CP2,
1075 OPC_PASUBUB = (25 << 21) | (0x0D) | OPC_CP2,
1076 OPC_SUB_CP2 = (26 << 21) | (0x0D) | OPC_CP2,
1077 OPC_DSUB_CP2 = (27 << 21) | (0x0D) | OPC_CP2,
1078 OPC_SLTU_CP2 = (28 << 21) | (0x0D) | OPC_CP2,
1079 OPC_SLT_CP2 = (29 << 21) | (0x0D) | OPC_CP2,
1080
1081 OPC_SLL_CP2 = (24 << 21) | (0x0E) | OPC_CP2,
1082 OPC_DSLL_CP2 = (25 << 21) | (0x0E) | OPC_CP2,
1083 OPC_PEXTRH = (26 << 21) | (0x0E) | OPC_CP2,
1084 OPC_PMADDHW = (27 << 21) | (0x0E) | OPC_CP2,
1085 OPC_SLEU_CP2 = (28 << 21) | (0x0E) | OPC_CP2,
1086 OPC_SLE_CP2 = (29 << 21) | (0x0E) | OPC_CP2,
1087
1088 OPC_SRL_CP2 = (24 << 21) | (0x0F) | OPC_CP2,
1089 OPC_DSRL_CP2 = (25 << 21) | (0x0F) | OPC_CP2,
1090 OPC_SRA_CP2 = (26 << 21) | (0x0F) | OPC_CP2,
1091 OPC_DSRA_CP2 = (27 << 21) | (0x0F) | OPC_CP2,
1092 OPC_BIADD = (28 << 21) | (0x0F) | OPC_CP2,
1093 OPC_PMOVMSKB = (29 << 21) | (0x0F) | OPC_CP2,
1094 };
1095
1096
1097 #define MASK_CP3(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
1098
1099 enum {
1100 OPC_LWXC1 = 0x00 | OPC_CP3,
1101 OPC_LDXC1 = 0x01 | OPC_CP3,
1102 OPC_LUXC1 = 0x05 | OPC_CP3,
1103 OPC_SWXC1 = 0x08 | OPC_CP3,
1104 OPC_SDXC1 = 0x09 | OPC_CP3,
1105 OPC_SUXC1 = 0x0D | OPC_CP3,
1106 OPC_PREFX = 0x0F | OPC_CP3,
1107 OPC_ALNV_PS = 0x1E | OPC_CP3,
1108 OPC_MADD_S = 0x20 | OPC_CP3,
1109 OPC_MADD_D = 0x21 | OPC_CP3,
1110 OPC_MADD_PS = 0x26 | OPC_CP3,
1111 OPC_MSUB_S = 0x28 | OPC_CP3,
1112 OPC_MSUB_D = 0x29 | OPC_CP3,
1113 OPC_MSUB_PS = 0x2E | OPC_CP3,
1114 OPC_NMADD_S = 0x30 | OPC_CP3,
1115 OPC_NMADD_D = 0x31 | OPC_CP3,
1116 OPC_NMADD_PS = 0x36 | OPC_CP3,
1117 OPC_NMSUB_S = 0x38 | OPC_CP3,
1118 OPC_NMSUB_D = 0x39 | OPC_CP3,
1119 OPC_NMSUB_PS = 0x3E | OPC_CP3,
1120 };
1121
1122 /*
1123 * MMI (MultiMedia Instruction) encodings
1124 * ======================================
1125 *
1126 * MMI instructions encoding table keys:
1127 *
1128 * * This code is reserved for future use. An attempt to execute it
1129 * causes a Reserved Instruction exception.
1130 * % This code indicates an instruction class. The instruction word
1131 * must be further decoded by examining additional tables that show
1132 * the values for other instruction fields.
1133 * # This code is reserved for the unsupported instructions DMULT,
1134 * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
1135 * to execute it causes a Reserved Instruction exception.
1136 *
1137 * MMI instructions encoded by opcode field (MMI, LQ, SQ):
1138 *
1139 * 31 26 0
1140 * +--------+----------------------------------------+
1141 * | opcode | |
1142 * +--------+----------------------------------------+
1143 *
1144 * opcode bits 28..26
1145 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
1146 * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
1147 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1148 * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
1149 * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
1150 * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
1151 * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
1152 * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
1153 * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
1154 * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
1155 * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
1156 */
1157
1158 enum {
1159 MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
1160 MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
1161 };
1162
1163 /*
1164 * MMI instructions with opcode field = MMI:
1165 *
1166 * 31 26 5 0
1167 * +--------+-------------------------------+--------+
1168 * | MMI | |function|
1169 * +--------+-------------------------------+--------+
1170 *
1171 * function bits 2..0
1172 * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
1173 * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
1174 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1175 * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
1176 * 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
1177 * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
1178 * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
1179 * 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
1180 * 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
1181 * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
1182 * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
1183 */
1184
1185 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
1186 enum {
1187 MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */
1188 MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */
1189 MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */
1190 MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */
1191 MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */
1192 MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */
1193 MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI,
1194 MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI,
1195 };
1196
1197 /* global register indices */
1198 TCGv cpu_gpr[32], cpu_PC;
1199 /*
1200 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
1201 * and the upper halves in cpu_gpr_hi[].
1202 */
1203 TCGv_i64 cpu_gpr_hi[32];
1204 TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
1205 static TCGv cpu_dspctrl, btarget;
1206 TCGv bcond;
1207 static TCGv cpu_lladdr, cpu_llval;
1208 static TCGv_i32 hflags;
1209 TCGv_i32 fpu_fcr0, fpu_fcr31;
1210 TCGv_i64 fpu_f64[32];
1211
1212 static const char regnames_HI[][4] = {
1213 "HI0", "HI1", "HI2", "HI3",
1214 };
1215
1216 static const char regnames_LO[][4] = {
1217 "LO0", "LO1", "LO2", "LO3",
1218 };
1219
1220 /* General purpose registers moves. */
1221 void gen_load_gpr(TCGv t, int reg)
1222 {
1223 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
1224 if (reg == 0) {
1225 tcg_gen_movi_tl(t, 0);
1226 } else {
1227 tcg_gen_mov_tl(t, cpu_gpr[reg]);
1228 }
1229 }
1230
1231 void gen_store_gpr(TCGv t, int reg)
1232 {
1233 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
1234 if (reg != 0) {
1235 tcg_gen_mov_tl(cpu_gpr[reg], t);
1236 }
1237 }
1238
1239 #if defined(TARGET_MIPS64)
1240 void gen_load_gpr_hi(TCGv_i64 t, int reg)
1241 {
1242 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi));
1243 if (reg == 0) {
1244 tcg_gen_movi_i64(t, 0);
1245 } else {
1246 tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
1247 }
1248 }
1249
1250 void gen_store_gpr_hi(TCGv_i64 t, int reg)
1251 {
1252 assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi));
1253 if (reg != 0) {
1254 tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
1255 }
1256 }
1257 #endif /* TARGET_MIPS64 */
1258
1259 /* Moves to/from shadow registers. */
1260 static inline void gen_load_srsgpr(int from, int to)
1261 {
1262 TCGv t0 = tcg_temp_new();
1263
1264 if (from == 0) {
1265 tcg_gen_movi_tl(t0, 0);
1266 } else {
1267 TCGv_i32 t2 = tcg_temp_new_i32();
1268 TCGv_ptr addr = tcg_temp_new_ptr();
1269
1270 tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1271 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1272 tcg_gen_andi_i32(t2, t2, 0xf);
1273 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1274 tcg_gen_ext_i32_ptr(addr, t2);
1275 tcg_gen_add_ptr(addr, tcg_env, addr);
1276
1277 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
1278 }
1279 gen_store_gpr(t0, to);
1280 }
1281
1282 static inline void gen_store_srsgpr(int from, int to)
1283 {
1284 if (to != 0) {
1285 TCGv t0 = tcg_temp_new();
1286 TCGv_i32 t2 = tcg_temp_new_i32();
1287 TCGv_ptr addr = tcg_temp_new_ptr();
1288
1289 gen_load_gpr(t0, from);
1290 tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl));
1291 tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
1292 tcg_gen_andi_i32(t2, t2, 0xf);
1293 tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
1294 tcg_gen_ext_i32_ptr(addr, t2);
1295 tcg_gen_add_ptr(addr, tcg_env, addr);
1296
1297 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
1298 }
1299 }
1300
1301 /* Tests */
1302 static inline void gen_save_pc(target_ulong pc)
1303 {
1304 tcg_gen_movi_tl(cpu_PC, pc);
1305 }
1306
1307 static inline void save_cpu_state(DisasContext *ctx, int do_save_pc)
1308 {
1309 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
1310 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) {
1311 gen_save_pc(ctx->base.pc_next);
1312 ctx->saved_pc = ctx->base.pc_next;
1313 }
1314 if (ctx->hflags != ctx->saved_hflags) {
1315 tcg_gen_movi_i32(hflags, ctx->hflags);
1316 ctx->saved_hflags = ctx->hflags;
1317 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1318 case MIPS_HFLAG_BR:
1319 break;
1320 case MIPS_HFLAG_BC:
1321 case MIPS_HFLAG_BL:
1322 case MIPS_HFLAG_B:
1323 tcg_gen_movi_tl(btarget, ctx->btarget);
1324 break;
1325 }
1326 }
1327 }
1328
1329 static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
1330 {
1331 ctx->saved_hflags = ctx->hflags;
1332 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) {
1333 case MIPS_HFLAG_BR:
1334 break;
1335 case MIPS_HFLAG_BC:
1336 case MIPS_HFLAG_BL:
1337 case MIPS_HFLAG_B:
1338 ctx->btarget = env->btarget;
1339 break;
1340 }
1341 }
1342
1343 void generate_exception_err(DisasContext *ctx, int excp, int err)
1344 {
1345 save_cpu_state(ctx, 1);
1346 gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(excp),
1347 tcg_constant_i32(err));
1348 ctx->base.is_jmp = DISAS_NORETURN;
1349 }
1350
1351 void generate_exception(DisasContext *ctx, int excp)
1352 {
1353 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
1354 }
1355
1356 void generate_exception_end(DisasContext *ctx, int excp)
1357 {
1358 generate_exception_err(ctx, excp, 0);
1359 }
1360
1361 void generate_exception_break(DisasContext *ctx, int code)
1362 {
1363 #ifdef CONFIG_USER_ONLY
1364 /* Pass the break code along to cpu_loop. */
1365 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
1366 offsetof(CPUMIPSState, error_code));
1367 #endif
1368 generate_exception_end(ctx, EXCP_BREAK);
1369 }
1370
1371 void gen_reserved_instruction(DisasContext *ctx)
1372 {
1373 generate_exception_end(ctx, EXCP_RI);
1374 }
1375
1376 /* Floating point register moves. */
1377 void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1378 {
1379 if (ctx->hflags & MIPS_HFLAG_FRE) {
1380 generate_exception(ctx, EXCP_RI);
1381 }
1382 tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
1383 }
1384
1385 void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
1386 {
1387 TCGv_i64 t64;
1388 if (ctx->hflags & MIPS_HFLAG_FRE) {
1389 generate_exception(ctx, EXCP_RI);
1390 }
1391 t64 = tcg_temp_new_i64();
1392 tcg_gen_extu_i32_i64(t64, t);
1393 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32);
1394 }
1395
1396 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1397 {
1398 if (ctx->hflags & MIPS_HFLAG_F64) {
1399 tcg_gen_extrh_i64_i32(t, fpu_f64[reg]);
1400 } else {
1401 gen_load_fpr32(ctx, t, reg | 1);
1402 }
1403 }
1404
1405 static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
1406 {
1407 if (ctx->hflags & MIPS_HFLAG_F64) {
1408 TCGv_i64 t64 = tcg_temp_new_i64();
1409 tcg_gen_extu_i32_i64(t64, t);
1410 tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32);
1411 } else {
1412 gen_store_fpr32(ctx, t, reg | 1);
1413 }
1414 }
1415
1416 void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1417 {
1418 if (ctx->hflags & MIPS_HFLAG_F64) {
1419 tcg_gen_mov_i64(t, fpu_f64[reg]);
1420 } else {
1421 tcg_gen_concat32_i64(t, fpu_f64[reg & ~1], fpu_f64[reg | 1]);
1422 }
1423 }
1424
1425 void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
1426 {
1427 if (ctx->hflags & MIPS_HFLAG_F64) {
1428 tcg_gen_mov_i64(fpu_f64[reg], t);
1429 } else {
1430 TCGv_i64 t0;
1431 tcg_gen_deposit_i64(fpu_f64[reg & ~1], fpu_f64[reg & ~1], t, 0, 32);
1432 t0 = tcg_temp_new_i64();
1433 tcg_gen_shri_i64(t0, t, 32);
1434 tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32);
1435 }
1436 }
1437
1438 int get_fp_bit(int cc)
1439 {
1440 if (cc) {
1441 return 24 + cc;
1442 } else {
1443 return 23;
1444 }
1445 }
1446
1447 /* Addresses computation */
1448 void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
1449 {
1450 tcg_gen_add_tl(ret, arg0, arg1);
1451
1452 #if defined(TARGET_MIPS64)
1453 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1454 tcg_gen_ext32s_i64(ret, ret);
1455 }
1456 #endif
1457 }
1458
1459 void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs)
1460 {
1461 tcg_gen_addi_tl(ret, base, ofs);
1462
1463 #if defined(TARGET_MIPS64)
1464 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1465 tcg_gen_ext32s_i64(ret, ret);
1466 }
1467 #endif
1468 }
1469
1470 /* Addresses computation (translation time) */
1471 static target_long addr_add(DisasContext *ctx, target_long base,
1472 target_long offset)
1473 {
1474 target_long sum = base + offset;
1475
1476 #if defined(TARGET_MIPS64)
1477 if (ctx->hflags & MIPS_HFLAG_AWRAP) {
1478 sum = (int32_t)sum;
1479 }
1480 #endif
1481 return sum;
1482 }
1483
1484 /* Sign-extract the low 32-bits to a target_long. */
1485 void gen_move_low32(TCGv ret, TCGv_i64 arg)
1486 {
1487 #if defined(TARGET_MIPS64)
1488 tcg_gen_ext32s_i64(ret, arg);
1489 #else
1490 tcg_gen_extrl_i64_i32(ret, arg);
1491 #endif
1492 }
1493
1494 /* Sign-extract the high 32-bits to a target_long. */
1495 void gen_move_high32(TCGv ret, TCGv_i64 arg)
1496 {
1497 #if defined(TARGET_MIPS64)
1498 tcg_gen_sari_i64(ret, arg, 32);
1499 #else
1500 tcg_gen_extrh_i64_i32(ret, arg);
1501 #endif
1502 }
1503
1504 bool check_cp0_enabled(DisasContext *ctx)
1505 {
1506 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
1507 generate_exception_end(ctx, EXCP_CpU);
1508 return false;
1509 }
1510 return true;
1511 }
1512
1513 void check_cp1_enabled(DisasContext *ctx)
1514 {
1515 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
1516 generate_exception_err(ctx, EXCP_CpU, 1);
1517 }
1518 }
1519
1520 /*
1521 * Verify that the processor is running with COP1X instructions enabled.
1522 * This is associated with the nabla symbol in the MIPS32 and MIPS64
1523 * opcode tables.
1524 */
1525 void check_cop1x(DisasContext *ctx)
1526 {
1527 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
1528 gen_reserved_instruction(ctx);
1529 }
1530 }
1531
1532 /*
1533 * Verify that the processor is running with 64-bit floating-point
1534 * operations enabled.
1535 */
1536 void check_cp1_64bitmode(DisasContext *ctx)
1537 {
1538 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) {
1539 gen_reserved_instruction(ctx);
1540 }
1541 }
1542
1543 /*
1544 * Verify if floating point register is valid; an operation is not defined
1545 * if bit 0 of any register specification is set and the FR bit in the
1546 * Status register equals zero, since the register numbers specify an
1547 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1548 * in the Status register equals one, both even and odd register numbers
1549 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1550 *
1551 * Multiple 64 bit wide registers can be checked by calling
1552 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1553 */
1554 void check_cp1_registers(DisasContext *ctx, int regs)
1555 {
1556 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
1557 gen_reserved_instruction(ctx);
1558 }
1559 }
1560
1561 /*
1562 * Verify that the processor is running with DSP instructions enabled.
1563 * This is enabled by CP0 Status register MX(24) bit.
1564 */
1565 static inline void check_dsp(DisasContext *ctx)
1566 {
1567 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
1568 if (ctx->insn_flags & ASE_DSP) {
1569 generate_exception_end(ctx, EXCP_DSPDIS);
1570 } else {
1571 gen_reserved_instruction(ctx);
1572 }
1573 }
1574 }
1575
1576 static inline void check_dsp_r2(DisasContext *ctx)
1577 {
1578 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) {
1579 if (ctx->insn_flags & ASE_DSP) {
1580 generate_exception_end(ctx, EXCP_DSPDIS);
1581 } else {
1582 gen_reserved_instruction(ctx);
1583 }
1584 }
1585 }
1586
1587 static inline void check_dsp_r3(DisasContext *ctx)
1588 {
1589 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) {
1590 if (ctx->insn_flags & ASE_DSP) {
1591 generate_exception_end(ctx, EXCP_DSPDIS);
1592 } else {
1593 gen_reserved_instruction(ctx);
1594 }
1595 }
1596 }
1597
1598 /*
1599 * This code generates a "reserved instruction" exception if the
1600 * CPU does not support the instruction set corresponding to flags.
1601 */
1602 void check_insn(DisasContext *ctx, uint64_t flags)
1603 {
1604 if (unlikely(!(ctx->insn_flags & flags))) {
1605 gen_reserved_instruction(ctx);
1606 }
1607 }
1608
1609 /*
1610 * This code generates a "reserved instruction" exception if the
1611 * CPU has corresponding flag set which indicates that the instruction
1612 * has been removed.
1613 */
1614 static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
1615 {
1616 if (unlikely(ctx->insn_flags & flags)) {
1617 gen_reserved_instruction(ctx);
1618 }
1619 }
1620
1621 /*
1622 * The Linux kernel traps certain reserved instruction exceptions to
1623 * emulate the corresponding instructions. QEMU is the kernel in user
1624 * mode, so those traps are emulated by accepting the instructions.
1625 *
1626 * A reserved instruction exception is generated for flagged CPUs if
1627 * QEMU runs in system mode.
1628 */
1629 static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
1630 {
1631 #ifndef CONFIG_USER_ONLY
1632 check_insn_opc_removed(ctx, flags);
1633 #endif
1634 }
1635
1636 /*
1637 * This code generates a "reserved instruction" exception if the
1638 * CPU does not support 64-bit paired-single (PS) floating point data type.
1639 */
1640 static inline void check_ps(DisasContext *ctx)
1641 {
1642 if (unlikely(!ctx->ps)) {
1643 generate_exception(ctx, EXCP_RI);
1644 }
1645 check_cp1_64bitmode(ctx);
1646 }
1647
1648 /*
1649 * This code generates a "reserved instruction" exception if cpu is not
1650 * 64-bit or 64-bit instructions are not enabled.
1651 */
1652 void check_mips_64(DisasContext *ctx)
1653 {
1654 if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
1655 gen_reserved_instruction(ctx);
1656 }
1657 }
1658
1659 #ifndef CONFIG_USER_ONLY
1660 static inline void check_mvh(DisasContext *ctx)
1661 {
1662 if (unlikely(!ctx->mvh)) {
1663 generate_exception(ctx, EXCP_RI);
1664 }
1665 }
1666 #endif
1667
1668 /*
1669 * This code generates a "reserved instruction" exception if the
1670 * Config5 XNP bit is set.
1671 */
1672 static inline void check_xnp(DisasContext *ctx)
1673 {
1674 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
1675 gen_reserved_instruction(ctx);
1676 }
1677 }
1678
1679 #ifndef CONFIG_USER_ONLY
1680 /*
1681 * This code generates a "reserved instruction" exception if the
1682 * Config3 PW bit is NOT set.
1683 */
1684 static inline void check_pw(DisasContext *ctx)
1685 {
1686 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
1687 gen_reserved_instruction(ctx);
1688 }
1689 }
1690 #endif
1691
1692 /*
1693 * This code generates a "reserved instruction" exception if the
1694 * Config3 MT bit is NOT set.
1695 */
1696 static inline void check_mt(DisasContext *ctx)
1697 {
1698 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
1699 gen_reserved_instruction(ctx);
1700 }
1701 }
1702
1703 #ifndef CONFIG_USER_ONLY
1704 /*
1705 * This code generates a "coprocessor unusable" exception if CP0 is not
1706 * available, and, if that is not the case, generates a "reserved instruction"
1707 * exception if the Config5 MT bit is NOT set. This is needed for availability
1708 * control of some of MT ASE instructions.
1709 */
1710 static inline void check_cp0_mt(DisasContext *ctx)
1711 {
1712 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
1713 generate_exception_end(ctx, EXCP_CpU);
1714 } else {
1715 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
1716 gen_reserved_instruction(ctx);
1717 }
1718 }
1719 }
1720 #endif
1721
1722 /*
1723 * This code generates a "reserved instruction" exception if the
1724 * Config5 NMS bit is set.
1725 */
1726 static inline void check_nms(DisasContext *ctx)
1727 {
1728 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
1729 gen_reserved_instruction(ctx);
1730 }
1731 }
1732
1733 /*
1734 * This code generates a "reserved instruction" exception if the
1735 * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
1736 * Config2 TL, and Config5 L2C are unset.
1737 */
1738 static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
1739 {
1740 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
1741 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
1742 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
1743 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
1744 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
1745 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
1746 gen_reserved_instruction(ctx);
1747 }
1748 }
1749
1750 /*
1751 * This code generates a "reserved instruction" exception if the
1752 * Config5 EVA bit is NOT set.
1753 */
1754 static inline void check_eva(DisasContext *ctx)
1755 {
1756 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
1757 gen_reserved_instruction(ctx);
1758 }
1759 }
1760
1761
1762 /*
1763 * Define small wrappers for gen_load_fpr* so that we have a uniform
1764 * calling interface for 32 and 64-bit FPRs. No sense in changing
1765 * all callers for gen_load_fpr32 when we need the CTX parameter for
1766 * this one use.
1767 */
1768 #define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(ctx, x, y)
1769 #define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y)
1770 #define FOP_CONDS(type, abs, fmt, ifmt, bits) \
1771 static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \
1772 int ft, int fs, int cc) \
1773 { \
1774 TCGv_i##bits fp0 = tcg_temp_new_i##bits(); \
1775 TCGv_i##bits fp1 = tcg_temp_new_i##bits(); \
1776 switch (ifmt) { \
1777 case FMT_PS: \
1778 check_ps(ctx); \
1779 break; \
1780 case FMT_D: \
1781 if (abs) { \
1782 check_cop1x(ctx); \
1783 } \
1784 check_cp1_registers(ctx, fs | ft); \
1785 break; \
1786 case FMT_S: \
1787 if (abs) { \
1788 check_cop1x(ctx); \
1789 } \
1790 break; \
1791 } \
1792 gen_ldcmp_fpr##bits(ctx, fp0, fs); \
1793 gen_ldcmp_fpr##bits(ctx, fp1, ft); \
1794 switch (n) { \
1795 case 0: \
1796 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); \
1797 break; \
1798 case 1: \
1799 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); \
1800 break; \
1801 case 2: \
1802 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _eq, fp0, fp1, cc); \
1803 break; \
1804 case 3: \
1805 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ueq, fp0, fp1, cc); \
1806 break; \
1807 case 4: \
1808 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _olt, fp0, fp1, cc); \
1809 break; \
1810 case 5: \
1811 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ult, fp0, fp1, cc); \
1812 break; \
1813 case 6: \
1814 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ole, fp0, fp1, cc); \
1815 break; \
1816 case 7: \
1817 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ule, fp0, fp1, cc); \
1818 break; \
1819 case 8: \
1820 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _sf, fp0, fp1, cc); \
1821 break; \
1822 case 9: \
1823 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngle, fp0, fp1, cc); \
1824 break; \
1825 case 10: \
1826 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _seq, fp0, fp1, cc); \
1827 break; \
1828 case 11: \
1829 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngl, fp0, fp1, cc); \
1830 break; \
1831 case 12: \
1832 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _lt, fp0, fp1, cc); \
1833 break; \
1834 case 13: \
1835 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _nge, fp0, fp1, cc); \
1836 break; \
1837 case 14: \
1838 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _le, fp0, fp1, cc); \
1839 break; \
1840 case 15: \
1841 gen_helper_0e2i(cmp ## type ## _ ## fmt ## _ngt, fp0, fp1, cc); \
1842 break; \
1843 default: \
1844 abort(); \
1845 } \
1846 }
1847
1848 FOP_CONDS(, 0, d, FMT_D, 64)
1849 FOP_CONDS(abs, 1, d, FMT_D, 64)
1850 FOP_CONDS(, 0, s, FMT_S, 32)
1851 FOP_CONDS(abs, 1, s, FMT_S, 32)
1852 FOP_CONDS(, 0, ps, FMT_PS, 64)
1853 FOP_CONDS(abs, 1, ps, FMT_PS, 64)
1854 #undef FOP_CONDS
1855
1856 #define FOP_CONDNS(fmt, ifmt, bits, STORE) \
1857 static inline void gen_r6_cmp_ ## fmt(DisasContext *ctx, int n, \
1858 int ft, int fs, int fd) \
1859 { \
1860 TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(); \
1861 TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(); \
1862 if (ifmt == FMT_D) { \
1863 check_cp1_registers(ctx, fs | ft | fd); \
1864 } \
1865 gen_ldcmp_fpr ## bits(ctx, fp0, fs); \
1866 gen_ldcmp_fpr ## bits(ctx, fp1, ft); \
1867 switch (n) { \
1868 case 0: \
1869 gen_helper_r6_cmp_ ## fmt ## _af(fp0, tcg_env, fp0, fp1); \
1870 break; \
1871 case 1: \
1872 gen_helper_r6_cmp_ ## fmt ## _un(fp0, tcg_env, fp0, fp1); \
1873 break; \
1874 case 2: \
1875 gen_helper_r6_cmp_ ## fmt ## _eq(fp0, tcg_env, fp0, fp1); \
1876 break; \
1877 case 3: \
1878 gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, tcg_env, fp0, fp1); \
1879 break; \
1880 case 4: \
1881 gen_helper_r6_cmp_ ## fmt ## _lt(fp0, tcg_env, fp0, fp1); \
1882 break; \
1883 case 5: \
1884 gen_helper_r6_cmp_ ## fmt ## _ult(fp0, tcg_env, fp0, fp1); \
1885 break; \
1886 case 6: \
1887 gen_helper_r6_cmp_ ## fmt ## _le(fp0, tcg_env, fp0, fp1); \
1888 break; \
1889 case 7: \
1890 gen_helper_r6_cmp_ ## fmt ## _ule(fp0, tcg_env, fp0, fp1); \
1891 break; \
1892 case 8: \
1893 gen_helper_r6_cmp_ ## fmt ## _saf(fp0, tcg_env, fp0, fp1); \
1894 break; \
1895 case 9: \
1896 gen_helper_r6_cmp_ ## fmt ## _sun(fp0, tcg_env, fp0, fp1); \
1897 break; \
1898 case 10: \
1899 gen_helper_r6_cmp_ ## fmt ## _seq(fp0, tcg_env, fp0, fp1); \
1900 break; \
1901 case 11: \
1902 gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, tcg_env, fp0, fp1); \
1903 break; \
1904 case 12: \
1905 gen_helper_r6_cmp_ ## fmt ## _slt(fp0, tcg_env, fp0, fp1); \
1906 break; \
1907 case 13: \
1908 gen_helper_r6_cmp_ ## fmt ## _sult(fp0, tcg_env, fp0, fp1); \
1909 break; \
1910 case 14: \
1911 gen_helper_r6_cmp_ ## fmt ## _sle(fp0, tcg_env, fp0, fp1); \
1912 break; \
1913 case 15: \
1914 gen_helper_r6_cmp_ ## fmt ## _sule(fp0, tcg_env, fp0, fp1); \
1915 break; \
1916 case 17: \
1917 gen_helper_r6_cmp_ ## fmt ## _or(fp0, tcg_env, fp0, fp1); \
1918 break; \
1919 case 18: \
1920 gen_helper_r6_cmp_ ## fmt ## _une(fp0, tcg_env, fp0, fp1); \
1921 break; \
1922 case 19: \
1923 gen_helper_r6_cmp_ ## fmt ## _ne(fp0, tcg_env, fp0, fp1); \
1924 break; \
1925 case 25: \
1926 gen_helper_r6_cmp_ ## fmt ## _sor(fp0, tcg_env, fp0, fp1); \
1927 break; \
1928 case 26: \
1929 gen_helper_r6_cmp_ ## fmt ## _sune(fp0, tcg_env, fp0, fp1); \
1930 break; \
1931 case 27: \
1932 gen_helper_r6_cmp_ ## fmt ## _sne(fp0, tcg_env, fp0, fp1); \
1933 break; \
1934 default: \
1935 abort(); \
1936 } \
1937 STORE; \
1938 }
1939
1940 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd))
1941 FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
1942 #undef FOP_CONDNS
1943 #undef gen_ldcmp_fpr32
1944 #undef gen_ldcmp_fpr64
1945
1946 /* load/store instructions. */
1947 #ifdef CONFIG_USER_ONLY
1948 #define OP_LD_ATOMIC(insn, memop) \
1949 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
1950 DisasContext *ctx) \
1951 { \
1952 TCGv t0 = tcg_temp_new(); \
1953 tcg_gen_mov_tl(t0, arg1); \
1954 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
1955 tcg_gen_st_tl(t0, tcg_env, offsetof(CPUMIPSState, lladdr)); \
1956 tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \
1957 }
1958 #else
1959 #define OP_LD_ATOMIC(insn, ignored_memop) \
1960 static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
1961 DisasContext *ctx) \
1962 { \
1963 gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
1964 }
1965 #endif
1966 OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL);
1967 #if defined(TARGET_MIPS64)
1968 OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ);
1969 #endif
1970 #undef OP_LD_ATOMIC
1971
1972 void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
1973 {
1974 if (base == 0) {
1975 tcg_gen_movi_tl(addr, offset);
1976 } else if (offset == 0) {
1977 gen_load_gpr(addr, base);
1978 } else {
1979 tcg_gen_movi_tl(addr, offset);
1980 gen_op_addr_add(ctx, addr, cpu_gpr[base], addr);
1981 }
1982 }
1983
1984 static target_ulong pc_relative_pc(DisasContext *ctx)
1985 {
1986 target_ulong pc = ctx->base.pc_next;
1987
1988 if (ctx->hflags & MIPS_HFLAG_BMASK) {
1989 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4;
1990
1991 pc -= branch_bytes;
1992 }
1993
1994 pc &= ~(target_ulong)3;
1995 return pc;
1996 }
1997
1998 /* LWL or LDL, depending on MemOp. */
1999 static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr,
2000 int mem_idx, MemOp mop)
2001 {
2002 int sizem1 = memop_size(mop) - 1;
2003 TCGv t0 = tcg_temp_new();
2004 TCGv t1 = tcg_temp_new();
2005
2006 /*
2007 * Do a byte access to possibly trigger a page
2008 * fault with the unaligned address.
2009 */
2010 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
2011 tcg_gen_andi_tl(t1, addr, sizem1);
2012 if (!disas_is_bigendian(ctx)) {
2013 tcg_gen_xori_tl(t1, t1, sizem1);
2014 }
2015 tcg_gen_shli_tl(t1, t1, 3);
2016 tcg_gen_andi_tl(t0, addr, ~sizem1);
2017 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop);
2018 tcg_gen_shl_tl(t0, t0, t1);
2019 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1);
2020 tcg_gen_andc_tl(t1, reg, t1);
2021 tcg_gen_or_tl(reg, t0, t1);
2022 }
2023
2024 /* LWR or LDR, depending on MemOp. */
2025 static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
2026 int mem_idx, MemOp mop)
2027 {
2028 int size = memop_size(mop);
2029 int sizem1 = size - 1;
2030 TCGv t0 = tcg_temp_new();
2031 TCGv t1 = tcg_temp_new();
2032
2033 /*
2034 * Do a byte access to possibly trigger a page
2035 * fault with the unaligned address.
2036 */
2037 tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
2038 tcg_gen_andi_tl(t1, addr, sizem1);
2039 if (disas_is_bigendian(ctx)) {
2040 tcg_gen_xori_tl(t1, t1, sizem1);
2041 }
2042 tcg_gen_shli_tl(t1, t1, 3);
2043 tcg_gen_andi_tl(t0, addr, ~sizem1);
2044 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mop);
2045 tcg_gen_shr_tl(t0, t0, t1);
2046 tcg_gen_xori_tl(t1, t1, size * 8 - 1);
2047 tcg_gen_shl_tl(t1, tcg_constant_tl(~1), t1);
2048 tcg_gen_and_tl(t1, reg, t1);
2049 tcg_gen_or_tl(reg, t0, t1);
2050 }
2051
2052 /* Load */
2053 static void gen_ld(DisasContext *ctx, uint32_t opc,
2054 int rt, int base, int offset)
2055 {
2056 TCGv t0, t1;
2057 int mem_idx = ctx->mem_idx;
2058
2059 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F |
2060 INSN_LOONGSON3A)) {
2061 /*
2062 * Loongson CPU uses a load to zero register for prefetch.
2063 * We emulate it as a NOP. On other CPU we must perform the
2064 * actual memory access.
2065 */
2066 return;
2067 }
2068
2069 t0 = tcg_temp_new();
2070 gen_base_offset_addr(ctx, t0, base, offset);
2071
2072 switch (opc) {
2073 #if defined(TARGET_MIPS64)
2074 case OPC_LWU:
2075 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL |
2076 ctx->default_tcg_memop_mask);
2077 gen_store_gpr(t0, rt);
2078 break;
2079 case OPC_LD:
2080 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ |
2081 ctx->default_tcg_memop_mask);
2082 gen_store_gpr(t0, rt);
2083 break;
2084 case OPC_LLD:
2085 case R6_OPC_LLD:
2086 op_ld_lld(t0, t0, mem_idx, ctx);
2087 gen_store_gpr(t0, rt);
2088 break;
2089 case OPC_LDL:
2090 t1 = tcg_temp_new();
2091 gen_load_gpr(t1, rt);
2092 gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
2093 gen_store_gpr(t1, rt);
2094 break;
2095 case OPC_LDR:
2096 t1 = tcg_temp_new();
2097 gen_load_gpr(t1, rt);
2098 gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
2099 gen_store_gpr(t1, rt);
2100 break;
2101 case OPC_LDPC:
2102 t1 = tcg_constant_tl(pc_relative_pc(ctx));
2103 gen_op_addr_add(ctx, t0, t0, t1);
2104 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ);
2105 gen_store_gpr(t0, rt);
2106 break;
2107 #endif
2108 case OPC_LWPC:
2109 t1 = tcg_constant_tl(pc_relative_pc(ctx));
2110 gen_op_addr_add(ctx, t0, t0, t1);
2111 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL);
2112 gen_store_gpr(t0, rt);
2113 break;
2114 case OPC_LWE:
2115 mem_idx = MIPS_HFLAG_UM;
2116 /* fall through */
2117 case OPC_LW:
2118 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL |
2119 ctx->default_tcg_memop_mask);
2120 gen_store_gpr(t0, rt);
2121 break;
2122 case OPC_LHE:
2123 mem_idx = MIPS_HFLAG_UM;
2124 /* fall through */
2125 case OPC_LH:
2126 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW |
2127 ctx->default_tcg_memop_mask);
2128 gen_store_gpr(t0, rt);
2129 break;
2130 case OPC_LHUE:
2131 mem_idx = MIPS_HFLAG_UM;
2132 /* fall through */
2133 case OPC_LHU:
2134 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW |
2135 ctx->default_tcg_memop_mask);
2136 gen_store_gpr(t0, rt);
2137 break;
2138 case OPC_LBE:
2139 mem_idx = MIPS_HFLAG_UM;
2140 /* fall through */
2141 case OPC_LB:
2142 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_SB);
2143 gen_store_gpr(t0, rt);
2144 break;
2145 case OPC_LBUE:
2146 mem_idx = MIPS_HFLAG_UM;
2147 /* fall through */
2148 case OPC_LBU:
2149 tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_UB);
2150 gen_store_gpr(t0, rt);
2151 break;
2152 case OPC_LWLE:
2153 mem_idx = MIPS_HFLAG_UM;
2154 /* fall through */
2155 case OPC_LWL:
2156 t1 = tcg_temp_new();
2157 gen_load_gpr(t1, rt);
2158 gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
2159 tcg_gen_ext32s_tl(t1, t1);
2160 gen_store_gpr(t1, rt);
2161 break;
2162 case OPC_LWRE:
2163 mem_idx = MIPS_HFLAG_UM;
2164 /* fall through */
2165 case OPC_LWR:
2166 t1 = tcg_temp_new();
2167 gen_load_gpr(t1, rt);
2168 gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
2169 tcg_gen_ext32s_tl(t1, t1);
2170 gen_store_gpr(t1, rt);
2171 break;
2172 case OPC_LLE:
2173 mem_idx = MIPS_HFLAG_UM;
2174 /* fall through */
2175 case OPC_LL:
2176 case R6_OPC_LL:
2177 op_ld_ll(t0, t0, mem_idx, ctx);
2178 gen_store_gpr(t0, rt);
2179 break;
2180 }
2181 }
2182
2183 /* Store */
2184 static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
2185 int base, int offset)
2186 {
2187 TCGv t0 = tcg_temp_new();
2188 TCGv t1 = tcg_temp_new();
2189 int mem_idx = ctx->mem_idx;
2190
2191 gen_base_offset_addr(ctx, t0, base, offset);
2192 gen_load_gpr(t1, rt);
2193 switch (opc) {
2194 #if defined(TARGET_MIPS64)
2195 case OPC_SD:
2196 tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ |
2197 ctx->default_tcg_memop_mask);
2198 break;
2199 case OPC_SDL:
2200 gen_helper_0e2i(sdl, t1, t0, mem_idx);
2201 break;
2202 case OPC_SDR:
2203 gen_helper_0e2i(sdr, t1, t0, mem_idx);
2204 break;
2205 #endif
2206 case OPC_SWE:
2207 mem_idx = MIPS_HFLAG_UM;
2208 /* fall through */
2209 case OPC_SW:
2210 tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL |
2211 ctx->default_tcg_memop_mask);
2212 break;
2213 case OPC_SHE:
2214 mem_idx = MIPS_HFLAG_UM;
2215 /* fall through */
2216 case OPC_SH:
2217 tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW |
2218 ctx->default_tcg_memop_mask);
2219 break;
2220 case OPC_SBE:
2221 mem_idx = MIPS_HFLAG_UM;
2222 /* fall through */
2223 case OPC_SB:
2224 tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_8);
2225 break;
2226 case OPC_SWLE:
2227 mem_idx = MIPS_HFLAG_UM;
2228 /* fall through */
2229 case OPC_SWL:
2230 gen_helper_0e2i(swl, t1, t0, mem_idx);
2231 break;
2232 case OPC_SWRE:
2233 mem_idx = MIPS_HFLAG_UM;
2234 /* fall through */
2235 case OPC_SWR:
2236 gen_helper_0e2i(swr, t1, t0, mem_idx);
2237 break;
2238 }
2239 }
2240
2241
2242 /* Store conditional */
2243 static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
2244 MemOp tcg_mo, bool eva)
2245 {
2246 TCGv addr, t0, val;
2247 TCGLabel *l1 = gen_new_label();
2248 TCGLabel *done = gen_new_label();
2249
2250 t0 = tcg_temp_new();
2251 addr = tcg_temp_new();
2252 /* compare the address against that of the preceding LL */
2253 gen_base_offset_addr(ctx, addr, base, offset);
2254 tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
2255 gen_store_gpr(tcg_constant_tl(0), rt);
2256 tcg_gen_br(done);
2257
2258 gen_set_label(l1);
2259 /* generate cmpxchg */
2260 val = tcg_temp_new();
2261 gen_load_gpr(val, rt);
2262 tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval, val,
2263 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo);
2264 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval);
2265 gen_store_gpr(t0, rt);
2266
2267 gen_set_label(done);
2268 }
2269
2270 /* Load and store */
2271 static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
2272 TCGv t0)
2273 {
2274 /*
2275 * Don't do NOP if destination is zero: we must perform the actual
2276 * memory access.
2277 */
2278 switch (opc) {
2279 case OPC_LWC1:
2280 {
2281 TCGv_i32 fp0 = tcg_temp_new_i32();
2282 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
2283 ctx->default_tcg_memop_mask);
2284 gen_store_fpr32(ctx, fp0, ft);
2285 }
2286 break;
2287 case OPC_SWC1:
2288 {
2289 TCGv_i32 fp0 = tcg_temp_new_i32();
2290 gen_load_fpr32(ctx, fp0, ft);
2291 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
2292 ctx->default_tcg_memop_mask);
2293 }
2294 break;
2295 case OPC_LDC1:
2296 {
2297 TCGv_i64 fp0 = tcg_temp_new_i64();
2298 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
2299 ctx->default_tcg_memop_mask);
2300 gen_store_fpr64(ctx, fp0, ft);
2301 }
2302 break;
2303 case OPC_SDC1:
2304 {
2305 TCGv_i64 fp0 = tcg_temp_new_i64();
2306 gen_load_fpr64(ctx, fp0, ft);
2307 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
2308 ctx->default_tcg_memop_mask);
2309 }
2310 break;
2311 default:
2312 MIPS_INVAL("flt_ldst");
2313 gen_reserved_instruction(ctx);
2314 break;
2315 }
2316 }
2317
2318 static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
2319 int rs, int16_t imm)
2320 {
2321 TCGv t0 = tcg_temp_new();
2322
2323 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
2324 check_cp1_enabled(ctx);
2325 switch (op) {
2326 case OPC_LDC1:
2327 case OPC_SDC1:
2328 check_insn(ctx, ISA_MIPS2);
2329 /* Fallthrough */
2330 default:
2331 gen_base_offset_addr(ctx, t0, rs, imm);
2332 gen_flt_ldst(ctx, op, rt, t0);
2333 }
2334 } else {
2335 generate_exception_err(ctx, EXCP_CpU, 1);
2336 }
2337 }
2338
2339 /* Arithmetic with immediate operand */
2340 static void gen_arith_imm(DisasContext *ctx, uint32_t opc,
2341 int rt, int rs, int imm)
2342 {
2343 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2344
2345 if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) {
2346 /*
2347 * If no destination, treat it as a NOP.
2348 * For addi, we must generate the overflow exception when needed.
2349 */
2350 return;
2351 }
2352 switch (opc) {
2353 case OPC_ADDI:
2354 {
2355 TCGv t0 = tcg_temp_new();
2356 TCGv t1 = tcg_temp_new();
2357 TCGv t2 = tcg_temp_new();
2358 TCGLabel *l1 = gen_new_label();
2359
2360 gen_load_gpr(t1, rs);
2361 tcg_gen_addi_tl(t0, t1, uimm);
2362 tcg_gen_ext32s_tl(t0, t0);
2363
2364 tcg_gen_xori_tl(t1, t1, ~uimm);
2365 tcg_gen_xori_tl(t2, t0, uimm);
2366 tcg_gen_and_tl(t1, t1, t2);
2367 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2368 /* operands of same sign, result different sign */
2369 generate_exception(ctx, EXCP_OVERFLOW);
2370 gen_set_label(l1);
2371 tcg_gen_ext32s_tl(t0, t0);
2372 gen_store_gpr(t0, rt);
2373 }
2374 break;
2375 case OPC_ADDIU:
2376 if (rs != 0) {
2377 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2378 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2379 } else {
2380 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2381 }
2382 break;
2383 #if defined(TARGET_MIPS64)
2384 case OPC_DADDI:
2385 {
2386 TCGv t0 = tcg_temp_new();
2387 TCGv t1 = tcg_temp_new();
2388 TCGv t2 = tcg_temp_new();
2389 TCGLabel *l1 = gen_new_label();
2390
2391 gen_load_gpr(t1, rs);
2392 tcg_gen_addi_tl(t0, t1, uimm);
2393
2394 tcg_gen_xori_tl(t1, t1, ~uimm);
2395 tcg_gen_xori_tl(t2, t0, uimm);
2396 tcg_gen_and_tl(t1, t1, t2);
2397 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2398 /* operands of same sign, result different sign */
2399 generate_exception(ctx, EXCP_OVERFLOW);
2400 gen_set_label(l1);
2401 gen_store_gpr(t0, rt);
2402 }
2403 break;
2404 case OPC_DADDIU:
2405 if (rs != 0) {
2406 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2407 } else {
2408 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2409 }
2410 break;
2411 #endif
2412 }
2413 }
2414
2415 /* Logic with immediate operand */
2416 static void gen_logic_imm(DisasContext *ctx, uint32_t opc,
2417 int rt, int rs, int16_t imm)
2418 {
2419 target_ulong uimm;
2420
2421 if (rt == 0) {
2422 /* If no destination, treat it as a NOP. */
2423 return;
2424 }
2425 uimm = (uint16_t)imm;
2426 switch (opc) {
2427 case OPC_ANDI:
2428 if (likely(rs != 0)) {
2429 tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2430 } else {
2431 tcg_gen_movi_tl(cpu_gpr[rt], 0);
2432 }
2433 break;
2434 case OPC_ORI:
2435 if (rs != 0) {
2436 tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2437 } else {
2438 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2439 }
2440 break;
2441 case OPC_XORI:
2442 if (likely(rs != 0)) {
2443 tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
2444 } else {
2445 tcg_gen_movi_tl(cpu_gpr[rt], uimm);
2446 }
2447 break;
2448 case OPC_LUI:
2449 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) {
2450 /* OPC_AUI */
2451 tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16);
2452 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
2453 } else {
2454 tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
2455 }
2456 break;
2457
2458 default:
2459 break;
2460 }
2461 }
2462
2463 /* Set on less than with immediate operand */
2464 static void gen_slt_imm(DisasContext *ctx, uint32_t opc,
2465 int rt, int rs, int16_t imm)
2466 {
2467 target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */
2468 TCGv t0;
2469
2470 if (rt == 0) {
2471 /* If no destination, treat it as a NOP. */
2472 return;
2473 }
2474 t0 = tcg_temp_new();
2475 gen_load_gpr(t0, rs);
2476 switch (opc) {
2477 case OPC_SLTI:
2478 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm);
2479 break;
2480 case OPC_SLTIU:
2481 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm);
2482 break;
2483 }
2484 }
2485
2486 /* Shifts with immediate operand */
2487 static void gen_shift_imm(DisasContext *ctx, uint32_t opc,
2488 int rt, int rs, int16_t imm)
2489 {
2490 target_ulong uimm = ((uint16_t)imm) & 0x1f;
2491 TCGv t0;
2492
2493 if (rt == 0) {
2494 /* If no destination, treat it as a NOP. */
2495 return;
2496 }
2497
2498 t0 = tcg_temp_new();
2499 gen_load_gpr(t0, rs);
2500 switch (opc) {
2501 case OPC_SLL:
2502 tcg_gen_shli_tl(t0, t0, uimm);
2503 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2504 break;
2505 case OPC_SRA:
2506 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2507 break;
2508 case OPC_SRL:
2509 if (uimm != 0) {
2510 tcg_gen_ext32u_tl(t0, t0);
2511 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2512 } else {
2513 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2514 }
2515 break;
2516 case OPC_ROTR:
2517 if (uimm != 0) {
2518 TCGv_i32 t1 = tcg_temp_new_i32();
2519
2520 tcg_gen_trunc_tl_i32(t1, t0);
2521 tcg_gen_rotri_i32(t1, t1, uimm);
2522 tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
2523 } else {
2524 tcg_gen_ext32s_tl(cpu_gpr[rt], t0);
2525 }
2526 break;
2527 #if defined(TARGET_MIPS64)
2528 case OPC_DSLL:
2529 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm);
2530 break;
2531 case OPC_DSRA:
2532 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm);
2533 break;
2534 case OPC_DSRL:
2535 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm);
2536 break;
2537 case OPC_DROTR:
2538 if (uimm != 0) {
2539 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm);
2540 } else {
2541 tcg_gen_mov_tl(cpu_gpr[rt], t0);
2542 }
2543 break;
2544 case OPC_DSLL32:
2545 tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32);
2546 break;
2547 case OPC_DSRA32:
2548 tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32);
2549 break;
2550 case OPC_DSRL32:
2551 tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32);
2552 break;
2553 case OPC_DROTR32:
2554 tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32);
2555 break;
2556 #endif
2557 }
2558 }
2559
2560 /* Arithmetic */
2561 static void gen_arith(DisasContext *ctx, uint32_t opc,
2562 int rd, int rs, int rt)
2563 {
2564 if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB
2565 && opc != OPC_DADD && opc != OPC_DSUB) {
2566 /*
2567 * If no destination, treat it as a NOP.
2568 * For add & sub, we must generate the overflow exception when needed.
2569 */
2570 return;
2571 }
2572
2573 switch (opc) {
2574 case OPC_ADD:
2575 {
2576 TCGv t0 = tcg_temp_new();
2577 TCGv t1 = tcg_temp_new();
2578 TCGv t2 = tcg_temp_new();
2579 TCGLabel *l1 = gen_new_label();
2580
2581 gen_load_gpr(t1, rs);
2582 gen_load_gpr(t2, rt);
2583 tcg_gen_add_tl(t0, t1, t2);
2584 tcg_gen_ext32s_tl(t0, t0);
2585 tcg_gen_xor_tl(t1, t1, t2);
2586 tcg_gen_xor_tl(t2, t0, t2);
2587 tcg_gen_andc_tl(t1, t2, t1);
2588 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2589 /* operands of same sign, result different sign */
2590 generate_exception(ctx, EXCP_OVERFLOW);
2591 gen_set_label(l1);
2592 gen_store_gpr(t0, rd);
2593 }
2594 break;
2595 case OPC_ADDU:
2596 if (rs != 0 && rt != 0) {
2597 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2598 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2599 } else if (rs == 0 && rt != 0) {
2600 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2601 } else if (rs != 0 && rt == 0) {
2602 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2603 } else {
2604 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2605 }
2606 break;
2607 case OPC_SUB:
2608 {
2609 TCGv t0 = tcg_temp_new();
2610 TCGv t1 = tcg_temp_new();
2611 TCGv t2 = tcg_temp_new();
2612 TCGLabel *l1 = gen_new_label();
2613
2614 gen_load_gpr(t1, rs);
2615 gen_load_gpr(t2, rt);
2616 tcg_gen_sub_tl(t0, t1, t2);
2617 tcg_gen_ext32s_tl(t0, t0);
2618 tcg_gen_xor_tl(t2, t1, t2);
2619 tcg_gen_xor_tl(t1, t0, t1);
2620 tcg_gen_and_tl(t1, t1, t2);
2621 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2622 /*
2623 * operands of different sign, first operand and the result
2624 * of different sign
2625 */
2626 generate_exception(ctx, EXCP_OVERFLOW);
2627 gen_set_label(l1);
2628 gen_store_gpr(t0, rd);
2629 }
2630 break;
2631 case OPC_SUBU:
2632 if (rs != 0 && rt != 0) {
2633 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2634 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2635 } else if (rs == 0 && rt != 0) {
2636 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2637 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2638 } else if (rs != 0 && rt == 0) {
2639 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2640 } else {
2641 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2642 }
2643 break;
2644 #if defined(TARGET_MIPS64)
2645 case OPC_DADD:
2646 {
2647 TCGv t0 = tcg_temp_new();
2648 TCGv t1 = tcg_temp_new();
2649 TCGv t2 = tcg_temp_new();
2650 TCGLabel *l1 = gen_new_label();
2651
2652 gen_load_gpr(t1, rs);
2653 gen_load_gpr(t2, rt);
2654 tcg_gen_add_tl(t0, t1, t2);
2655 tcg_gen_xor_tl(t1, t1, t2);
2656 tcg_gen_xor_tl(t2, t0, t2);
2657 tcg_gen_andc_tl(t1, t2, t1);
2658 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2659 /* operands of same sign, result different sign */
2660 generate_exception(ctx, EXCP_OVERFLOW);
2661 gen_set_label(l1);
2662 gen_store_gpr(t0, rd);
2663 }
2664 break;
2665 case OPC_DADDU:
2666 if (rs != 0 && rt != 0) {
2667 tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2668 } else if (rs == 0 && rt != 0) {
2669 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2670 } else if (rs != 0 && rt == 0) {
2671 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2672 } else {
2673 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2674 }
2675 break;
2676 case OPC_DSUB:
2677 {
2678 TCGv t0 = tcg_temp_new();
2679 TCGv t1 = tcg_temp_new();
2680 TCGv t2 = tcg_temp_new();
2681 TCGLabel *l1 = gen_new_label();
2682
2683 gen_load_gpr(t1, rs);
2684 gen_load_gpr(t2, rt);
2685 tcg_gen_sub_tl(t0, t1, t2);
2686 tcg_gen_xor_tl(t2, t1, t2);
2687 tcg_gen_xor_tl(t1, t0, t1);
2688 tcg_gen_and_tl(t1, t1, t2);
2689 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
2690 /*
2691 * Operands of different sign, first operand and result different
2692 * sign.
2693 */
2694 generate_exception(ctx, EXCP_OVERFLOW);
2695 gen_set_label(l1);
2696 gen_store_gpr(t0, rd);
2697 }
2698 break;
2699 case OPC_DSUBU:
2700 if (rs != 0 && rt != 0) {
2701 tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2702 } else if (rs == 0 && rt != 0) {
2703 tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]);
2704 } else if (rs != 0 && rt == 0) {
2705 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2706 } else {
2707 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2708 }
2709 break;
2710 #endif
2711 case OPC_MUL:
2712 if (likely(rs != 0 && rt != 0)) {
2713 tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2714 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
2715 } else {
2716 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2717 }
2718 break;
2719 }
2720 }
2721
2722 /* Conditional move */
2723 static void gen_cond_move(DisasContext *ctx, uint32_t opc,
2724 int rd, int rs, int rt)
2725 {
2726 TCGv t0, t1, t2;
2727
2728 if (rd == 0) {
2729 /* If no destination, treat it as a NOP. */
2730 return;
2731 }
2732
2733 t0 = tcg_temp_new();
2734 gen_load_gpr(t0, rt);
2735 t1 = tcg_constant_tl(0);
2736 t2 = tcg_temp_new();
2737 gen_load_gpr(t2, rs);
2738 switch (opc) {
2739 case OPC_MOVN:
2740 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2741 break;
2742 case OPC_MOVZ:
2743 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
2744 break;
2745 case OPC_SELNEZ:
2746 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1);
2747 break;
2748 case OPC_SELEQZ:
2749 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1);
2750 break;
2751 }
2752 }
2753
2754 /* Logic */
2755 static void gen_logic(DisasContext *ctx, uint32_t opc,
2756 int rd, int rs, int rt)
2757 {
2758 if (rd == 0) {
2759 /* If no destination, treat it as a NOP. */
2760 return;
2761 }
2762
2763 switch (opc) {
2764 case OPC_AND:
2765 if (likely(rs != 0 && rt != 0)) {
2766 tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2767 } else {
2768 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2769 }
2770 break;
2771 case OPC_NOR:
2772 if (rs != 0 && rt != 0) {
2773 tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2774 } else if (rs == 0 && rt != 0) {
2775 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]);
2776 } else if (rs != 0 && rt == 0) {
2777 tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]);
2778 } else {
2779 tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0));
2780 }
2781 break;
2782 case OPC_OR:
2783 if (likely(rs != 0 && rt != 0)) {
2784 tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2785 } else if (rs == 0 && rt != 0) {
2786 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2787 } else if (rs != 0 && rt == 0) {
2788 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2789 } else {
2790 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2791 }
2792 break;
2793 case OPC_XOR:
2794 if (likely(rs != 0 && rt != 0)) {
2795 tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
2796 } else if (rs == 0 && rt != 0) {
2797 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]);
2798 } else if (rs != 0 && rt == 0) {
2799 tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
2800 } else {
2801 tcg_gen_movi_tl(cpu_gpr[rd], 0);
2802 }
2803 break;
2804 }
2805 }
2806
2807 /* Set on lower than */
2808 static void gen_slt(DisasContext *ctx, uint32_t opc,
2809 int rd, int rs, int rt)
2810 {
2811 TCGv t0, t1;
2812
2813 if (rd == 0) {
2814 /* If no destination, treat it as a NOP. */
2815 return;
2816 }
2817
2818 t0 = tcg_temp_new();
2819 t1 = tcg_temp_new();
2820 gen_load_gpr(t0, rs);
2821 gen_load_gpr(t1, rt);
2822 switch (opc) {
2823 case OPC_SLT:
2824 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1);
2825 break;
2826 case OPC_SLTU:
2827 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1);
2828 break;
2829 }
2830 }
2831
2832 /* Shifts */
2833 static void gen_shift(DisasContext *ctx, uint32_t opc,
2834 int rd, int rs, int rt)
2835 {
2836 TCGv t0, t1;
2837
2838 if (rd == 0) {
2839 /*
2840 * If no destination, treat it as a NOP.
2841 * For add & sub, we must generate the overflow exception when needed.
2842 */
2843 return;
2844 }
2845
2846 t0 = tcg_temp_new();
2847 t1 = tcg_temp_new();
2848 gen_load_gpr(t0, rs);
2849 gen_load_gpr(t1, rt);
2850 switch (opc) {
2851 case OPC_SLLV:
2852 tcg_gen_andi_tl(t0, t0, 0x1f);
2853 tcg_gen_shl_tl(t0, t1, t0);
2854 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2855 break;
2856 case OPC_SRAV:
2857 tcg_gen_andi_tl(t0, t0, 0x1f);
2858 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2859 break;
2860 case OPC_SRLV:
2861 tcg_gen_ext32u_tl(t1, t1);
2862 tcg_gen_andi_tl(t0, t0, 0x1f);
2863 tcg_gen_shr_tl(t0, t1, t0);
2864 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
2865 break;
2866 case OPC_ROTRV:
2867 {
2868 TCGv_i32 t2 = tcg_temp_new_i32();
2869 TCGv_i32 t3 = tcg_temp_new_i32();
2870
2871 tcg_gen_trunc_tl_i32(t2, t0);
2872 tcg_gen_trunc_tl_i32(t3, t1);
2873 tcg_gen_andi_i32(t2, t2, 0x1f);
2874 tcg_gen_rotr_i32(t2, t3, t2);
2875 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
2876 }
2877 break;
2878 #if defined(TARGET_MIPS64)
2879 case OPC_DSLLV:
2880 tcg_gen_andi_tl(t0, t0, 0x3f);
2881 tcg_gen_shl_tl(cpu_gpr[rd], t1, t0);
2882 break;
2883 case OPC_DSRAV:
2884 tcg_gen_andi_tl(t0, t0, 0x3f);
2885 tcg_gen_sar_tl(cpu_gpr[rd], t1, t0);
2886 break;
2887 case OPC_DSRLV:
2888 tcg_gen_andi_tl(t0, t0, 0x3f);
2889 tcg_gen_shr_tl(cpu_gpr[rd], t1, t0);
2890 break;
2891 case OPC_DROTRV:
2892 tcg_gen_andi_tl(t0, t0, 0x3f);
2893 tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0);
2894 break;
2895 #endif
2896 }
2897 }
2898
2899 /* Arithmetic on HI/LO registers */
2900 static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
2901 {
2902 if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
2903 /* Treat as NOP. */
2904 return;
2905 }
2906
2907 if (acc != 0) {
2908 check_dsp(ctx);
2909 }
2910
2911 switch (opc) {
2912 case OPC_MFHI:
2913 #if defined(TARGET_MIPS64)
2914 if (acc != 0) {
2915 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
2916 } else
2917 #endif
2918 {
2919 tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]);
2920 }
2921 break;
2922 case OPC_MFLO:
2923 #if defined(TARGET_MIPS64)
2924 if (acc != 0) {
2925 tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
2926 } else
2927 #endif
2928 {
2929 tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]);
2930 }
2931 break;
2932 case OPC_MTHI:
2933 if (reg != 0) {
2934 #if defined(TARGET_MIPS64)
2935 if (acc != 0) {
2936 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]);
2937 } else
2938 #endif
2939 {
2940 tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]);
2941 }
2942 } else {
2943 tcg_gen_movi_tl(cpu_HI[acc], 0);
2944 }
2945 break;
2946 case OPC_MTLO:
2947 if (reg != 0) {
2948 #if defined(TARGET_MIPS64)
2949 if (acc != 0) {
2950 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]);
2951 } else
2952 #endif
2953 {
2954 tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]);
2955 }
2956 } else {
2957 tcg_gen_movi_tl(cpu_LO[acc], 0);
2958 }
2959 break;
2960 }
2961 }
2962
2963 static inline void gen_r6_ld(target_long addr, int reg, int memidx,
2964 MemOp memop)
2965 {
2966 TCGv t0 = tcg_temp_new();
2967 tcg_gen_qemu_ld_tl(t0, tcg_constant_tl(addr), memidx, memop);
2968 gen_store_gpr(t0, reg);
2969 }
2970
2971 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
2972 int rs)
2973 {
2974 target_long offset;
2975 target_long addr;
2976
2977 switch (MASK_OPC_PCREL_TOP2BITS(opc)) {
2978 case OPC_ADDIUPC:
2979 if (rs != 0) {
2980 offset = sextract32(ctx->opcode << 2, 0, 21);
2981 addr = addr_add(ctx, pc, offset);
2982 tcg_gen_movi_tl(cpu_gpr[rs], addr);
2983 }
2984 break;
2985 case R6_OPC_LWPC:
2986 offset = sextract32(ctx->opcode << 2, 0, 21);
2987 addr = addr_add(ctx, pc, offset);
2988 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL);
2989 break;
2990 #if defined(TARGET_MIPS64)
2991 case OPC_LWUPC:
2992 check_mips_64(ctx);
2993 offset = sextract32(ctx->opcode << 2, 0, 21);
2994 addr = addr_add(ctx, pc, offset);
2995 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL);
2996 break;
2997 #endif
2998 default:
2999 switch (MASK_OPC_PCREL_TOP5BITS(opc)) {
3000 case OPC_AUIPC:
3001 if (rs != 0) {
3002 offset = sextract32(ctx->opcode, 0, 16) << 16;
3003 addr = addr_add(ctx, pc, offset);
3004 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3005 }
3006 break;
3007 case OPC_ALUIPC:
3008 if (rs != 0) {
3009 offset = sextract32(ctx->opcode, 0, 16) << 16;
3010 addr = ~0xFFFF & addr_add(ctx, pc, offset);
3011 tcg_gen_movi_tl(cpu_gpr[rs], addr);
3012 }
3013 break;
3014 #if defined(TARGET_MIPS64)
3015 case R6_OPC_LDPC: /* bits 16 and 17 are part of immediate */
3016 case R6_OPC_LDPC + (1 << 16):
3017 case R6_OPC_LDPC + (2 << 16):
3018 case R6_OPC_LDPC + (3 << 16):
3019 check_mips_64(ctx);
3020 offset = sextract32(ctx->opcode << 3, 0, 21);
3021 addr = addr_add(ctx, (pc & ~0x7), offset);
3022 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
3023 break;
3024 #endif
3025 default:
3026 MIPS_INVAL("OPC_PCREL");
3027 gen_reserved_instruction(ctx);
3028 break;
3029 }
3030 break;
3031 }
3032 }
3033
3034 static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
3035 {
3036 TCGv t0, t1;
3037
3038 if (rd == 0) {
3039 /* Treat as NOP. */
3040 return;
3041 }
3042
3043 t0 = tcg_temp_new();
3044 t1 = tcg_temp_new();
3045
3046 gen_load_gpr(t0, rs);
3047 gen_load_gpr(t1, rt);
3048
3049 switch (opc) {
3050 case R6_OPC_DIV:
3051 {
3052 TCGv t2 = tcg_temp_new();
3053 TCGv t3 = tcg_temp_new();
3054 tcg_gen_ext32s_tl(t0, t0);
3055 tcg_gen_ext32s_tl(t1, t1);
3056 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3057 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3058 tcg_gen_and_tl(t2, t2, t3);
3059 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3060 tcg_gen_or_tl(t2, t2, t3);
3061 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3062 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3063 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3064 }
3065 break;
3066 case R6_OPC_MOD:
3067 {
3068 TCGv t2 = tcg_temp_new();
3069 TCGv t3 = tcg_temp_new();
3070 tcg_gen_ext32s_tl(t0, t0);
3071 tcg_gen_ext32s_tl(t1, t1);
3072 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3073 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3074 tcg_gen_and_tl(t2, t2, t3);
3075 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3076 tcg_gen_or_tl(t2, t2, t3);
3077 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3078 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3079 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3080 }
3081 break;
3082 case R6_OPC_DIVU:
3083 {
3084 tcg_gen_ext32u_tl(t0, t0);
3085 tcg_gen_ext32u_tl(t1, t1);
3086 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
3087 tcg_constant_tl(0), tcg_constant_tl(1), t1);
3088 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3089 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3090 }
3091 break;
3092 case R6_OPC_MODU:
3093 {
3094 tcg_gen_ext32u_tl(t0, t0);
3095 tcg_gen_ext32u_tl(t1, t1);
3096 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
3097 tcg_constant_tl(0), tcg_constant_tl(1), t1);
3098 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3099 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3100 }
3101 break;
3102 case R6_OPC_MUL:
3103 {
3104 TCGv_i32 t2 = tcg_temp_new_i32();
3105 TCGv_i32 t3 = tcg_temp_new_i32();
3106 tcg_gen_trunc_tl_i32(t2, t0);
3107 tcg_gen_trunc_tl_i32(t3, t1);
3108 tcg_gen_mul_i32(t2, t2, t3);
3109 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3110 }
3111 break;
3112 case R6_OPC_MUH:
3113 {
3114 TCGv_i32 t2 = tcg_temp_new_i32();
3115 TCGv_i32 t3 = tcg_temp_new_i32();
3116 tcg_gen_trunc_tl_i32(t2, t0);
3117 tcg_gen_trunc_tl_i32(t3, t1);
3118 tcg_gen_muls2_i32(t2, t3, t2, t3);
3119 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3120 }
3121 break;
3122 case R6_OPC_MULU:
3123 {
3124 TCGv_i32 t2 = tcg_temp_new_i32();
3125 TCGv_i32 t3 = tcg_temp_new_i32();
3126 tcg_gen_trunc_tl_i32(t2, t0);
3127 tcg_gen_trunc_tl_i32(t3, t1);
3128 tcg_gen_mul_i32(t2, t2, t3);
3129 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3130 }
3131 break;
3132 case R6_OPC_MUHU:
3133 {
3134 TCGv_i32 t2 = tcg_temp_new_i32();
3135 TCGv_i32 t3 = tcg_temp_new_i32();
3136 tcg_gen_trunc_tl_i32(t2, t0);
3137 tcg_gen_trunc_tl_i32(t3, t1);
3138 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3139 tcg_gen_ext_i32_tl(cpu_gpr[rd], t3);
3140 }
3141 break;
3142 #if defined(TARGET_MIPS64)
3143 case R6_OPC_DDIV:
3144 {
3145 TCGv t2 = tcg_temp_new();
3146 TCGv t3 = tcg_temp_new();
3147 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3148 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3149 tcg_gen_and_tl(t2, t2, t3);
3150 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3151 tcg_gen_or_tl(t2, t2, t3);
3152 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3153 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3154 }
3155 break;
3156 case R6_OPC_DMOD:
3157 {
3158 TCGv t2 = tcg_temp_new();
3159 TCGv t3 = tcg_temp_new();
3160 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3161 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3162 tcg_gen_and_tl(t2, t2, t3);
3163 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3164 tcg_gen_or_tl(t2, t2, t3);
3165 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3166 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3167 }
3168 break;
3169 case R6_OPC_DDIVU:
3170 {
3171 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
3172 tcg_constant_tl(0), tcg_constant_tl(1), t1);
3173 tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
3174 }
3175 break;
3176 case R6_OPC_DMODU:
3177 {
3178 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
3179 tcg_constant_tl(0), tcg_constant_tl(1), t1);
3180 tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
3181 }
3182 break;
3183 case R6_OPC_DMUL:
3184 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3185 break;
3186 case R6_OPC_DMUH:
3187 {
3188 TCGv t2 = tcg_temp_new();
3189 tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1);
3190 }
3191 break;
3192 case R6_OPC_DMULU:
3193 tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);
3194 break;
3195 case R6_OPC_DMUHU:
3196 {
3197 TCGv t2 = tcg_temp_new();
3198 tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1);
3199 }
3200 break;
3201 #endif
3202 default:
3203 MIPS_INVAL("r6 mul/div");
3204 gen_reserved_instruction(ctx);
3205 break;
3206 }
3207 }
3208
3209 #if defined(TARGET_MIPS64)
3210 static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
3211 {
3212 TCGv t0, t1;
3213
3214 t0 = tcg_temp_new();
3215 t1 = tcg_temp_new();
3216
3217 gen_load_gpr(t0, rs);
3218 gen_load_gpr(t1, rt);
3219
3220 switch (opc) {
3221 case MMI_OPC_DIV1:
3222 {
3223 TCGv t2 = tcg_temp_new();
3224 TCGv t3 = tcg_temp_new();
3225 tcg_gen_ext32s_tl(t0, t0);
3226 tcg_gen_ext32s_tl(t1, t1);
3227 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3228 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3229 tcg_gen_and_tl(t2, t2, t3);
3230 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3231 tcg_gen_or_tl(t2, t2, t3);
3232 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3233 tcg_gen_div_tl(cpu_LO[1], t0, t1);
3234 tcg_gen_rem_tl(cpu_HI[1], t0, t1);
3235 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
3236 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
3237 }
3238 break;
3239 case MMI_OPC_DIVU1:
3240 {
3241 TCGv t2 = tcg_constant_tl(0);
3242 TCGv t3 = tcg_constant_tl(1);
3243 tcg_gen_ext32u_tl(t0, t0);
3244 tcg_gen_ext32u_tl(t1, t1);
3245 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3246 tcg_gen_divu_tl(cpu_LO[1], t0, t1);
3247 tcg_gen_remu_tl(cpu_HI[1], t0, t1);
3248 tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
3249 tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]);
3250 }
3251 break;
3252 default:
3253 MIPS_INVAL("div1 TX79");
3254 gen_reserved_instruction(ctx);
3255 break;
3256 }
3257 }
3258 #endif
3259
3260 static void gen_muldiv(DisasContext *ctx, uint32_t opc,
3261 int acc, int rs, int rt)
3262 {
3263 TCGv t0, t1;
3264
3265 t0 = tcg_temp_new();
3266 t1 = tcg_temp_new();
3267
3268 gen_load_gpr(t0, rs);
3269 gen_load_gpr(t1, rt);
3270
3271 if (acc != 0) {
3272 check_dsp(ctx);
3273 }
3274
3275 switch (opc) {
3276 case OPC_DIV:
3277 {
3278 TCGv t2 = tcg_temp_new();
3279 TCGv t3 = tcg_temp_new();
3280 tcg_gen_ext32s_tl(t0, t0);
3281 tcg_gen_ext32s_tl(t1, t1);
3282 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN);
3283 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1);
3284 tcg_gen_and_tl(t2, t2, t3);
3285 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3286 tcg_gen_or_tl(t2, t2, t3);
3287 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3288 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3289 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3290 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3291 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3292 }
3293 break;
3294 case OPC_DIVU:
3295 {
3296 TCGv t2 = tcg_constant_tl(0);
3297 TCGv t3 = tcg_constant_tl(1);
3298 tcg_gen_ext32u_tl(t0, t0);
3299 tcg_gen_ext32u_tl(t1, t1);
3300 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
3301 tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
3302 tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
3303 tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
3304 tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
3305 }
3306 break;
3307 case OPC_MULT:
3308 {
3309 TCGv_i32 t2 = tcg_temp_new_i32();
3310 TCGv_i32 t3 = tcg_temp_new_i32();
3311 tcg_gen_trunc_tl_i32(t2, t0);
3312 tcg_gen_trunc_tl_i32(t3, t1);
3313 tcg_gen_muls2_i32(t2, t3, t2, t3);
3314 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3315 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3316 }
3317 break;
3318 case OPC_MULTU:
3319 {
3320 TCGv_i32 t2 = tcg_temp_new_i32();
3321 TCGv_i32 t3 = tcg_temp_new_i32();
3322 tcg_gen_trunc_tl_i32(t2, t0);
3323 tcg_gen_trunc_tl_i32(t3, t1);
3324 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3325 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3326 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3327 }
3328 break;
3329 #if defined(TARGET_MIPS64)
3330 case OPC_DDIV:
3331 {
3332 TCGv t2 = tcg_temp_new();
3333 TCGv t3 = tcg_temp_new();
3334 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63);
3335 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL);
3336 tcg_gen_and_tl(t2, t2, t3);
3337 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
3338 tcg_gen_or_tl(t2, t2, t3);
3339 tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
3340 tcg_gen_div_tl(cpu_LO[acc], t0, t1);
3341 tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
3342 }
3343 break;
3344 case OPC_DDIVU:
3345 {
3346 tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
3347 tcg_constant_tl(0), tcg_constant_tl(1), t1);
3348 tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
3349 tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
3350 }
3351 break;
3352 case OPC_DMULT:
3353 tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3354 break;
3355 case OPC_DMULTU:
3356 tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1);
3357 break;
3358 #endif
3359 case OPC_MADD:
3360 {
3361 TCGv_i64 t2 = tcg_temp_new_i64();
3362 TCGv_i64 t3 = tcg_temp_new_i64();
3363
3364 tcg_gen_ext_tl_i64(t2, t0);
3365 tcg_gen_ext_tl_i64(t3, t1);
3366 tcg_gen_mul_i64(t2, t2, t3);
3367 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3368 tcg_gen_add_i64(t2, t2, t3);
3369 gen_move_low32(cpu_LO[acc], t2);
3370 gen_move_high32(cpu_HI[acc], t2);
3371 }
3372 break;
3373 case OPC_MADDU:
3374 {
3375 TCGv_i64 t2 = tcg_temp_new_i64();
3376 TCGv_i64 t3 = tcg_temp_new_i64();
3377
3378 tcg_gen_ext32u_tl(t0, t0);
3379 tcg_gen_ext32u_tl(t1, t1);
3380 tcg_gen_extu_tl_i64(t2, t0);
3381 tcg_gen_extu_tl_i64(t3, t1);
3382 tcg_gen_mul_i64(t2, t2, t3);
3383 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3384 tcg_gen_add_i64(t2, t2, t3);
3385 gen_move_low32(cpu_LO[acc], t2);
3386 gen_move_high32(cpu_HI[acc], t2);
3387 }
3388 break;
3389 case OPC_MSUB:
3390 {
3391 TCGv_i64 t2 = tcg_temp_new_i64();
3392 TCGv_i64 t3 = tcg_temp_new_i64();
3393
3394 tcg_gen_ext_tl_i64(t2, t0);
3395 tcg_gen_ext_tl_i64(t3, t1);
3396 tcg_gen_mul_i64(t2, t2, t3);
3397 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3398 tcg_gen_sub_i64(t2, t3, t2);
3399 gen_move_low32(cpu_LO[acc], t2);
3400 gen_move_high32(cpu_HI[acc], t2);
3401 }
3402 break;
3403 case OPC_MSUBU:
3404 {
3405 TCGv_i64 t2 = tcg_temp_new_i64();
3406 TCGv_i64 t3 = tcg_temp_new_i64();
3407
3408 tcg_gen_ext32u_tl(t0, t0);
3409 tcg_gen_ext32u_tl(t1, t1);
3410 tcg_gen_extu_tl_i64(t2, t0);
3411 tcg_gen_extu_tl_i64(t3, t1);
3412 tcg_gen_mul_i64(t2, t2, t3);
3413 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3414 tcg_gen_sub_i64(t2, t3, t2);
3415 gen_move_low32(cpu_LO[acc], t2);
3416 gen_move_high32(cpu_HI[acc], t2);
3417 }
3418 break;
3419 default:
3420 MIPS_INVAL("mul/div");
3421 gen_reserved_instruction(ctx);
3422 break;
3423 }
3424 }
3425
3426 /*
3427 * These MULT[U] and MADD[U] instructions implemented in for example
3428 * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
3429 * architectures are special three-operand variants with the syntax
3430 *
3431 * MULT[U][1] rd, rs, rt
3432 *
3433 * such that
3434 *
3435 * (rd, LO, HI) <- rs * rt
3436 *
3437 * and
3438 *
3439 * MADD[U][1] rd, rs, rt
3440 *
3441 * such that
3442 *
3443 * (rd, LO, HI) <- (LO, HI) + rs * rt
3444 *
3445 * where the low-order 32-bits of the result is placed into both the
3446 * GPR rd and the special register LO. The high-order 32-bits of the
3447 * result is placed into the special register HI.
3448 *
3449 * If the GPR rd is omitted in assembly language, it is taken to be 0,
3450 * which is the zero register that always reads as 0.
3451 */
3452 static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
3453 int rd, int rs, int rt)
3454 {
3455 TCGv t0 = tcg_temp_new();
3456 TCGv t1 = tcg_temp_new();
3457 int acc = 0;
3458
3459 gen_load_gpr(t0, rs);
3460 gen_load_gpr(t1, rt);
3461
3462 switch (opc) {
3463 case MMI_OPC_MULT1:
3464 acc = 1;
3465 /* Fall through */
3466 case OPC_MULT:
3467 {
3468 TCGv_i32 t2 = tcg_temp_new_i32();
3469 TCGv_i32 t3 = tcg_temp_new_i32();
3470 tcg_gen_trunc_tl_i32(t2, t0);
3471 tcg_gen_trunc_tl_i32(t3, t1);
3472 tcg_gen_muls2_i32(t2, t3, t2, t3);
3473 if (rd) {
3474 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3475 }
3476 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3477 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3478 }
3479 break;
3480 case MMI_OPC_MULTU1:
3481 acc = 1;
3482 /* Fall through */
3483 case OPC_MULTU:
3484 {
3485 TCGv_i32 t2 = tcg_temp_new_i32();
3486 TCGv_i32 t3 = tcg_temp_new_i32();
3487 tcg_gen_trunc_tl_i32(t2, t0);
3488 tcg_gen_trunc_tl_i32(t3, t1);
3489 tcg_gen_mulu2_i32(t2, t3, t2, t3);
3490 if (rd) {
3491 tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
3492 }
3493 tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
3494 tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
3495 }
3496 break;
3497 case MMI_OPC_MADD1:
3498 acc = 1;
3499 /* Fall through */
3500 case MMI_OPC_MADD:
3501 {
3502 TCGv_i64 t2 = tcg_temp_new_i64();
3503 TCGv_i64 t3 = tcg_temp_new_i64();
3504
3505 tcg_gen_ext_tl_i64(t2, t0);
3506 tcg_gen_ext_tl_i64(t3, t1);
3507 tcg_gen_mul_i64(t2, t2, t3);
3508 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3509 tcg_gen_add_i64(t2, t2, t3);
3510 gen_move_low32(cpu_LO[acc], t2);
3511 gen_move_high32(cpu_HI[acc], t2);
3512 if (rd) {
3513 gen_move_low32(cpu_gpr[rd], t2);
3514 }
3515 }
3516 break;
3517 case MMI_OPC_MADDU1:
3518 acc = 1;
3519 /* Fall through */
3520 case MMI_OPC_MADDU:
3521 {
3522 TCGv_i64 t2 = tcg_temp_new_i64();
3523 TCGv_i64 t3 = tcg_temp_new_i64();
3524
3525 tcg_gen_ext32u_tl(t0, t0);
3526 tcg_gen_ext32u_tl(t1, t1);
3527 tcg_gen_extu_tl_i64(t2, t0);
3528 tcg_gen_extu_tl_i64(t3, t1);
3529 tcg_gen_mul_i64(t2, t2, t3);
3530 tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]);
3531 tcg_gen_add_i64(t2, t2, t3);
3532 gen_move_low32(cpu_LO[acc], t2);
3533 gen_move_high32(cpu_HI[acc], t2);
3534 if (rd) {
3535 gen_move_low32(cpu_gpr[rd], t2);
3536 }
3537 }
3538 break;
3539 default:
3540 MIPS_INVAL("mul/madd TXx9");
3541 gen_reserved_instruction(ctx);
3542 break;
3543 }
3544 }
3545
3546 static void gen_cl(DisasContext *ctx, uint32_t opc,
3547 int rd, int rs)
3548 {
3549 TCGv t0;
3550
3551 if (rd == 0) {
3552 /* Treat as NOP. */
3553 return;
3554 }
3555 t0 = cpu_gpr[rd];
3556 gen_load_gpr(t0, rs);
3557
3558 switch (opc) {
3559 case OPC_CLO:
3560 case R6_OPC_CLO:
3561 #if defined(TARGET_MIPS64)
3562 case OPC_DCLO:
3563 case R6_OPC_DCLO:
3564 #endif
3565 tcg_gen_not_tl(t0, t0);
3566 break;
3567 }
3568
3569 switch (opc) {
3570 case OPC_CLO:
3571 case R6_OPC_CLO:
3572 case OPC_CLZ:
3573 case R6_OPC_CLZ:
3574 tcg_gen_ext32u_tl(t0, t0);
3575 tcg_gen_clzi_tl(t0, t0, TARGET_LONG_BITS);
3576 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32);
3577 break;
3578 #if defined(TARGET_MIPS64)
3579 case OPC_DCLO:
3580 case R6_OPC_DCLO:
3581 case OPC_DCLZ:
3582 case R6_OPC_DCLZ:
3583 tcg_gen_clzi_i64(t0, t0, 64);
3584 break;
3585 #endif
3586 }
3587 }
3588
3589 /* Godson integer instructions */
3590 static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
3591 int rd, int rs, int rt)
3592 {
3593 TCGv t0, t1;
3594
3595 if (rd == 0) {
3596 /* Treat as NOP. */
3597 return;
3598 }
3599
3600 t0 = tcg_temp_new();
3601 t1 = tcg_temp_new();
3602 gen_load_gpr(t0, rs);
3603 gen_load_gpr(t1, rt);
3604
3605 switch (opc) {
3606 case OPC_MULT_G_2E:
3607 case OPC_MULT_G_2F:
3608 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3609 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3610 break;
3611 case OPC_MULTU_G_2E:
3612 case OPC_MULTU_G_2F:
3613 tcg_gen_ext32u_tl(t0, t0);
3614 tcg_gen_ext32u_tl(t1, t1);
3615 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3616 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3617 break;
3618 case OPC_DIV_G_2E:
3619 case OPC_DIV_G_2F:
3620 {
3621 TCGLabel *l1 = gen_new_label();
3622 TCGLabel *l2 = gen_new_label();
3623 TCGLabel *l3 = gen_new_label();
3624 tcg_gen_ext32s_tl(t0, t0);
3625 tcg_gen_ext32s_tl(t1, t1);
3626 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3627 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3628 tcg_gen_br(l3);
3629 gen_set_label(l1);
3630 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3631 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3632 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3633 tcg_gen_br(l3);
3634 gen_set_label(l2);
3635 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3636 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3637 gen_set_label(l3);
3638 }
3639 break;
3640 case OPC_DIVU_G_2E:
3641 case OPC_DIVU_G_2F:
3642 {
3643 TCGLabel *l1 = gen_new_label();
3644 TCGLabel *l2 = gen_new_label();
3645 tcg_gen_ext32u_tl(t0, t0);
3646 tcg_gen_ext32u_tl(t1, t1);
3647 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3648 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3649 tcg_gen_br(l2);
3650 gen_set_label(l1);
3651 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3652 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3653 gen_set_label(l2);
3654 }
3655 break;
3656 case OPC_MOD_G_2E:
3657 case OPC_MOD_G_2F:
3658 {
3659 TCGLabel *l1 = gen_new_label();
3660 TCGLabel *l2 = gen_new_label();
3661 TCGLabel *l3 = gen_new_label();
3662 tcg_gen_ext32u_tl(t0, t0);
3663 tcg_gen_ext32u_tl(t1, t1);
3664 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3665 tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
3666 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
3667 gen_set_label(l1);
3668 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3669 tcg_gen_br(l3);
3670 gen_set_label(l2);
3671 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3672 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3673 gen_set_label(l3);
3674 }
3675 break;
3676 case OPC_MODU_G_2E:
3677 case OPC_MODU_G_2F:
3678 {
3679 TCGLabel *l1 = gen_new_label();
3680 TCGLabel *l2 = gen_new_label();
3681 tcg_gen_ext32u_tl(t0, t0);
3682 tcg_gen_ext32u_tl(t1, t1);
3683 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3684 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3685 tcg_gen_br(l2);
3686 gen_set_label(l1);
3687 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3688 tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
3689 gen_set_label(l2);
3690 }
3691 break;
3692 #if defined(TARGET_MIPS64)
3693 case OPC_DMULT_G_2E:
3694 case OPC_DMULT_G_2F:
3695 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3696 break;
3697 case OPC_DMULTU_G_2E:
3698 case OPC_DMULTU_G_2F:
3699 tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
3700 break;
3701 case OPC_DDIV_G_2E:
3702 case OPC_DDIV_G_2F:
3703 {
3704 TCGLabel *l1 = gen_new_label();
3705 TCGLabel *l2 = gen_new_label();
3706 TCGLabel *l3 = gen_new_label();
3707 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3708 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3709 tcg_gen_br(l3);
3710 gen_set_label(l1);
3711 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3712 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3713 tcg_gen_mov_tl(cpu_gpr[rd], t0);
3714 tcg_gen_br(l3);
3715 gen_set_label(l2);
3716 tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
3717 gen_set_label(l3);
3718 }
3719 break;
3720 case OPC_DDIVU_G_2E:
3721 case OPC_DDIVU_G_2F:
3722 {
3723 TCGLabel *l1 = gen_new_label();
3724 TCGLabel *l2 = gen_new_label();
3725 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3726 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3727 tcg_gen_br(l2);
3728 gen_set_label(l1);
3729 tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
3730 gen_set_label(l2);
3731 }
3732 break;
3733 case OPC_DMOD_G_2E:
3734 case OPC_DMOD_G_2F:
3735 {
3736 TCGLabel *l1 = gen_new_label();
3737 TCGLabel *l2 = gen_new_label();
3738 TCGLabel *l3 = gen_new_label();
3739 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
3740 tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
3741 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
3742 gen_set_label(l1);
3743 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3744 tcg_gen_br(l3);
3745 gen_set_label(l2);
3746 tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
3747 gen_set_label(l3);
3748 }
3749 break;
3750 case OPC_DMODU_G_2E:
3751 case OPC_DMODU_G_2F:
3752 {
3753 TCGLabel *l1 = gen_new_label();
3754 TCGLabel *l2 = gen_new_label();
3755 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
3756 tcg_gen_movi_tl(cpu_gpr[rd], 0);
3757 tcg_gen_br(l2);
3758 gen_set_label(l1);
3759 tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
3760 gen_set_label(l2);
3761 }
3762 break;
3763 #endif
3764 }
3765 }
3766
3767 /* Loongson multimedia instructions */
3768 static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
3769 {
3770 uint32_t opc, shift_max;
3771 TCGv_i64 t0, t1;
3772 TCGCond cond;
3773
3774 opc = MASK_LMMI(ctx->opcode);
3775 check_cp1_enabled(ctx);
3776
3777 t0 = tcg_temp_new_i64();
3778 t1 = tcg_temp_new_i64();
3779 gen_load_fpr64(ctx, t0, rs);
3780 gen_load_fpr64(ctx, t1, rt);
3781
3782 switch (opc) {
3783 case OPC_PADDSH:
3784 gen_helper_paddsh(t0, t0, t1);
3785 break;
3786 case OPC_PADDUSH:
3787 gen_helper_paddush(t0, t0, t1);
3788 break;
3789 case OPC_PADDH:
3790 gen_helper_paddh(t0, t0, t1);
3791 break;
3792 case OPC_PADDW:
3793 gen_helper_paddw(t0, t0, t1);
3794 break;
3795 case OPC_PADDSB:
3796 gen_helper_paddsb(t0, t0, t1);
3797 break;
3798 case OPC_PADDUSB:
3799 gen_helper_paddusb(t0, t0, t1);
3800 break;
3801 case OPC_PADDB:
3802 gen_helper_paddb(t0, t0, t1);
3803 break;
3804
3805 case OPC_PSUBSH:
3806 gen_helper_psubsh(t0, t0, t1);
3807 break;
3808 case OPC_PSUBUSH:
3809 gen_helper_psubush(t0, t0, t1);
3810 break;
3811 case OPC_PSUBH:
3812 gen_helper_psubh(t0, t0, t1);
3813 break;
3814 case OPC_PSUBW:
3815 gen_helper_psubw(t0, t0, t1);
3816 break;
3817 case OPC_PSUBSB:
3818 gen_helper_psubsb(t0, t0, t1);
3819 break;
3820 case OPC_PSUBUSB:
3821 gen_helper_psubusb(t0, t0, t1);
3822 break;
3823 case OPC_PSUBB:
3824 gen_helper_psubb(t0, t0, t1);
3825 break;
3826
3827 case OPC_PSHUFH:
3828 gen_helper_pshufh(t0, t0, t1);
3829 break;
3830 case OPC_PACKSSWH:
3831 gen_helper_packsswh(t0, t0, t1);
3832 break;
3833 case OPC_PACKSSHB:
3834 gen_helper_packsshb(t0, t0, t1);
3835 break;
3836 case OPC_PACKUSHB:
3837 gen_helper_packushb(t0, t0, t1);
3838 break;
3839
3840 case OPC_PUNPCKLHW:
3841 gen_helper_punpcklhw(t0, t0, t1);
3842 break;
3843 case OPC_PUNPCKHHW:
3844 gen_helper_punpckhhw(t0, t0, t1);
3845 break;
3846 case OPC_PUNPCKLBH:
3847 gen_helper_punpcklbh(t0, t0, t1);
3848 break;
3849 case OPC_PUNPCKHBH:
3850 gen_helper_punpckhbh(t0, t0, t1);
3851 break;
3852 case OPC_PUNPCKLWD:
3853 gen_helper_punpcklwd(t0, t0, t1);
3854 break;
3855 case OPC_PUNPCKHWD:
3856 gen_helper_punpckhwd(t0, t0, t1);
3857 break;
3858
3859 case OPC_PAVGH:
3860 gen_helper_pavgh(t0, t0, t1);
3861 break;
3862 case OPC_PAVGB:
3863 gen_helper_pavgb(t0, t0, t1);
3864 break;
3865 case OPC_PMAXSH:
3866 gen_helper_pmaxsh(t0, t0, t1);
3867 break;
3868 case OPC_PMINSH:
3869 gen_helper_pminsh(t0, t0, t1);
3870 break;
3871 case OPC_PMAXUB:
3872 gen_helper_pmaxub(t0, t0, t1);
3873 break;
3874 case OPC_PMINUB:
3875 gen_helper_pminub(t0, t0, t1);
3876 break;
3877
3878 case OPC_PCMPEQW:
3879 gen_helper_pcmpeqw(t0, t0, t1);
3880 break;
3881 case OPC_PCMPGTW:
3882 gen_helper_pcmpgtw(t0, t0, t1);
3883 break;
3884 case OPC_PCMPEQH:
3885 gen_helper_pcmpeqh(t0, t0, t1);
3886 break;
3887 case OPC_PCMPGTH:
3888 gen_helper_pcmpgth(t0, t0, t1);
3889 break;
3890 case OPC_PCMPEQB:
3891 gen_helper_pcmpeqb(t0, t0, t1);
3892 break;
3893 case OPC_PCMPGTB:
3894 gen_helper_pcmpgtb(t0, t0, t1);
3895 break;
3896
3897 case OPC_PSLLW:
3898 gen_helper_psllw(t0, t0, t1);
3899 break;
3900 case OPC_PSLLH:
3901 gen_helper_psllh(t0, t0, t1);
3902 break;
3903 case OPC_PSRLW:
3904 gen_helper_psrlw(t0, t0, t1);
3905 break;
3906 case OPC_PSRLH:
3907 gen_helper_psrlh(t0, t0, t1);
3908 break;
3909 case OPC_PSRAW:
3910 gen_helper_psraw(t0, t0, t1);
3911 break;
3912 case OPC_PSRAH:
3913 gen_helper_psrah(t0, t0, t1);
3914 break;
3915
3916 case OPC_PMULLH:
3917 gen_helper_pmullh(t0, t0, t1);
3918 break;
3919 case OPC_PMULHH:
3920 gen_helper_pmulhh(t0, t0, t1);
3921 break;
3922 case OPC_PMULHUH:
3923 gen_helper_pmulhuh(t0, t0, t1);
3924 break;
3925 case OPC_PMADDHW:
3926 gen_helper_pmaddhw(t0, t0, t1);
3927 break;
3928
3929 case OPC_PASUBUB:
3930 gen_helper_pasubub(t0, t0, t1);
3931 break;
3932 case OPC_BIADD:
3933 gen_helper_biadd(t0, t0);
3934 break;
3935 case OPC_PMOVMSKB:
3936 gen_helper_pmovmskb(t0, t0);
3937 break;
3938
3939 case OPC_PADDD:
3940 tcg_gen_add_i64(t0, t0, t1);
3941 break;
3942 case OPC_PSUBD:
3943 tcg_gen_sub_i64(t0, t0, t1);
3944 break;
3945 case OPC_XOR_CP2:
3946 tcg_gen_xor_i64(t0, t0, t1);
3947 break;
3948 case OPC_NOR_CP2:
3949 tcg_gen_nor_i64(t0, t0, t1);
3950 break;
3951 case OPC_AND_CP2:
3952 tcg_gen_and_i64(t0, t0, t1);
3953 break;
3954 case OPC_OR_CP2:
3955 tcg_gen_or_i64(t0, t0, t1);
3956 break;
3957
3958 case OPC_PANDN:
3959 tcg_gen_andc_i64(t0, t1, t0);
3960 break;
3961
3962 case OPC_PINSRH_0:
3963 tcg_gen_deposit_i64(t0, t0, t1, 0, 16);
3964 break;
3965 case OPC_PINSRH_1:
3966 tcg_gen_deposit_i64(t0, t0, t1, 16, 16);
3967 break;
3968 case OPC_PINSRH_2:
3969 tcg_gen_deposit_i64(t0, t0, t1, 32, 16);
3970 break;
3971 case OPC_PINSRH_3:
3972 tcg_gen_deposit_i64(t0, t0, t1, 48, 16);
3973 break;
3974
3975 case OPC_PEXTRH:
3976 tcg_gen_andi_i64(t1, t1, 3);
3977 tcg_gen_shli_i64(t1, t1, 4);
3978 tcg_gen_shr_i64(t0, t0, t1);
3979 tcg_gen_ext16u_i64(t0, t0);
3980 break;
3981
3982 case OPC_ADDU_CP2:
3983 tcg_gen_add_i64(t0, t0, t1);
3984 tcg_gen_ext32s_i64(t0, t0);
3985 break;
3986 case OPC_SUBU_CP2:
3987 tcg_gen_sub_i64(t0, t0, t1);
3988 tcg_gen_ext32s_i64(t0, t0);
3989 break;
3990
3991 case OPC_SLL_CP2:
3992 shift_max = 32;
3993 goto do_shift;
3994 case OPC_SRL_CP2:
3995 shift_max = 32;
3996 goto do_shift;
3997 case OPC_SRA_CP2:
3998 shift_max = 32;
3999 goto do_shift;
4000 case OPC_DSLL_CP2:
4001 shift_max = 64;
4002 goto do_shift;
4003 case OPC_DSRL_CP2:
4004 shift_max = 64;
4005 goto do_shift;
4006 case OPC_DSRA_CP2:
4007 shift_max = 64;
4008 goto do_shift;
4009 do_shift:
4010 /* Make sure shift count isn't TCG undefined behaviour. */
4011 tcg_gen_andi_i64(t1, t1, shift_max - 1);
4012
4013 switch (opc) {
4014 case OPC_SLL_CP2:
4015 case OPC_DSLL_CP2:
4016 tcg_gen_shl_i64(t0, t0, t1);
4017 break;
4018 case OPC_SRA_CP2:
4019 case OPC_DSRA_CP2:
4020 /*
4021 * Since SRA is UndefinedResult without sign-extended inputs,
4022 * we can treat SRA and DSRA the same.
4023 */
4024 tcg_gen_sar_i64(t0, t0, t1);
4025 break;
4026 case OPC_SRL_CP2:
4027 /* We want to shift in zeros for SRL; zero-extend first. */
4028 tcg_gen_ext32u_i64(t0, t0);
4029 /* FALLTHRU */
4030 case OPC_DSRL_CP2:
4031 tcg_gen_shr_i64(t0, t0, t1);
4032 break;
4033 }
4034
4035 if (shift_max == 32) {
4036 tcg_gen_ext32s_i64(t0, t0);
4037 }
4038
4039 /* Shifts larger than MAX produce zero. */
4040 tcg_gen_setcondi_i64(TCG_COND_LTU, t1, t1, shift_max);
4041 tcg_gen_neg_i64(t1, t1);
4042 tcg_gen_and_i64(t0, t0, t1);
4043 break;
4044
4045 case OPC_ADD_CP2:
4046 case OPC_DADD_CP2:
4047 {
4048 TCGv_i64 t2 = tcg_temp_new_i64();
4049 TCGLabel *lab = gen_new_label();
4050
4051 tcg_gen_mov_i64(t2, t0);
4052 tcg_gen_add_i64(t0, t1, t2);
4053 if (opc == OPC_ADD_CP2) {
4054 tcg_gen_ext32s_i64(t0, t0);
4055 }
4056 tcg_gen_xor_i64(t1, t1, t2);
4057 tcg_gen_xor_i64(t2, t2, t0);
4058 tcg_gen_andc_i64(t1, t2, t1);
4059 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4060 generate_exception(ctx, EXCP_OVERFLOW);
4061 gen_set_label(lab);
4062 break;
4063 }
4064
4065 case OPC_SUB_CP2:
4066 case OPC_DSUB_CP2:
4067 {
4068 TCGv_i64 t2 = tcg_temp_new_i64();
4069 TCGLabel *lab = gen_new_label();
4070
4071 tcg_gen_mov_i64(t2, t0);
4072 tcg_gen_sub_i64(t0, t1, t2);
4073 if (opc == OPC_SUB_CP2) {
4074 tcg_gen_ext32s_i64(t0, t0);
4075 }
4076 tcg_gen_xor_i64(t1, t1, t2);
4077 tcg_gen_xor_i64(t2, t2, t0);
4078 tcg_gen_and_i64(t1, t1, t2);
4079 tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab);
4080 generate_exception(ctx, EXCP_OVERFLOW);
4081 gen_set_label(lab);
4082 break;
4083 }
4084
4085 case OPC_PMULUW:
4086 tcg_gen_ext32u_i64(t0, t0);
4087 tcg_gen_ext32u_i64(t1, t1);
4088 tcg_gen_mul_i64(t0, t0, t1);
4089 break;
4090
4091 case OPC_SEQU_CP2:
4092 case OPC_SEQ_CP2:
4093 cond = TCG_COND_EQ;
4094 goto do_cc_cond;
4095 break;
4096 case OPC_SLTU_CP2:
4097 cond = TCG_COND_LTU;
4098 goto do_cc_cond;
4099 break;
4100 case OPC_SLT_CP2:
4101 cond = TCG_COND_LT;
4102 goto do_cc_cond;
4103 break;
4104 case OPC_SLEU_CP2:
4105 cond = TCG_COND_LEU;
4106 goto do_cc_cond;
4107 break;
4108 case OPC_SLE_CP2:
4109 cond = TCG_COND_LE;
4110 do_cc_cond:
4111 {
4112 int cc = (ctx->opcode >> 8) & 0x7;
4113 TCGv_i64 t64 = tcg_temp_new_i64();
4114 TCGv_i32 t32 = tcg_temp_new_i32();
4115
4116 tcg_gen_setcond_i64(cond, t64, t0, t1);
4117 tcg_gen_extrl_i64_i32(t32, t64);
4118 tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32,
4119 get_fp_bit(cc), 1);
4120 }
4121 return;
4122 default:
4123 MIPS_INVAL("loongson_cp2");
4124 gen_reserved_instruction(ctx);
4125 return;
4126 }
4127
4128 gen_store_fpr64(ctx, t0, rd);
4129 }
4130
4131 static void gen_loongson_lswc2(DisasContext *ctx, int rt,
4132 int rs, int rd)
4133 {
4134 TCGv t0, t1;
4135 TCGv_i32 fp0;
4136 #if defined(TARGET_MIPS64)
4137 int lsq_rt1 = ctx->opcode & 0x1f;
4138 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4;
4139 #endif
4140 int shf_offset = sextract32(ctx->opcode, 6, 8);
4141
4142 t0 = tcg_temp_new();
4143
4144 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) {
4145 #if defined(TARGET_MIPS64)
4146 case OPC_GSLQ:
4147 t1 = tcg_temp_new();
4148 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4149 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4150 ctx->default_tcg_memop_mask);
4151 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4152 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4153 ctx->default_tcg_memop_mask);
4154 gen_store_gpr(t1, rt);
4155 gen_store_gpr(t0, lsq_rt1);
4156 break;
4157 case OPC_GSLQC1:
4158 check_cp1_enabled(ctx);
4159 t1 = tcg_temp_new();
4160 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4161 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4162 ctx->default_tcg_memop_mask);
4163 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4164 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4165 ctx->default_tcg_memop_mask);
4166 gen_store_fpr64(ctx, t1, rt);
4167 gen_store_fpr64(ctx, t0, lsq_rt1);
4168 break;
4169 case OPC_GSSQ:
4170 t1 = tcg_temp_new();
4171 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4172 gen_load_gpr(t1, rt);
4173 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4174 ctx->default_tcg_memop_mask);
4175 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4176 gen_load_gpr(t1, lsq_rt1);
4177 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4178 ctx->default_tcg_memop_mask);
4179 break;
4180 case OPC_GSSQC1:
4181 check_cp1_enabled(ctx);
4182 t1 = tcg_temp_new();
4183 gen_base_offset_addr(ctx, t0, rs, lsq_offset);
4184 gen_load_fpr64(ctx, t1, rt);
4185 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4186 ctx->default_tcg_memop_mask);
4187 gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
4188 gen_load_fpr64(ctx, t1, lsq_rt1);
4189 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4190 ctx->default_tcg_memop_mask);
4191 break;
4192 #endif
4193 case OPC_GSSHFL:
4194 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
4195 case OPC_GSLWLC1:
4196 check_cp1_enabled(ctx);
4197 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4198 fp0 = tcg_temp_new_i32();
4199 gen_load_fpr32(ctx, fp0, rt);
4200 t1 = tcg_temp_new();
4201 tcg_gen_ext_i32_tl(t1, fp0);
4202 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
4203 tcg_gen_trunc_tl_i32(fp0, t1);
4204 gen_store_fpr32(ctx, fp0, rt);
4205 break;
4206 case OPC_GSLWRC1:
4207 check_cp1_enabled(ctx);
4208 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4209 fp0 = tcg_temp_new_i32();
4210 gen_load_fpr32(ctx, fp0, rt);
4211 t1 = tcg_temp_new();
4212 tcg_gen_ext_i32_tl(t1, fp0);
4213 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
4214 tcg_gen_trunc_tl_i32(fp0, t1);
4215 gen_store_fpr32(ctx, fp0, rt);
4216 break;
4217 #if defined(TARGET_MIPS64)
4218 case OPC_GSLDLC1:
4219 check_cp1_enabled(ctx);
4220 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4221 t1 = tcg_temp_new();
4222 gen_load_fpr64(ctx, t1, rt);
4223 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
4224 gen_store_fpr64(ctx, t1, rt);
4225 break;
4226 case OPC_GSLDRC1:
4227 check_cp1_enabled(ctx);
4228 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4229 t1 = tcg_temp_new();
4230 gen_load_fpr64(ctx, t1, rt);
4231 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
4232 gen_store_fpr64(ctx, t1, rt);
4233 break;
4234 #endif
4235 default:
4236 MIPS_INVAL("loongson_gsshfl");
4237 gen_reserved_instruction(ctx);
4238 break;
4239 }
4240 break;
4241 case OPC_GSSHFS:
4242 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) {
4243 case OPC_GSSWLC1:
4244 check_cp1_enabled(ctx);
4245 t1 = tcg_temp_new();
4246 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4247 fp0 = tcg_temp_new_i32();
4248 gen_load_fpr32(ctx, fp0, rt);
4249 tcg_gen_ext_i32_tl(t1, fp0);
4250 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx);
4251 break;
4252 case OPC_GSSWRC1:
4253 check_cp1_enabled(ctx);
4254 t1 = tcg_temp_new();
4255 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4256 fp0 = tcg_temp_new_i32();
4257 gen_load_fpr32(ctx, fp0, rt);
4258 tcg_gen_ext_i32_tl(t1, fp0);
4259 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx);
4260 break;
4261 #if defined(TARGET_MIPS64)
4262 case OPC_GSSDLC1:
4263 check_cp1_enabled(ctx);
4264 t1 = tcg_temp_new();
4265 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4266 gen_load_fpr64(ctx, t1, rt);
4267 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx);
4268 break;
4269 case OPC_GSSDRC1:
4270 check_cp1_enabled(ctx);
4271 t1 = tcg_temp_new();
4272 gen_base_offset_addr(ctx, t0, rs, shf_offset);
4273 gen_load_fpr64(ctx, t1, rt);
4274 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx);
4275 break;
4276 #endif
4277 default:
4278 MIPS_INVAL("loongson_gsshfs");
4279 gen_reserved_instruction(ctx);
4280 break;
4281 }
4282 break;
4283 default:
4284 MIPS_INVAL("loongson_gslsq");
4285 gen_reserved_instruction(ctx);
4286 break;
4287 }
4288 }
4289
4290 /* Loongson EXT LDC2/SDC2 */
4291 static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
4292 int rs, int rd)
4293 {
4294 int offset = sextract32(ctx->opcode, 3, 8);
4295 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode);
4296 TCGv t0, t1;
4297 TCGv_i32 fp0;
4298
4299 /* Pre-conditions */
4300 switch (opc) {
4301 case OPC_GSLBX:
4302 case OPC_GSLHX:
4303 case OPC_GSLWX:
4304 case OPC_GSLDX:
4305 /* prefetch, implement as NOP */
4306 if (rt == 0) {
4307 return;
4308 }
4309 break;
4310 case OPC_GSSBX:
4311 case OPC_GSSHX:
4312 case OPC_GSSWX:
4313 case OPC_GSSDX:
4314 break;
4315 case OPC_GSLWXC1:
4316 #if defined(TARGET_MIPS64)
4317 case OPC_GSLDXC1:
4318 #endif
4319 check_cp1_enabled(ctx);
4320 /* prefetch, implement as NOP */
4321 if (rt == 0) {
4322 return;
4323 }
4324 break;
4325 case OPC_GSSWXC1:
4326 #if defined(TARGET_MIPS64)
4327 case OPC_GSSDXC1:
4328 #endif
4329 check_cp1_enabled(ctx);
4330 break;
4331 default:
4332 MIPS_INVAL("loongson_lsdc2");
4333 gen_reserved_instruction(ctx);
4334 return;
4335 break;
4336 }
4337
4338 t0 = tcg_temp_new();
4339
4340 gen_base_offset_addr(ctx, t0, rs, offset);
4341 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4342
4343 switch (opc) {
4344 case OPC_GSLBX:
4345 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
4346 gen_store_gpr(t0, rt);
4347 break;
4348 case OPC_GSLHX:
4349 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW |
4350 ctx->default_tcg_memop_mask);
4351 gen_store_gpr(t0, rt);
4352 break;
4353 case OPC_GSLWX:
4354 gen_base_offset_addr(ctx, t0, rs, offset);
4355 if (rd) {
4356 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4357 }
4358 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
4359 ctx->default_tcg_memop_mask);
4360 gen_store_gpr(t0, rt);
4361 break;
4362 #if defined(TARGET_MIPS64)
4363 case OPC_GSLDX:
4364 gen_base_offset_addr(ctx, t0, rs, offset);
4365 if (rd) {
4366 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4367 }
4368 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4369 ctx->default_tcg_memop_mask);
4370 gen_store_gpr(t0, rt);
4371 break;
4372 #endif
4373 case OPC_GSLWXC1:
4374 gen_base_offset_addr(ctx, t0, rs, offset);
4375 if (rd) {
4376 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4377 }
4378 fp0 = tcg_temp_new_i32();
4379 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
4380 ctx->default_tcg_memop_mask);
4381 gen_store_fpr32(ctx, fp0, rt);
4382 break;
4383 #if defined(TARGET_MIPS64)
4384 case OPC_GSLDXC1:
4385 gen_base_offset_addr(ctx, t0, rs, offset);
4386 if (rd) {
4387 gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
4388 }
4389 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4390 ctx->default_tcg_memop_mask);
4391 gen_store_fpr64(ctx, t0, rt);
4392 break;
4393 #endif
4394 case OPC_GSSBX:
4395 t1 = tcg_temp_new();
4396 gen_load_gpr(t1, rt);
4397 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB);
4398 break;
4399 case OPC_GSSHX:
4400 t1 = tcg_temp_new();
4401 gen_load_gpr(t1, rt);
4402 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW |
4403 ctx->default_tcg_memop_mask);
4404 break;
4405 case OPC_GSSWX:
4406 t1 = tcg_temp_new();
4407 gen_load_gpr(t1, rt);
4408 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
4409 ctx->default_tcg_memop_mask);
4410 break;
4411 #if defined(TARGET_MIPS64)
4412 case OPC_GSSDX:
4413 t1 = tcg_temp_new();
4414 gen_load_gpr(t1, rt);
4415 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4416 ctx->default_tcg_memop_mask);
4417 break;
4418 #endif
4419 case OPC_GSSWXC1:
4420 fp0 = tcg_temp_new_i32();
4421 gen_load_fpr32(ctx, fp0, rt);
4422 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
4423 ctx->default_tcg_memop_mask);
4424 break;
4425 #if defined(TARGET_MIPS64)
4426 case OPC_GSSDXC1:
4427 t1 = tcg_temp_new();
4428 gen_load_fpr64(ctx, t1, rt);
4429 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
4430 ctx->default_tcg_memop_mask);
4431 break;
4432 #endif
4433 default:
4434 break;
4435 }
4436 }
4437
4438 /* Traps */
4439 static void gen_trap(DisasContext *ctx, uint32_t opc,
4440 int rs, int rt, int16_t imm, int code)
4441 {
4442 int cond;
4443 TCGv t0 = tcg_temp_new();
4444 TCGv t1 = tcg_temp_new();
4445
4446 cond = 0;
4447 /* Load needed operands */
4448 switch (opc) {
4449 case OPC_TEQ:
4450 case OPC_TGE:
4451 case OPC_TGEU:
4452 case OPC_TLT:
4453 case OPC_TLTU:
4454 case OPC_TNE:
4455 /* Compare two registers */
4456 if (rs != rt) {
4457 gen_load_gpr(t0, rs);
4458 gen_load_gpr(t1, rt);
4459 cond = 1;
4460 }
4461 break;
4462 case OPC_TEQI:
4463 case OPC_TGEI:
4464 case OPC_TGEIU:
4465 case OPC_TLTI:
4466 case OPC_TLTIU:
4467 case OPC_TNEI:
4468 /* Compare register to immediate */
4469 if (rs != 0 || imm != 0) {
4470 gen_load_gpr(t0, rs);
4471 tcg_gen_movi_tl(t1, (int32_t)imm);
4472 cond = 1;
4473 }
4474 break;
4475 }
4476 if (cond == 0) {
4477 switch (opc) {
4478 case OPC_TEQ: /* rs == rs */
4479 case OPC_TEQI: /* r0 == 0 */
4480 case OPC_TGE: /* rs >= rs */
4481 case OPC_TGEI: /* r0 >= 0 */
4482 case OPC_TGEU: /* rs >= rs unsigned */
4483 case OPC_TGEIU: /* r0 >= 0 unsigned */
4484 /* Always trap */
4485 #ifdef CONFIG_USER_ONLY
4486 /* Pass the break code along to cpu_loop. */
4487 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
4488 offsetof(CPUMIPSState, error_code));
4489 #endif
4490 generate_exception_end(ctx, EXCP_TRAP);
4491 break;
4492 case OPC_TLT: /* rs < rs */
4493 case OPC_TLTI: /* r0 < 0 */
4494 case OPC_TLTU: /* rs < rs unsigned */
4495 case OPC_TLTIU: /* r0 < 0 unsigned */
4496 case OPC_TNE: /* rs != rs */
4497 case OPC_TNEI: /* r0 != 0 */
4498 /* Never trap: treat as NOP. */
4499 break;
4500 }
4501 } else {
4502 TCGLabel *l1 = gen_new_label();
4503
4504 switch (opc) {
4505 case OPC_TEQ:
4506 case OPC_TEQI:
4507 tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1);
4508 break;
4509 case OPC_TGE:
4510 case OPC_TGEI:
4511 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
4512 break;
4513 case OPC_TGEU:
4514 case OPC_TGEIU:
4515 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
4516 break;
4517 case OPC_TLT:
4518 case OPC_TLTI:
4519 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4520 break;
4521 case OPC_TLTU:
4522 case OPC_TLTIU:
4523 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
4524 break;
4525 case OPC_TNE:
4526 case OPC_TNEI:
4527 tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1);
4528 break;
4529 }
4530 #ifdef CONFIG_USER_ONLY
4531 /* Pass the break code along to cpu_loop. */
4532 tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
4533 offsetof(CPUMIPSState, error_code));
4534 #endif
4535 /* Like save_cpu_state, only don't update saved values. */
4536 if (ctx->base.pc_next != ctx->saved_pc) {
4537 gen_save_pc(ctx->base.pc_next);
4538 }
4539 if (ctx->hflags != ctx->saved_hflags) {
4540 tcg_gen_movi_i32(hflags, ctx->hflags);
4541 }
4542 generate_exception(ctx, EXCP_TRAP);
4543 gen_set_label(l1);
4544 }
4545 }
4546
4547 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
4548 {
4549 if (translator_use_goto_tb(&ctx->base, dest)) {
4550 tcg_gen_goto_tb(n);
4551 gen_save_pc(dest);
4552 tcg_gen_exit_tb(ctx->base.tb, n);
4553 } else {
4554 gen_save_pc(dest);
4555 tcg_gen_lookup_and_goto_ptr();
4556 }
4557 }
4558
4559 /* Branches (before delay slot) */
4560 static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
4561 int insn_bytes,
4562 int rs, int rt, int32_t offset,
4563 int delayslot_size)
4564 {
4565 target_ulong btgt = -1;
4566 int blink = 0;
4567 int bcond_compute = 0;
4568 TCGv t0 = tcg_temp_new();
4569 TCGv t1 = tcg_temp_new();
4570
4571 if (ctx->hflags & MIPS_HFLAG_BMASK) {
4572 #ifdef MIPS_DEBUG_DISAS
4573 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
4574 VADDR_PRIx "\n", ctx->base.pc_next);
4575 #endif
4576 gen_reserved_instruction(ctx);
4577 goto out;
4578 }
4579
4580 /* Load needed operands */
4581 switch (opc) {
4582 case OPC_BEQ:
4583 case OPC_BEQL:
4584 case OPC_BNE:
4585 case OPC_BNEL:
4586 /* Compare two registers */
4587 if (rs != rt) {
4588 gen_load_gpr(t0, rs);
4589 gen_load_gpr(t1, rt);
4590 bcond_compute = 1;
4591 }
4592 btgt = ctx->base.pc_next + insn_bytes + offset;
4593 break;
4594 case OPC_BGEZ:
4595 case OPC_BGEZAL:
4596 case OPC_BGEZALL:
4597 case OPC_BGEZL:
4598 case OPC_BGTZ:
4599 case OPC_BGTZL:
4600 case OPC_BLEZ:
4601 case OPC_BLEZL:
4602 case OPC_BLTZ:
4603 case OPC_BLTZAL:
4604 case OPC_BLTZALL:
4605 case OPC_BLTZL:
4606 /* Compare to zero */
4607 if (rs != 0) {
4608 gen_load_gpr(t0, rs);
4609 bcond_compute = 1;
4610 }
4611 btgt = ctx->base.pc_next + insn_bytes + offset;
4612 break;
4613 case OPC_BPOSGE32:
4614 #if defined(TARGET_MIPS64)
4615 case OPC_BPOSGE64:
4616 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
4617 #else
4618 tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
4619 #endif
4620 bcond_compute = 1;
4621 btgt = ctx->base.pc_next + insn_bytes + offset;
4622 break;
4623 case OPC_J:
4624 case OPC_JAL:
4625 {
4626 /* Jump to immediate */
4627 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000
4628 : 0xF0000000;
4629 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask)
4630 | (uint32_t)offset;
4631 break;
4632 }
4633 case OPC_JALX:
4634 /* Jump to immediate */
4635 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
4636 (uint32_t)offset;
4637 break;
4638 case OPC_JR:
4639 case OPC_JALR:
4640 /* Jump to register */
4641 if (offset != 0 && offset != 16) {
4642 /*
4643 * Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
4644 * others are reserved.
4645 */
4646 MIPS_INVAL("jump hint");
4647 gen_reserved_instruction(ctx);
4648 goto out;
4649 }
4650 gen_load_gpr(btarget, rs);
4651 break;
4652 default:
4653 MIPS_INVAL("branch/jump");
4654 gen_reserved_instruction(ctx);
4655 goto out;
4656 }
4657 if (bcond_compute == 0) {
4658 /* No condition to be computed */
4659 switch (opc) {
4660 case OPC_BEQ: /* rx == rx */
4661 case OPC_BEQL: /* rx == rx likely */
4662 case OPC_BGEZ: /* 0 >= 0 */
4663 case OPC_BGEZL: /* 0 >= 0 likely */
4664 case OPC_BLEZ: /* 0 <= 0 */
4665 case OPC_BLEZL: /* 0 <= 0 likely */
4666 /* Always take */
4667 ctx->hflags |= MIPS_HFLAG_B;
4668 break;
4669 case OPC_BGEZAL: /* 0 >= 0 */
4670 case OPC_BGEZALL: /* 0 >= 0 likely */
4671 /* Always take and link */
4672 blink = 31;
4673 ctx->hflags |= MIPS_HFLAG_B;
4674 break;
4675 case OPC_BNE: /* rx != rx */
4676 case OPC_BGTZ: /* 0 > 0 */
4677 case OPC_BLTZ: /* 0 < 0 */
4678 /* Treat as NOP. */
4679 goto out;
4680 case OPC_BLTZAL: /* 0 < 0 */
4681 /*
4682 * Handle as an unconditional branch to get correct delay
4683 * slot checking.
4684 */
4685 blink = 31;
4686 btgt = ctx->base.pc_next + insn_bytes + delayslot_size;
4687 ctx->hflags |= MIPS_HFLAG_B;
4688 break;
4689 case OPC_BLTZALL: /* 0 < 0 likely */
4690 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8);
4691 /* Skip the instruction in the delay slot */
4692 ctx->base.pc_next += 4;
4693 goto out;
4694 case OPC_BNEL: /* rx != rx likely */
4695 case OPC_BGTZL: /* 0 > 0 likely */
4696 case OPC_BLTZL: /* 0 < 0 likely */
4697 /* Skip the instruction in the delay slot */
4698 ctx->base.pc_next += 4;
4699 goto out;
4700 case OPC_J:
4701 ctx->hflags |= MIPS_HFLAG_B;
4702 break;
4703 case OPC_JALX:
4704 ctx->hflags |= MIPS_HFLAG_BX;
4705 /* Fallthrough */
4706 case OPC_JAL:
4707 blink = 31;
4708 ctx->hflags |= MIPS_HFLAG_B;
4709 break;
4710 case OPC_JR:
4711 ctx->hflags |= MIPS_HFLAG_BR;
4712 break;
4713 case OPC_JALR:
4714 blink = rt;
4715 ctx->hflags |= MIPS_HFLAG_BR;
4716 break;
4717 default:
4718 MIPS_INVAL("branch/jump");
4719 gen_reserved_instruction(ctx);
4720 goto out;
4721 }
4722 } else {
4723 switch (opc) {
4724 case OPC_BEQ:
4725 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4726 goto not_likely;
4727 case OPC_BEQL:
4728 tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1);
4729 goto likely;
4730 case OPC_BNE:
4731 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
4732 goto not_likely;
4733 case OPC_BNEL:
4734 tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1);
4735 goto likely;
4736 case OPC_BGEZ:
4737 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4738 goto not_likely;
4739 case OPC_BGEZL:
4740 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4741 goto likely;
4742 case OPC_BGEZAL:
4743 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4744 blink = 31;
4745 goto not_likely;
4746 case OPC_BGEZALL:
4747 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0);
4748 blink = 31;
4749 goto likely;
4750 case OPC_BGTZ:
4751 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
4752 goto not_likely;
4753 case OPC_BGTZL:
4754 tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0);
4755 goto likely;
4756 case OPC_BLEZ:
4757 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
4758 goto not_likely;
4759 case OPC_BLEZL:
4760 tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0);
4761 goto likely;
4762 case OPC_BLTZ:
4763 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4764 goto not_likely;
4765 case OPC_BLTZL:
4766 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4767 goto likely;
4768 case OPC_BPOSGE32:
4769 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
4770 goto not_likely;
4771 #if defined(TARGET_MIPS64)
4772 case OPC_BPOSGE64:
4773 tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
4774 goto not_likely;
4775 #endif
4776 case OPC_BLTZAL:
4777 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4778 blink = 31;
4779 not_likely:
4780 ctx->hflags |= MIPS_HFLAG_BC;
4781 break;
4782 case OPC_BLTZALL:
4783 tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
4784 blink = 31;
4785 likely:
4786 ctx->hflags |= MIPS_HFLAG_BL;
4787 break;
4788 default:
4789 MIPS_INVAL("conditional branch/jump");
4790 gen_reserved_instruction(ctx);
4791 goto out;
4792 }
4793 }
4794
4795 ctx->btarget = btgt;
4796
4797 switch (delayslot_size) {
4798 case 2:
4799 ctx->hflags |= MIPS_HFLAG_BDS16;
4800 break;
4801 case 4:
4802 ctx->hflags |= MIPS_HFLAG_BDS32;
4803 break;
4804 }
4805
4806 if (blink > 0) {
4807 int post_delay = insn_bytes + delayslot_size;
4808 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
4809
4810 tcg_gen_movi_tl(cpu_gpr[blink],
4811 ctx->base.pc_next + post_delay + lowbit);
4812 }
4813
4814 out:
4815 if (insn_bytes == 2) {
4816 ctx->hflags |= MIPS_HFLAG_B16;
4817 }
4818 }
4819
4820
4821 /* special3 bitfield operations */
4822 static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
4823 int rs, int lsb, int msb)
4824 {
4825 TCGv t0 = tcg_temp_new();
4826 TCGv t1 = tcg_temp_new();
4827
4828 gen_load_gpr(t1, rs);
4829 switch (opc) {
4830 case OPC_EXT:
4831 if (lsb + msb > 31) {
4832 goto fail;
4833 }
4834 if (msb != 31) {
4835 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
4836 } else {
4837 /*
4838 * The two checks together imply that lsb == 0,
4839 * so this is a simple sign-extension.
4840 */
4841 tcg_gen_ext32s_tl(t0, t1);
4842 }
4843 break;
4844 #if defined(TARGET_MIPS64)
4845 case OPC_DEXTU:
4846 lsb += 32;
4847 goto do_dext;
4848 case OPC_DEXTM:
4849 msb += 32;
4850 goto do_dext;
4851 case OPC_DEXT:
4852 do_dext:
4853 if (lsb + msb > 63) {
4854 goto fail;
4855 }
4856 tcg_gen_extract_tl(t0, t1, lsb, msb + 1);
4857 break;
4858 #endif
4859 case OPC_INS:
4860 if (lsb > msb) {
4861 goto fail;
4862 }
4863 gen_load_gpr(t0, rt);
4864 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
4865 tcg_gen_ext32s_tl(t0, t0);
4866 break;
4867 #if defined(TARGET_MIPS64)
4868 case OPC_DINSU:
4869 lsb += 32;
4870 /* FALLTHRU */
4871 case OPC_DINSM:
4872 msb += 32;
4873 /* FALLTHRU */
4874 case OPC_DINS:
4875 if (lsb > msb) {
4876 goto fail;
4877 }
4878 gen_load_gpr(t0, rt);
4879 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1);
4880 break;
4881 #endif
4882 default:
4883 fail:
4884 MIPS_INVAL("bitops");
4885 gen_reserved_instruction(ctx);
4886 return;
4887 }
4888 gen_store_gpr(t0, rt);
4889 }
4890
4891 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
4892 {
4893 TCGv t0;
4894
4895 if (rd == 0) {
4896 /* If no destination, treat it as a NOP. */
4897 return;
4898 }
4899
4900 t0 = tcg_temp_new();
4901 gen_load_gpr(t0, rt);
4902 switch (op2) {
4903 case OPC_WSBH:
4904 {
4905 TCGv t1 = tcg_temp_new();
4906 TCGv t2 = tcg_constant_tl(0x00FF00FF);
4907
4908 tcg_gen_shri_tl(t1, t0, 8);
4909 tcg_gen_and_tl(t1, t1, t2);
4910 tcg_gen_and_tl(t0, t0, t2);
4911 tcg_gen_shli_tl(t0, t0, 8);
4912 tcg_gen_or_tl(t0, t0, t1);
4913 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4914 }
4915 break;
4916 case OPC_SEB:
4917 tcg_gen_ext8s_tl(cpu_gpr[rd], t0);
4918 break;
4919 case OPC_SEH:
4920 tcg_gen_ext16s_tl(cpu_gpr[rd], t0);
4921 break;
4922 #if defined(TARGET_MIPS64)
4923 case OPC_DSBH:
4924 {
4925 TCGv t1 = tcg_temp_new();
4926 TCGv t2 = tcg_constant_tl(0x00FF00FF00FF00FFULL);
4927
4928 tcg_gen_shri_tl(t1, t0, 8);
4929 tcg_gen_and_tl(t1, t1, t2);
4930 tcg_gen_and_tl(t0, t0, t2);
4931 tcg_gen_shli_tl(t0, t0, 8);
4932 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
4933 }
4934 break;
4935 case OPC_DSHD:
4936 {
4937 TCGv t1 = tcg_temp_new();
4938 TCGv t2 = tcg_constant_tl(0x0000FFFF0000FFFFULL);
4939
4940 tcg_gen_shri_tl(t1, t0, 16);
4941 tcg_gen_and_tl(t1, t1, t2);
4942 tcg_gen_and_tl(t0, t0, t2);
4943 tcg_gen_shli_tl(t0, t0, 16);
4944 tcg_gen_or_tl(t0, t0, t1);
4945 tcg_gen_shri_tl(t1, t0, 32);
4946 tcg_gen_shli_tl(t0, t0, 32);
4947 tcg_gen_or_tl(cpu_gpr[rd], t0, t1);
4948 }
4949 break;
4950 #endif
4951 default:
4952 MIPS_INVAL("bsfhl");
4953 gen_reserved_instruction(ctx);
4954 return;
4955 }
4956 }
4957
4958 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
4959 int rt, int bits)
4960 {
4961 TCGv t0;
4962 if (rd == 0) {
4963 /* Treat as NOP. */
4964 return;
4965 }
4966 t0 = tcg_temp_new();
4967 if (bits == 0 || bits == wordsz) {
4968 if (bits == 0) {
4969 gen_load_gpr(t0, rt);
4970 } else {
4971 gen_load_gpr(t0, rs);
4972 }
4973 switch (wordsz) {
4974 case 32:
4975 tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
4976 break;
4977 #if defined(TARGET_MIPS64)
4978 case 64:
4979 tcg_gen_mov_tl(cpu_gpr[rd], t0);
4980 break;
4981 #endif
4982 }
4983 } else {
4984 TCGv t1 = tcg_temp_new();
4985 gen_load_gpr(t0, rt);
4986 gen_load_gpr(t1, rs);
4987 switch (wordsz) {
4988 case 32:
4989 {
4990 TCGv_i64 t2 = tcg_temp_new_i64();
4991 tcg_gen_concat_tl_i64(t2, t1, t0);
4992 tcg_gen_shri_i64(t2, t2, 32 - bits);
4993 gen_move_low32(cpu_gpr[rd], t2);
4994 }
4995 break;
4996 #if defined(TARGET_MIPS64)
4997 case 64:
4998 tcg_gen_shli_tl(t0, t0, bits);
4999 tcg_gen_shri_tl(t1, t1, 64 - bits);
5000 tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
5001 break;
5002 #endif
5003 }
5004 }
5005 }
5006
5007 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int bp)
5008 {
5009 gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
5010 }
5011
5012 static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
5013 {
5014 TCGv t0;
5015 if (rd == 0) {
5016 /* Treat as NOP. */
5017 return;
5018 }
5019 t0 = tcg_temp_new();
5020 gen_load_gpr(t0, rt);
5021 switch (opc) {
5022 case OPC_BITSWAP:
5023 gen_helper_bitswap(cpu_gpr[rd], t0);
5024 break;
5025 #if defined(TARGET_MIPS64)
5026 case OPC_DBITSWAP:
5027 gen_helper_dbitswap(cpu_gpr[rd], t0);
5028 break;
5029 #endif
5030 }
5031 }
5032
5033 #ifndef CONFIG_USER_ONLY
5034 /* CP0 (MMU and control) */
5035 static inline void gen_mthc0_entrylo(TCGv arg, target_ulong off)
5036 {
5037 TCGv_i64 t0 = tcg_temp_new_i64();
5038 TCGv_i64 t1 = tcg_temp_new_i64();
5039
5040 tcg_gen_ext_tl_i64(t0, arg);
5041 tcg_gen_ld_i64(t1, tcg_env, off);
5042 #if defined(TARGET_MIPS64)
5043 tcg_gen_deposit_i64(t1, t1, t0, 30, 32);
5044 #else
5045 tcg_gen_concat32_i64(t1, t1, t0);
5046 #endif
5047 tcg_gen_st_i64(t1, tcg_env, off);
5048 }
5049
5050 static inline void gen_mthc0_store64(TCGv arg, target_ulong off)
5051 {
5052 TCGv_i64 t0 = tcg_temp_new_i64();
5053 TCGv_i64 t1 = tcg_temp_new_i64();
5054
5055 tcg_gen_ext_tl_i64(t0, arg);
5056 tcg_gen_ld_i64(t1, tcg_env, off);
5057 tcg_gen_concat32_i64(t1, t1, t0);
5058 tcg_gen_st_i64(t1, tcg_env, off);
5059 }
5060
5061 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off)
5062 {
5063 TCGv_i64 t0 = tcg_temp_new_i64();
5064
5065 tcg_gen_ld_i64(t0, tcg_env, off);
5066 #if defined(TARGET_MIPS64)
5067 tcg_gen_shri_i64(t0, t0, 30);
5068 #else
5069 tcg_gen_shri_i64(t0, t0, 32);
5070 #endif
5071 gen_move_low32(arg, t0);
5072 }
5073
5074 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift)
5075 {
5076 TCGv_i64 t0 = tcg_temp_new_i64();
5077
5078 tcg_gen_ld_i64(t0, tcg_env, off);
5079 tcg_gen_shri_i64(t0, t0, 32 + shift);
5080 gen_move_low32(arg, t0);
5081 }
5082
5083 static inline void gen_mfc0_load32(TCGv arg, target_ulong off)
5084 {
5085 TCGv_i32 t0 = tcg_temp_new_i32();
5086
5087 tcg_gen_ld_i32(t0, tcg_env, off);
5088 tcg_gen_ext_i32_tl(arg, t0);
5089 }
5090
5091 static inline void gen_mfc0_load64(TCGv arg, target_ulong off)
5092 {
5093 tcg_gen_ld_tl(arg, tcg_env, off);
5094 tcg_gen_ext32s_tl(arg, arg);
5095 }
5096
5097 static inline void gen_mtc0_store32(TCGv arg, target_ulong off)
5098 {
5099 TCGv_i32 t0 = tcg_temp_new_i32();
5100
5101 tcg_gen_trunc_tl_i32(t0, arg);
5102 tcg_gen_st_i32(t0, tcg_env, off);
5103 }
5104
5105 #define CP0_CHECK(c) \
5106 do { \
5107 if (!(c)) { \
5108 goto cp0_unimplemented; \
5109 } \
5110 } while (0)
5111
5112 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5113 {
5114 const char *register_name = "invalid";
5115
5116 switch (reg) {
5117 case CP0_REGISTER_02:
5118 switch (sel) {
5119 case 0:
5120 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5121 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
5122 register_name = "EntryLo0";
5123 break;
5124 default:
5125 goto cp0_unimplemented;
5126 }
5127 break;
5128 case CP0_REGISTER_03:
5129 switch (sel) {
5130 case CP0_REG03__ENTRYLO1:
5131 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5132 gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
5133 register_name = "EntryLo1";
5134 break;
5135 default:
5136 goto cp0_unimplemented;
5137 }
5138 break;
5139 case CP0_REGISTER_17:
5140 switch (sel) {
5141 case CP0_REG17__LLADDR:
5142 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
5143 ctx->CP0_LLAddr_shift);
5144 register_name = "LLAddr";
5145 break;
5146 case CP0_REG17__MAAR:
5147 CP0_CHECK(ctx->mrp);
5148 gen_helper_mfhc0_maar(arg, tcg_env);
5149 register_name = "MAAR";
5150 break;
5151 default:
5152 goto cp0_unimplemented;
5153 }
5154 break;
5155 case CP0_REGISTER_19:
5156 switch (sel) {
5157 case CP0_REG19__WATCHHI0:
5158 case CP0_REG19__WATCHHI1:
5159 case CP0_REG19__WATCHHI2:
5160 case CP0_REG19__WATCHHI3:
5161 case CP0_REG19__WATCHHI4:
5162 case CP0_REG19__WATCHHI5:
5163 case CP0_REG19__WATCHHI6:
5164 case CP0_REG19__WATCHHI7:
5165 /* upper 32 bits are only available when Config5MI != 0 */
5166 CP0_CHECK(ctx->mi);
5167 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0);
5168 register_name = "WatchHi";
5169 break;
5170 default:
5171 goto cp0_unimplemented;
5172 }
5173 break;
5174 case CP0_REGISTER_28:
5175 switch (sel) {
5176 case 0:
5177 case 2:
5178 case 4:
5179 case 6:
5180 gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_TagLo), 0);
5181 register_name = "TagLo";
5182 break;
5183 default:
5184 goto cp0_unimplemented;
5185 }
5186 break;
5187 default:
5188 goto cp0_unimplemented;
5189 }
5190 trace_mips_translate_c0("mfhc0", register_name, reg, sel);
5191 return;
5192
5193 cp0_unimplemented:
5194 qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n",
5195 register_name, reg, sel);
5196 tcg_gen_movi_tl(arg, 0);
5197 }
5198
5199 static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5200 {
5201 const char *register_name = "invalid";
5202 uint64_t mask = ctx->PAMask >> 36;
5203
5204 switch (reg) {
5205 case CP0_REGISTER_02:
5206 switch (sel) {
5207 case 0:
5208 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5209 tcg_gen_andi_tl(arg, arg, mask);
5210 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
5211 register_name = "EntryLo0";
5212 break;
5213 default:
5214 goto cp0_unimplemented;
5215 }
5216 break;
5217 case CP0_REGISTER_03:
5218 switch (sel) {
5219 case CP0_REG03__ENTRYLO1:
5220 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
5221 tcg_gen_andi_tl(arg, arg, mask);
5222 gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
5223 register_name = "EntryLo1";
5224 break;
5225 default:
5226 goto cp0_unimplemented;
5227 }
5228 break;
5229 case CP0_REGISTER_17:
5230 switch (sel) {
5231 case CP0_REG17__LLADDR:
5232 /*
5233 * LLAddr is read-only (the only exception is bit 0 if LLB is
5234 * supported); the CP0_LLAddr_rw_bitmask does not seem to be
5235 * relevant for modern MIPS cores supporting MTHC0, therefore
5236 * treating MTHC0 to LLAddr as NOP.
5237 */
5238 register_name = "LLAddr";
5239 break;
5240 case CP0_REG17__MAAR:
5241 CP0_CHECK(ctx->mrp);
5242 gen_helper_mthc0_maar(tcg_env, arg);
5243 register_name = "MAAR";
5244 break;
5245 default:
5246 goto cp0_unimplemented;
5247 }
5248 break;
5249 case CP0_REGISTER_19:
5250 switch (sel) {
5251 case CP0_REG19__WATCHHI0:
5252 case CP0_REG19__WATCHHI1:
5253 case CP0_REG19__WATCHHI2:
5254 case CP0_REG19__WATCHHI3:
5255 case CP0_REG19__WATCHHI4:
5256 case CP0_REG19__WATCHHI5:
5257 case CP0_REG19__WATCHHI6:
5258 case CP0_REG19__WATCHHI7:
5259 /* upper 32 bits are only available when Config5MI != 0 */
5260 CP0_CHECK(ctx->mi);
5261 gen_helper_0e1i(mthc0_watchhi, arg, sel);
5262 register_name = "WatchHi";
5263 break;
5264 default:
5265 goto cp0_unimplemented;
5266 }
5267 break;
5268 case CP0_REGISTER_28:
5269 switch (sel) {
5270 case 0:
5271 case 2:
5272 case 4:
5273 case 6:
5274 tcg_gen_andi_tl(arg, arg, mask);
5275 gen_mthc0_store64(arg, offsetof(CPUMIPSState, CP0_TagLo));
5276 register_name = "TagLo";
5277 break;
5278 default:
5279 goto cp0_unimplemented;
5280 }
5281 break;
5282 default:
5283 goto cp0_unimplemented;
5284 }
5285 trace_mips_translate_c0("mthc0", register_name, reg, sel);
5286 return;
5287
5288 cp0_unimplemented:
5289 qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n",
5290 register_name, reg, sel);
5291 }
5292
5293 static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
5294 {
5295 if (ctx->insn_flags & ISA_MIPS_R6) {
5296 tcg_gen_movi_tl(arg, 0);
5297 } else {
5298 tcg_gen_movi_tl(arg, ~0);
5299 }
5300 }
5301
5302 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
5303 {
5304 const char *register_name = "invalid";
5305
5306 if (sel != 0) {
5307 check_insn(ctx, ISA_MIPS_R1);
5308 }
5309
5310 switch (reg) {
5311 case CP0_REGISTER_00:
5312 switch (sel) {
5313 case CP0_REG00__INDEX:
5314 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
5315 register_name = "Index";
5316 break;
5317 case CP0_REG00__MVPCONTROL:
5318 CP0_CHECK(ctx->insn_flags & ASE_MT);
5319 gen_helper_mfc0_mvpcontrol(arg, tcg_env);
5320 register_name = "MVPControl";
5321 break;
5322 case CP0_REG00__MVPCONF0:
5323 CP0_CHECK(ctx->insn_flags & ASE_MT);
5324 gen_helper_mfc0_mvpconf0(arg, tcg_env);
5325 register_name = "MVPConf0";
5326 break;
5327 case CP0_REG00__MVPCONF1:
5328 CP0_CHECK(ctx->insn_flags & ASE_MT);
5329 gen_helper_mfc0_mvpconf1(arg, tcg_env);
5330 register_name = "MVPConf1";
5331 break;
5332 case CP0_REG00__VPCONTROL:
5333 CP0_CHECK(ctx->vp);
5334 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
5335 register_name = "VPControl";
5336 break;
5337 default:
5338 goto cp0_unimplemented;
5339 }
5340 break;
5341 case CP0_REGISTER_01:
5342 switch (sel) {
5343 case CP0_REG01__RANDOM:
5344 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
5345 gen_helper_mfc0_random(arg, tcg_env);
5346 register_name = "Random";
5347 break;
5348 case CP0_REG01__VPECONTROL:
5349 CP0_CHECK(ctx->insn_flags & ASE_MT);
5350 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
5351 register_name = "VPEControl";
5352 break;
5353 case CP0_REG01__VPECONF0:
5354 CP0_CHECK(ctx->insn_flags & ASE_MT);
5355 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
5356 register_name = "VPEConf0";
5357 break;
5358 case CP0_REG01__VPECONF1:
5359 CP0_CHECK(ctx->insn_flags & ASE_MT);
5360 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
5361 register_name = "VPEConf1";
5362 break;
5363 case CP0_REG01__YQMASK:
5364 CP0_CHECK(ctx->insn_flags & ASE_MT);
5365 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
5366 register_name = "YQMask";
5367 break;
5368 case CP0_REG01__VPESCHEDULE:
5369 CP0_CHECK(ctx->insn_flags & ASE_MT);
5370 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
5371 register_name = "VPESchedule";
5372 break;
5373 case CP0_REG01__VPESCHEFBACK:
5374 CP0_CHECK(ctx->insn_flags & ASE_MT);
5375 gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
5376 register_name = "VPEScheFBack";
5377 break;
5378 case CP0_REG01__VPEOPT:
5379 CP0_CHECK(ctx->insn_flags & ASE_MT);
5380 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
5381 register_name = "VPEOpt";
5382 break;
5383 default:
5384 goto cp0_unimplemented;
5385 }
5386 break;
5387 case CP0_REGISTER_02:
5388 switch (sel) {
5389 case CP0_REG02__ENTRYLO0:
5390 {
5391 TCGv_i64 tmp = tcg_temp_new_i64();
5392 tcg_gen_ld_i64(tmp, tcg_env,
5393 offsetof(CPUMIPSState, CP0_EntryLo0));
5394 #if defined(TARGET_MIPS64)
5395 if (ctx->rxi) {
5396 /* Move RI/XI fields to bits 31:30 */
5397 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5398 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5399 }
5400 #endif
5401 gen_move_low32(arg, tmp);
5402 }
5403 register_name = "EntryLo0";
5404 break;
5405 case CP0_REG02__TCSTATUS:
5406 CP0_CHECK(ctx->insn_flags & ASE_MT);
5407 gen_helper_mfc0_tcstatus(arg, tcg_env);
5408 register_name = "TCStatus";
5409 break;
5410 case CP0_REG02__TCBIND:
5411 CP0_CHECK(ctx->insn_flags & ASE_MT);
5412 gen_helper_mfc0_tcbind(arg, tcg_env);
5413 register_name = "TCBind";
5414 break;
5415 case CP0_REG02__TCRESTART:
5416 CP0_CHECK(ctx->insn_flags & ASE_MT);
5417 gen_helper_mfc0_tcrestart(arg, tcg_env);
5418 register_name = "TCRestart";
5419 break;
5420 case CP0_REG02__TCHALT:
5421 CP0_CHECK(ctx->insn_flags & ASE_MT);
5422 gen_helper_mfc0_tchalt(arg, tcg_env);
5423 register_name = "TCHalt";
5424 break;
5425 case CP0_REG02__TCCONTEXT:
5426 CP0_CHECK(ctx->insn_flags & ASE_MT);
5427 gen_helper_mfc0_tccontext(arg, tcg_env);
5428 register_name = "TCContext";
5429 break;
5430 case CP0_REG02__TCSCHEDULE:
5431 CP0_CHECK(ctx->insn_flags & ASE_MT);
5432 gen_helper_mfc0_tcschedule(arg, tcg_env);
5433 register_name = "TCSchedule";
5434 break;
5435 case CP0_REG02__TCSCHEFBACK:
5436 CP0_CHECK(ctx->insn_flags & ASE_MT);
5437 gen_helper_mfc0_tcschefback(arg, tcg_env);
5438 register_name = "TCScheFBack";
5439 break;
5440 default:
5441 goto cp0_unimplemented;
5442 }
5443 break;
5444 case CP0_REGISTER_03:
5445 switch (sel) {
5446 case CP0_REG03__ENTRYLO1:
5447 {
5448 TCGv_i64 tmp = tcg_temp_new_i64();
5449 tcg_gen_ld_i64(tmp, tcg_env,
5450 offsetof(CPUMIPSState, CP0_EntryLo1));
5451 #if defined(TARGET_MIPS64)
5452 if (ctx->rxi) {
5453 /* Move RI/XI fields to bits 31:30 */
5454 tcg_gen_shri_tl(arg, tmp, CP0EnLo_XI);
5455 tcg_gen_deposit_tl(tmp, tmp, arg, 30, 2);
5456 }
5457 #endif
5458 gen_move_low32(arg, tmp);
5459 }
5460 register_name = "EntryLo1";
5461 break;
5462 case CP0_REG03__GLOBALNUM:
5463 CP0_CHECK(ctx->vp);
5464 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
5465 register_name = "GlobalNumber";
5466 break;
5467 default:
5468 goto cp0_unimplemented;
5469 }
5470 break;
5471 case CP0_REGISTER_04:
5472 switch (sel) {
5473 case CP0_REG04__CONTEXT:
5474 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context));
5475 tcg_gen_ext32s_tl(arg, arg);
5476 register_name = "Context";
5477 break;
5478 case CP0_REG04__CONTEXTCONFIG:
5479 /* SmartMIPS ASE */
5480 /* gen_helper_mfc0_contextconfig(arg); */
5481 register_name = "ContextConfig";
5482 goto cp0_unimplemented;
5483 case CP0_REG04__USERLOCAL:
5484 CP0_CHECK(ctx->ulri);
5485 tcg_gen_ld_tl(arg, tcg_env,
5486 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
5487 tcg_gen_ext32s_tl(arg, arg);
5488 register_name = "UserLocal";
5489 break;
5490 case CP0_REG04__MMID:
5491 CP0_CHECK(ctx->mi);
5492 gen_helper_mtc0_memorymapid(tcg_env, arg);
5493 register_name = "MMID";
5494 break;
5495 default:
5496 goto cp0_unimplemented;
5497 }
5498 break;
5499 case CP0_REGISTER_05:
5500 switch (sel) {
5501 case CP0_REG05__PAGEMASK:
5502 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
5503 register_name = "PageMask";
5504 break;
5505 case CP0_REG05__PAGEGRAIN:
5506 check_insn(ctx, ISA_MIPS_R2);
5507 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
5508 register_name = "PageGrain";
5509 break;
5510 case CP0_REG05__SEGCTL0:
5511 CP0_CHECK(ctx->sc);
5512 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0));
5513 tcg_gen_ext32s_tl(arg, arg);
5514 register_name = "SegCtl0";
5515 break;
5516 case CP0_REG05__SEGCTL1:
5517 CP0_CHECK(ctx->sc);
5518 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1));
5519 tcg_gen_ext32s_tl(arg, arg);
5520 register_name = "SegCtl1";
5521 break;
5522 case CP0_REG05__SEGCTL2:
5523 CP0_CHECK(ctx->sc);
5524 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2));
5525 tcg_gen_ext32s_tl(arg, arg);
5526 register_name = "SegCtl2";
5527 break;
5528 case CP0_REG05__PWBASE:
5529 check_pw(ctx);
5530 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
5531 register_name = "PWBase";
5532 break;
5533 case CP0_REG05__PWFIELD:
5534 check_pw(ctx);
5535 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
5536 register_name = "PWField";
5537 break;
5538 case CP0_REG05__PWSIZE:
5539 check_pw(ctx);
5540 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
5541 register_name = "PWSize";
5542 break;
5543 default:
5544 goto cp0_unimplemented;
5545 }
5546 break;
5547 case CP0_REGISTER_06:
5548 switch (sel) {
5549 case CP0_REG06__WIRED:
5550 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
5551 register_name = "Wired";
5552 break;
5553 case CP0_REG06__SRSCONF0:
5554 check_insn(ctx, ISA_MIPS_R2);
5555 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
5556 register_name = "SRSConf0";
5557 break;
5558 case CP0_REG06__SRSCONF1:
5559 check_insn(ctx, ISA_MIPS_R2);
5560 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
5561 register_name = "SRSConf1";
5562 break;
5563 case CP0_REG06__SRSCONF2:
5564 check_insn(ctx, ISA_MIPS_R2);
5565 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
5566 register_name = "SRSConf2";
5567 break;
5568 case CP0_REG06__SRSCONF3:
5569 check_insn(ctx, ISA_MIPS_R2);
5570 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
5571 register_name = "SRSConf3";
5572 break;
5573 case CP0_REG06__SRSCONF4:
5574 check_insn(ctx, ISA_MIPS_R2);
5575 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
5576 register_name = "SRSConf4";
5577 break;
5578 case CP0_REG06__PWCTL:
5579 check_pw(ctx);
5580 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
5581 register_name = "PWCtl";
5582 break;
5583 default:
5584 goto cp0_unimplemented;
5585 }
5586 break;
5587 case CP0_REGISTER_07:
5588 switch (sel) {
5589 case CP0_REG07__HWRENA:
5590 check_insn(ctx, ISA_MIPS_R2);
5591 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
5592 register_name = "HWREna";
5593 break;
5594 default:
5595 goto cp0_unimplemented;
5596 }
5597 break;
5598 case CP0_REGISTER_08:
5599 switch (sel) {
5600 case CP0_REG08__BADVADDR:
5601 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
5602 tcg_gen_ext32s_tl(arg, arg);
5603 register_name = "BadVAddr";
5604 break;
5605 case CP0_REG08__BADINSTR:
5606 CP0_CHECK(ctx->bi);
5607 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
5608 register_name = "BadInstr";
5609 break;
5610 case CP0_REG08__BADINSTRP:
5611 CP0_CHECK(ctx->bp);
5612 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
5613 register_name = "BadInstrP";
5614 break;
5615 case CP0_REG08__BADINSTRX:
5616 CP0_CHECK(ctx->bi);
5617 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
5618 tcg_gen_andi_tl(arg, arg, ~0xffff);
5619 register_name = "BadInstrX";
5620 break;
5621 default:
5622 goto cp0_unimplemented;
5623 }
5624 break;
5625 case CP0_REGISTER_09:
5626 switch (sel) {
5627 case CP0_REG09__COUNT:
5628 /* Mark as an IO operation because we read the time. */
5629 translator_io_start(&ctx->base);
5630
5631 gen_helper_mfc0_count(arg, tcg_env);
5632 /*
5633 * Break the TB to be able to take timer interrupts immediately
5634 * after reading count. DISAS_STOP isn't sufficient, we need to
5635 * ensure we break completely out of translated code.
5636 */
5637 gen_save_pc(ctx->base.pc_next + 4);
5638 ctx->base.is_jmp = DISAS_EXIT;
5639 register_name = "Count";
5640 break;
5641 default:
5642 goto cp0_unimplemented;
5643 }
5644 break;
5645 case CP0_REGISTER_10:
5646 switch (sel) {
5647 case CP0_REG10__ENTRYHI:
5648 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi));
5649 tcg_gen_ext32s_tl(arg, arg);
5650 register_name = "EntryHi";
5651 break;
5652 default:
5653 goto cp0_unimplemented;
5654 }
5655 break;
5656 case CP0_REGISTER_11:
5657 switch (sel) {
5658 case CP0_REG11__COMPARE:
5659 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
5660 register_name = "Compare";
5661 break;
5662 /* 6,7 are implementation dependent */
5663 default:
5664 goto cp0_unimplemented;
5665 }
5666 break;
5667 case CP0_REGISTER_12:
5668 switch (sel) {
5669 case CP0_REG12__STATUS:
5670 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
5671 register_name = "Status";
5672 break;
5673 case CP0_REG12__INTCTL:
5674 check_insn(ctx, ISA_MIPS_R2);
5675 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
5676 register_name = "IntCtl";
5677 break;
5678 case CP0_REG12__SRSCTL:
5679 check_insn(ctx, ISA_MIPS_R2);
5680 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
5681 register_name = "SRSCtl";
5682 break;
5683 case CP0_REG12__SRSMAP:
5684 check_insn(ctx, ISA_MIPS_R2);
5685 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
5686 register_name = "SRSMap";
5687 break;
5688 default:
5689 goto cp0_unimplemented;
5690 }
5691 break;
5692 case CP0_REGISTER_13:
5693 switch (sel) {
5694 case CP0_REG13__CAUSE:
5695 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
5696 register_name = "Cause";
5697 break;
5698 default:
5699 goto cp0_unimplemented;
5700 }
5701 break;
5702 case CP0_REGISTER_14:
5703 switch (sel) {
5704 case CP0_REG14__EPC:
5705 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
5706 tcg_gen_ext32s_tl(arg, arg);
5707 register_name = "EPC";
5708 break;
5709 default:
5710 goto cp0_unimplemented;
5711 }
5712 break;
5713 case CP0_REGISTER_15:
5714 switch (sel) {
5715 case CP0_REG15__PRID:
5716 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
5717 register_name = "PRid";
5718 break;
5719 case CP0_REG15__EBASE:
5720 check_insn(ctx, ISA_MIPS_R2);
5721 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase));
5722 tcg_gen_ext32s_tl(arg, arg);
5723 register_name = "EBase";
5724 break;
5725 case CP0_REG15__CMGCRBASE:
5726 check_insn(ctx, ISA_MIPS_R2);
5727 CP0_CHECK(ctx->cmgcr);
5728 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
5729 tcg_gen_ext32s_tl(arg, arg);
5730 register_name = "CMGCRBase";
5731 break;
5732 default:
5733 goto cp0_unimplemented;
5734 }
5735 break;
5736 case CP0_REGISTER_16:
5737 switch (sel) {
5738 case CP0_REG16__CONFIG:
5739 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
5740 register_name = "Config";
5741 break;
5742 case CP0_REG16__CONFIG1:
5743 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
5744 register_name = "Config1";
5745 break;
5746 case CP0_REG16__CONFIG2:
5747 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
5748 register_name = "Config2";
5749 break;
5750 case CP0_REG16__CONFIG3:
5751 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
5752 register_name = "Config3";
5753 break;
5754 case CP0_REG16__CONFIG4:
5755 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
5756 register_name = "Config4";
5757 break;
5758 case CP0_REG16__CONFIG5:
5759 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
5760 register_name = "Config5";
5761 break;
5762 /* 6,7 are implementation dependent */
5763 case CP0_REG16__CONFIG6:
5764 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
5765 register_name = "Config6";
5766 break;
5767 case CP0_REG16__CONFIG7:
5768 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
5769 register_name = "Config7";
5770 break;
5771 default:
5772 goto cp0_unimplemented;
5773 }
5774 break;
5775 case CP0_REGISTER_17:
5776 switch (sel) {
5777 case CP0_REG17__LLADDR:
5778 gen_helper_mfc0_lladdr(arg, tcg_env);
5779 register_name = "LLAddr";
5780 break;
5781 case CP0_REG17__MAAR:
5782 CP0_CHECK(ctx->mrp);
5783 gen_helper_mfc0_maar(arg, tcg_env);
5784 register_name = "MAAR";
5785 break;
5786 case CP0_REG17__MAARI:
5787 CP0_CHECK(ctx->mrp);
5788 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
5789 register_name = "MAARI";
5790 break;
5791 default:
5792 goto cp0_unimplemented;
5793 }
5794 break;
5795 case CP0_REGISTER_18:
5796 switch (sel) {
5797 case CP0_REG18__WATCHLO0:
5798 case CP0_REG18__WATCHLO1:
5799 case CP0_REG18__WATCHLO2:
5800 case CP0_REG18__WATCHLO3:
5801 case CP0_REG18__WATCHLO4:
5802 case CP0_REG18__WATCHLO5:
5803 case CP0_REG18__WATCHLO6:
5804 case CP0_REG18__WATCHLO7:
5805 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
5806 gen_helper_1e0i(mfc0_watchlo, arg, sel);
5807 register_name = "WatchLo";
5808 break;
5809 default:
5810 goto cp0_unimplemented;
5811 }
5812 break;
5813 case CP0_REGISTER_19:
5814 switch (sel) {
5815 case CP0_REG19__WATCHHI0:
5816 case CP0_REG19__WATCHHI1:
5817 case CP0_REG19__WATCHHI2:
5818 case CP0_REG19__WATCHHI3:
5819 case CP0_REG19__WATCHHI4:
5820 case CP0_REG19__WATCHHI5:
5821 case CP0_REG19__WATCHHI6:
5822 case CP0_REG19__WATCHHI7:
5823 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
5824 gen_helper_1e0i(mfc0_watchhi, arg, sel);
5825 register_name = "WatchHi";
5826 break;
5827 default:
5828 goto cp0_unimplemented;
5829 }
5830 break;
5831 case CP0_REGISTER_20:
5832 switch (sel) {
5833 case CP0_REG20__XCONTEXT:
5834 #if defined(TARGET_MIPS64)
5835 check_insn(ctx, ISA_MIPS3);
5836 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext));
5837 tcg_gen_ext32s_tl(arg, arg);
5838 register_name = "XContext";
5839 break;
5840 #endif
5841 default:
5842 goto cp0_unimplemented;
5843 }
5844 break;
5845 case CP0_REGISTER_21:
5846 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5847 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
5848 switch (sel) {
5849 case 0:
5850 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
5851 register_name = "Framemask";
5852 break;
5853 default:
5854 goto cp0_unimplemented;
5855 }
5856 break;
5857 case CP0_REGISTER_22:
5858 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5859 register_name = "'Diagnostic"; /* implementation dependent */
5860 break;
5861 case CP0_REGISTER_23:
5862 switch (sel) {
5863 case CP0_REG23__DEBUG:
5864 gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */
5865 register_name = "Debug";
5866 break;
5867 case CP0_REG23__TRACECONTROL:
5868 /* PDtrace support */
5869 /* gen_helper_mfc0_tracecontrol(arg); */
5870 register_name = "TraceControl";
5871 goto cp0_unimplemented;
5872 case CP0_REG23__TRACECONTROL2:
5873 /* PDtrace support */
5874 /* gen_helper_mfc0_tracecontrol2(arg); */
5875 register_name = "TraceControl2";
5876 goto cp0_unimplemented;
5877 case CP0_REG23__USERTRACEDATA1:
5878 /* PDtrace support */
5879 /* gen_helper_mfc0_usertracedata1(arg);*/
5880 register_name = "UserTraceData1";
5881 goto cp0_unimplemented;
5882 case CP0_REG23__TRACEIBPC:
5883 /* PDtrace support */
5884 /* gen_helper_mfc0_traceibpc(arg); */
5885 register_name = "TraceIBPC";
5886 goto cp0_unimplemented;
5887 case CP0_REG23__TRACEDBPC:
5888 /* PDtrace support */
5889 /* gen_helper_mfc0_tracedbpc(arg); */
5890 register_name = "TraceDBPC";
5891 goto cp0_unimplemented;
5892 default:
5893 goto cp0_unimplemented;
5894 }
5895 break;
5896 case CP0_REGISTER_24:
5897 switch (sel) {
5898 case CP0_REG24__DEPC:
5899 /* EJTAG support */
5900 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
5901 tcg_gen_ext32s_tl(arg, arg);
5902 register_name = "DEPC";
5903 break;
5904 default:
5905 goto cp0_unimplemented;
5906 }
5907 break;
5908 case CP0_REGISTER_25:
5909 switch (sel) {
5910 case CP0_REG25__PERFCTL0:
5911 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
5912 register_name = "Performance0";
5913 break;
5914 case CP0_REG25__PERFCNT0:
5915 /* gen_helper_mfc0_performance1(arg); */
5916 register_name = "Performance1";
5917 goto cp0_unimplemented;
5918 case CP0_REG25__PERFCTL1:
5919 /* gen_helper_mfc0_performance2(arg); */
5920 register_name = "Performance2";
5921 goto cp0_unimplemented;
5922 case CP0_REG25__PERFCNT1:
5923 /* gen_helper_mfc0_performance3(arg); */
5924 register_name = "Performance3";
5925 goto cp0_unimplemented;
5926 case CP0_REG25__PERFCTL2:
5927 /* gen_helper_mfc0_performance4(arg); */
5928 register_name = "Performance4";
5929 goto cp0_unimplemented;
5930 case CP0_REG25__PERFCNT2:
5931 /* gen_helper_mfc0_performance5(arg); */
5932 register_name = "Performance5";
5933 goto cp0_unimplemented;
5934 case CP0_REG25__PERFCTL3:
5935 /* gen_helper_mfc0_performance6(arg); */
5936 register_name = "Performance6";
5937 goto cp0_unimplemented;
5938 case CP0_REG25__PERFCNT3:
5939 /* gen_helper_mfc0_performance7(arg); */
5940 register_name = "Performance7";
5941 goto cp0_unimplemented;
5942 default:
5943 goto cp0_unimplemented;
5944 }
5945 break;
5946 case CP0_REGISTER_26:
5947 switch (sel) {
5948 case CP0_REG26__ERRCTL:
5949 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
5950 register_name = "ErrCtl";
5951 break;
5952 default:
5953 goto cp0_unimplemented;
5954 }
5955 break;
5956 case CP0_REGISTER_27:
5957 switch (sel) {
5958 case CP0_REG27__CACHERR:
5959 tcg_gen_movi_tl(arg, 0); /* unimplemented */
5960 register_name = "CacheErr";
5961 break;
5962 default:
5963 goto cp0_unimplemented;
5964 }
5965 break;
5966 case CP0_REGISTER_28:
5967 switch (sel) {
5968 case CP0_REG28__TAGLO:
5969 case CP0_REG28__TAGLO1:
5970 case CP0_REG28__TAGLO2:
5971 case CP0_REG28__TAGLO3:
5972 {
5973 TCGv_i64 tmp = tcg_temp_new_i64();
5974 tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_TagLo));
5975 gen_move_low32(arg, tmp);
5976 }
5977 register_name = "TagLo";
5978 break;
5979 case CP0_REG28__DATALO:
5980 case CP0_REG28__DATALO1:
5981 case CP0_REG28__DATALO2:
5982 case CP0_REG28__DATALO3:
5983 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
5984 register_name = "DataLo";
5985 break;
5986 default:
5987 goto cp0_unimplemented;
5988 }
5989 break;
5990 case CP0_REGISTER_29:
5991 switch (sel) {
5992 case CP0_REG29__TAGHI:
5993 case CP0_REG29__TAGHI1:
5994 case CP0_REG29__TAGHI2:
5995 case CP0_REG29__TAGHI3:
5996 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
5997 register_name = "TagHi";
5998 break;
5999 case CP0_REG29__DATAHI:
6000 case CP0_REG29__DATAHI1:
6001 case CP0_REG29__DATAHI2:
6002 case CP0_REG29__DATAHI3:
6003 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
6004 register_name = "DataHi";
6005 break;
6006 default:
6007 goto cp0_unimplemented;
6008 }
6009 break;
6010 case CP0_REGISTER_30:
6011 switch (sel) {
6012 case CP0_REG30__ERROREPC:
6013 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6014 tcg_gen_ext32s_tl(arg, arg);
6015 register_name = "ErrorEPC";
6016 break;
6017 default:
6018 goto cp0_unimplemented;
6019 }
6020 break;
6021 case CP0_REGISTER_31:
6022 switch (sel) {
6023 case CP0_REG31__DESAVE:
6024 /* EJTAG support */
6025 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6026 register_name = "DESAVE";
6027 break;
6028 case CP0_REG31__KSCRATCH1:
6029 case CP0_REG31__KSCRATCH2:
6030 case CP0_REG31__KSCRATCH3:
6031 case CP0_REG31__KSCRATCH4:
6032 case CP0_REG31__KSCRATCH5:
6033 case CP0_REG31__KSCRATCH6:
6034 CP0_CHECK(ctx->kscrexist & (1 << sel));
6035 tcg_gen_ld_tl(arg, tcg_env,
6036 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
6037 tcg_gen_ext32s_tl(arg, arg);
6038 register_name = "KScratch";
6039 break;
6040 default:
6041 goto cp0_unimplemented;
6042 }
6043 break;
6044 default:
6045 goto cp0_unimplemented;
6046 }
6047 trace_mips_translate_c0("mfc0", register_name, reg, sel);
6048 return;
6049
6050 cp0_unimplemented:
6051 qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n",
6052 register_name, reg, sel);
6053 gen_mfc0_unimplemented(ctx, arg);
6054 }
6055
6056 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6057 {
6058 const char *register_name = "invalid";
6059 bool icount;
6060
6061 if (sel != 0) {
6062 check_insn(ctx, ISA_MIPS_R1);
6063 }
6064
6065 icount = translator_io_start(&ctx->base);
6066
6067 switch (reg) {
6068 case CP0_REGISTER_00:
6069 switch (sel) {
6070 case CP0_REG00__INDEX:
6071 gen_helper_mtc0_index(tcg_env, arg);
6072 register_name = "Index";
6073 break;
6074 case CP0_REG00__MVPCONTROL:
6075 CP0_CHECK(ctx->insn_flags & ASE_MT);
6076 gen_helper_mtc0_mvpcontrol(tcg_env, arg);
6077 register_name = "MVPControl";
6078 break;
6079 case CP0_REG00__MVPCONF0:
6080 CP0_CHECK(ctx->insn_flags & ASE_MT);
6081 /* ignored */
6082 register_name = "MVPConf0";
6083 break;
6084 case CP0_REG00__MVPCONF1:
6085 CP0_CHECK(ctx->insn_flags & ASE_MT);
6086 /* ignored */
6087 register_name = "MVPConf1";
6088 break;
6089 case CP0_REG00__VPCONTROL:
6090 CP0_CHECK(ctx->vp);
6091 /* ignored */
6092 register_name = "VPControl";
6093 break;
6094 default:
6095 goto cp0_unimplemented;
6096 }
6097 break;
6098 case CP0_REGISTER_01:
6099 switch (sel) {
6100 case CP0_REG01__RANDOM:
6101 /* ignored */
6102 register_name = "Random";
6103 break;
6104 case CP0_REG01__VPECONTROL:
6105 CP0_CHECK(ctx->insn_flags & ASE_MT);
6106 gen_helper_mtc0_vpecontrol(tcg_env, arg);
6107 register_name = "VPEControl";
6108 break;
6109 case CP0_REG01__VPECONF0:
6110 CP0_CHECK(ctx->insn_flags & ASE_MT);
6111 gen_helper_mtc0_vpeconf0(tcg_env, arg);
6112 register_name = "VPEConf0";
6113 break;
6114 case CP0_REG01__VPECONF1:
6115 CP0_CHECK(ctx->insn_flags & ASE_MT);
6116 gen_helper_mtc0_vpeconf1(tcg_env, arg);
6117 register_name = "VPEConf1";
6118 break;
6119 case CP0_REG01__YQMASK:
6120 CP0_CHECK(ctx->insn_flags & ASE_MT);
6121 gen_helper_mtc0_yqmask(tcg_env, arg);
6122 register_name = "YQMask";
6123 break;
6124 case CP0_REG01__VPESCHEDULE:
6125 CP0_CHECK(ctx->insn_flags & ASE_MT);
6126 tcg_gen_st_tl(arg, tcg_env,
6127 offsetof(CPUMIPSState, CP0_VPESchedule));
6128 register_name = "VPESchedule";
6129 break;
6130 case CP0_REG01__VPESCHEFBACK:
6131 CP0_CHECK(ctx->insn_flags & ASE_MT);
6132 tcg_gen_st_tl(arg, tcg_env,
6133 offsetof(CPUMIPSState, CP0_VPEScheFBack));
6134 register_name = "VPEScheFBack";
6135 break;
6136 case CP0_REG01__VPEOPT:
6137 CP0_CHECK(ctx->insn_flags & ASE_MT);
6138 gen_helper_mtc0_vpeopt(tcg_env, arg);
6139 register_name = "VPEOpt";
6140 break;
6141 default:
6142 goto cp0_unimplemented;
6143 }
6144 break;
6145 case CP0_REGISTER_02:
6146 switch (sel) {
6147 case CP0_REG02__ENTRYLO0:
6148 gen_helper_mtc0_entrylo0(tcg_env, arg);
6149 register_name = "EntryLo0";
6150 break;
6151 case CP0_REG02__TCSTATUS:
6152 CP0_CHECK(ctx->insn_flags & ASE_MT);
6153 gen_helper_mtc0_tcstatus(tcg_env, arg);
6154 register_name = "TCStatus";
6155 break;
6156 case CP0_REG02__TCBIND:
6157 CP0_CHECK(ctx->insn_flags & ASE_MT);
6158 gen_helper_mtc0_tcbind(tcg_env, arg);
6159 register_name = "TCBind";
6160 break;
6161 case CP0_REG02__TCRESTART:
6162 CP0_CHECK(ctx->insn_flags & ASE_MT);
6163 gen_helper_mtc0_tcrestart(tcg_env, arg);
6164 register_name = "TCRestart";
6165 break;
6166 case CP0_REG02__TCHALT:
6167 CP0_CHECK(ctx->insn_flags & ASE_MT);
6168 gen_helper_mtc0_tchalt(tcg_env, arg);
6169 register_name = "TCHalt";
6170 break;
6171 case CP0_REG02__TCCONTEXT:
6172 CP0_CHECK(ctx->insn_flags & ASE_MT);
6173 gen_helper_mtc0_tccontext(tcg_env, arg);
6174 register_name = "TCContext";
6175 break;
6176 case CP0_REG02__TCSCHEDULE:
6177 CP0_CHECK(ctx->insn_flags & ASE_MT);
6178 gen_helper_mtc0_tcschedule(tcg_env, arg);
6179 register_name = "TCSchedule";
6180 break;
6181 case CP0_REG02__TCSCHEFBACK:
6182 CP0_CHECK(ctx->insn_flags & ASE_MT);
6183 gen_helper_mtc0_tcschefback(tcg_env, arg);
6184 register_name = "TCScheFBack";
6185 break;
6186 default:
6187 goto cp0_unimplemented;
6188 }
6189 break;
6190 case CP0_REGISTER_03:
6191 switch (sel) {
6192 case CP0_REG03__ENTRYLO1:
6193 gen_helper_mtc0_entrylo1(tcg_env, arg);
6194 register_name = "EntryLo1";
6195 break;
6196 case CP0_REG03__GLOBALNUM:
6197 CP0_CHECK(ctx->vp);
6198 /* ignored */
6199 register_name = "GlobalNumber";
6200 break;
6201 default:
6202 goto cp0_unimplemented;
6203 }
6204 break;
6205 case CP0_REGISTER_04:
6206 switch (sel) {
6207 case CP0_REG04__CONTEXT:
6208 gen_helper_mtc0_context(tcg_env, arg);
6209 register_name = "Context";
6210 break;
6211 case CP0_REG04__CONTEXTCONFIG:
6212 /* SmartMIPS ASE */
6213 /* gen_helper_mtc0_contextconfig(arg); */
6214 register_name = "ContextConfig";
6215 goto cp0_unimplemented;
6216 case CP0_REG04__USERLOCAL:
6217 CP0_CHECK(ctx->ulri);
6218 tcg_gen_st_tl(arg, tcg_env,
6219 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6220 register_name = "UserLocal";
6221 break;
6222 case CP0_REG04__MMID:
6223 CP0_CHECK(ctx->mi);
6224 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
6225 register_name = "MMID";
6226 break;
6227 default:
6228 goto cp0_unimplemented;
6229 }
6230 break;
6231 case CP0_REGISTER_05:
6232 switch (sel) {
6233 case CP0_REG05__PAGEMASK:
6234 gen_helper_mtc0_pagemask(tcg_env, arg);
6235 register_name = "PageMask";
6236 break;
6237 case CP0_REG05__PAGEGRAIN:
6238 check_insn(ctx, ISA_MIPS_R2);
6239 gen_helper_mtc0_pagegrain(tcg_env, arg);
6240 register_name = "PageGrain";
6241 ctx->base.is_jmp = DISAS_STOP;
6242 break;
6243 case CP0_REG05__SEGCTL0:
6244 CP0_CHECK(ctx->sc);
6245 gen_helper_mtc0_segctl0(tcg_env, arg);
6246 register_name = "SegCtl0";
6247 break;
6248 case CP0_REG05__SEGCTL1:
6249 CP0_CHECK(ctx->sc);
6250 gen_helper_mtc0_segctl1(tcg_env, arg);
6251 register_name = "SegCtl1";
6252 break;
6253 case CP0_REG05__SEGCTL2:
6254 CP0_CHECK(ctx->sc);
6255 gen_helper_mtc0_segctl2(tcg_env, arg);
6256 register_name = "SegCtl2";
6257 break;
6258 case CP0_REG05__PWBASE:
6259 check_pw(ctx);
6260 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
6261 register_name = "PWBase";
6262 break;
6263 case CP0_REG05__PWFIELD:
6264 check_pw(ctx);
6265 gen_helper_mtc0_pwfield(tcg_env, arg);
6266 register_name = "PWField";
6267 break;
6268 case CP0_REG05__PWSIZE:
6269 check_pw(ctx);
6270 gen_helper_mtc0_pwsize(tcg_env, arg);
6271 register_name = "PWSize";
6272 break;
6273 default:
6274 goto cp0_unimplemented;
6275 }
6276 break;
6277 case CP0_REGISTER_06:
6278 switch (sel) {
6279 case CP0_REG06__WIRED:
6280 gen_helper_mtc0_wired(tcg_env, arg);
6281 register_name = "Wired";
6282 break;
6283 case CP0_REG06__SRSCONF0:
6284 check_insn(ctx, ISA_MIPS_R2);
6285 gen_helper_mtc0_srsconf0(tcg_env, arg);
6286 register_name = "SRSConf0";
6287 break;
6288 case CP0_REG06__SRSCONF1:
6289 check_insn(ctx, ISA_MIPS_R2);
6290 gen_helper_mtc0_srsconf1(tcg_env, arg);
6291 register_name = "SRSConf1";
6292 break;
6293 case CP0_REG06__SRSCONF2:
6294 check_insn(ctx, ISA_MIPS_R2);
6295 gen_helper_mtc0_srsconf2(tcg_env, arg);
6296 register_name = "SRSConf2";
6297 break;
6298 case CP0_REG06__SRSCONF3:
6299 check_insn(ctx, ISA_MIPS_R2);
6300 gen_helper_mtc0_srsconf3(tcg_env, arg);
6301 register_name = "SRSConf3";
6302 break;
6303 case CP0_REG06__SRSCONF4:
6304 check_insn(ctx, ISA_MIPS_R2);
6305 gen_helper_mtc0_srsconf4(tcg_env, arg);
6306 register_name = "SRSConf4";
6307 break;
6308 case CP0_REG06__PWCTL:
6309 check_pw(ctx);
6310 gen_helper_mtc0_pwctl(tcg_env, arg);
6311 register_name = "PWCtl";
6312 break;
6313 default:
6314 goto cp0_unimplemented;
6315 }
6316 break;
6317 case CP0_REGISTER_07:
6318 switch (sel) {
6319 case CP0_REG07__HWRENA:
6320 check_insn(ctx, ISA_MIPS_R2);
6321 gen_helper_mtc0_hwrena(tcg_env, arg);
6322 ctx->base.is_jmp = DISAS_STOP;
6323 register_name = "HWREna";
6324 break;
6325 default:
6326 goto cp0_unimplemented;
6327 }
6328 break;
6329 case CP0_REGISTER_08:
6330 switch (sel) {
6331 case CP0_REG08__BADVADDR:
6332 /* ignored */
6333 register_name = "BadVAddr";
6334 break;
6335 case CP0_REG08__BADINSTR:
6336 /* ignored */
6337 register_name = "BadInstr";
6338 break;
6339 case CP0_REG08__BADINSTRP:
6340 /* ignored */
6341 register_name = "BadInstrP";
6342 break;
6343 case CP0_REG08__BADINSTRX:
6344 /* ignored */
6345 register_name = "BadInstrX";
6346 break;
6347 default:
6348 goto cp0_unimplemented;
6349 }
6350 break;
6351 case CP0_REGISTER_09:
6352 switch (sel) {
6353 case CP0_REG09__COUNT:
6354 gen_helper_mtc0_count(tcg_env, arg);
6355 register_name = "Count";
6356 break;
6357 default:
6358 goto cp0_unimplemented;
6359 }
6360 break;
6361 case CP0_REGISTER_10:
6362 switch (sel) {
6363 case CP0_REG10__ENTRYHI:
6364 gen_helper_mtc0_entryhi(tcg_env, arg);
6365 register_name = "EntryHi";
6366 break;
6367 default:
6368 goto cp0_unimplemented;
6369 }
6370 break;
6371 case CP0_REGISTER_11:
6372 switch (sel) {
6373 case CP0_REG11__COMPARE:
6374 gen_helper_mtc0_compare(tcg_env, arg);
6375 register_name = "Compare";
6376 break;
6377 /* 6,7 are implementation dependent */
6378 default:
6379 goto cp0_unimplemented;
6380 }
6381 break;
6382 case CP0_REGISTER_12:
6383 switch (sel) {
6384 case CP0_REG12__STATUS:
6385 save_cpu_state(ctx, 1);
6386 gen_helper_mtc0_status(tcg_env, arg);
6387 /* DISAS_STOP isn't good enough here, hflags may have changed. */
6388 gen_save_pc(ctx->base.pc_next + 4);
6389 ctx->base.is_jmp = DISAS_EXIT;
6390 register_name = "Status";
6391 break;
6392 case CP0_REG12__INTCTL:
6393 check_insn(ctx, ISA_MIPS_R2);
6394 gen_helper_mtc0_intctl(tcg_env, arg);
6395 /* Stop translation as we may have switched the execution mode */
6396 ctx->base.is_jmp = DISAS_STOP;
6397 register_name = "IntCtl";
6398 break;
6399 case CP0_REG12__SRSCTL:
6400 check_insn(ctx, ISA_MIPS_R2);
6401 gen_helper_mtc0_srsctl(tcg_env, arg);
6402 /* Stop translation as we may have switched the execution mode */
6403 ctx->base.is_jmp = DISAS_STOP;
6404 register_name = "SRSCtl";
6405 break;
6406 case CP0_REG12__SRSMAP:
6407 check_insn(ctx, ISA_MIPS_R2);
6408 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
6409 /* Stop translation as we may have switched the execution mode */
6410 ctx->base.is_jmp = DISAS_STOP;
6411 register_name = "SRSMap";
6412 break;
6413 default:
6414 goto cp0_unimplemented;
6415 }
6416 break;
6417 case CP0_REGISTER_13:
6418 switch (sel) {
6419 case CP0_REG13__CAUSE:
6420 save_cpu_state(ctx, 1);
6421 gen_helper_mtc0_cause(tcg_env, arg);
6422 /*
6423 * Stop translation as we may have triggered an interrupt.
6424 * DISAS_STOP isn't sufficient, we need to ensure we break out of
6425 * translated code to check for pending interrupts.
6426 */
6427 gen_save_pc(ctx->base.pc_next + 4);
6428 ctx->base.is_jmp = DISAS_EXIT;
6429 register_name = "Cause";
6430 break;
6431 default:
6432 goto cp0_unimplemented;
6433 }
6434 break;
6435 case CP0_REGISTER_14:
6436 switch (sel) {
6437 case CP0_REG14__EPC:
6438 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
6439 register_name = "EPC";
6440 break;
6441 default:
6442 goto cp0_unimplemented;
6443 }
6444 break;
6445 case CP0_REGISTER_15:
6446 switch (sel) {
6447 case CP0_REG15__PRID:
6448 /* ignored */
6449 register_name = "PRid";
6450 break;
6451 case CP0_REG15__EBASE:
6452 check_insn(ctx, ISA_MIPS_R2);
6453 gen_helper_mtc0_ebase(tcg_env, arg);
6454 register_name = "EBase";
6455 break;
6456 default:
6457 goto cp0_unimplemented;
6458 }
6459 break;
6460 case CP0_REGISTER_16:
6461 switch (sel) {
6462 case CP0_REG16__CONFIG:
6463 gen_helper_mtc0_config0(tcg_env, arg);
6464 register_name = "Config";
6465 /* Stop translation as we may have switched the execution mode */
6466 ctx->base.is_jmp = DISAS_STOP;
6467 break;
6468 case CP0_REG16__CONFIG1:
6469 /* ignored, read only */
6470 register_name = "Config1";
6471 break;
6472 case CP0_REG16__CONFIG2:
6473 gen_helper_mtc0_config2(tcg_env, arg);
6474 register_name = "Config2";
6475 /* Stop translation as we may have switched the execution mode */
6476 ctx->base.is_jmp = DISAS_STOP;
6477 break;
6478 case CP0_REG16__CONFIG3:
6479 gen_helper_mtc0_config3(tcg_env, arg);
6480 register_name = "Config3";
6481 /* Stop translation as we may have switched the execution mode */
6482 ctx->base.is_jmp = DISAS_STOP;
6483 break;
6484 case CP0_REG16__CONFIG4:
6485 gen_helper_mtc0_config4(tcg_env, arg);
6486 register_name = "Config4";
6487 ctx->base.is_jmp = DISAS_STOP;
6488 break;
6489 case CP0_REG16__CONFIG5:
6490 gen_helper_mtc0_config5(tcg_env, arg);
6491 register_name = "Config5";
6492 /* Stop translation as we may have switched the execution mode */
6493 ctx->base.is_jmp = DISAS_STOP;
6494 break;
6495 /* 6,7 are implementation dependent */
6496 case CP0_REG16__CONFIG6:
6497 /* ignored */
6498 register_name = "Config6";
6499 break;
6500 case CP0_REG16__CONFIG7:
6501 /* ignored */
6502 register_name = "Config7";
6503 break;
6504 default:
6505 register_name = "Invalid config selector";
6506 goto cp0_unimplemented;
6507 }
6508 break;
6509 case CP0_REGISTER_17:
6510 switch (sel) {
6511 case CP0_REG17__LLADDR:
6512 gen_helper_mtc0_lladdr(tcg_env, arg);
6513 register_name = "LLAddr";
6514 break;
6515 case CP0_REG17__MAAR:
6516 CP0_CHECK(ctx->mrp);
6517 gen_helper_mtc0_maar(tcg_env, arg);
6518 register_name = "MAAR";
6519 break;
6520 case CP0_REG17__MAARI:
6521 CP0_CHECK(ctx->mrp);
6522 gen_helper_mtc0_maari(tcg_env, arg);
6523 register_name = "MAARI";
6524 break;
6525 default:
6526 goto cp0_unimplemented;
6527 }
6528 break;
6529 case CP0_REGISTER_18:
6530 switch (sel) {
6531 case CP0_REG18__WATCHLO0:
6532 case CP0_REG18__WATCHLO1:
6533 case CP0_REG18__WATCHLO2:
6534 case CP0_REG18__WATCHLO3:
6535 case CP0_REG18__WATCHLO4:
6536 case CP0_REG18__WATCHLO5:
6537 case CP0_REG18__WATCHLO6:
6538 case CP0_REG18__WATCHLO7:
6539 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6540 gen_helper_0e1i(mtc0_watchlo, arg, sel);
6541 register_name = "WatchLo";
6542 break;
6543 default:
6544 goto cp0_unimplemented;
6545 }
6546 break;
6547 case CP0_REGISTER_19:
6548 switch (sel) {
6549 case CP0_REG19__WATCHHI0:
6550 case CP0_REG19__WATCHHI1:
6551 case CP0_REG19__WATCHHI2:
6552 case CP0_REG19__WATCHHI3:
6553 case CP0_REG19__WATCHHI4:
6554 case CP0_REG19__WATCHHI5:
6555 case CP0_REG19__WATCHHI6:
6556 case CP0_REG19__WATCHHI7:
6557 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
6558 gen_helper_0e1i(mtc0_watchhi, arg, sel);
6559 register_name = "WatchHi";
6560 break;
6561 default:
6562 goto cp0_unimplemented;
6563 }
6564 break;
6565 case CP0_REGISTER_20:
6566 switch (sel) {
6567 case CP0_REG20__XCONTEXT:
6568 #if defined(TARGET_MIPS64)
6569 check_insn(ctx, ISA_MIPS3);
6570 gen_helper_mtc0_xcontext(tcg_env, arg);
6571 register_name = "XContext";
6572 break;
6573 #endif
6574 default:
6575 goto cp0_unimplemented;
6576 }
6577 break;
6578 case CP0_REGISTER_21:
6579 /* Officially reserved, but sel 0 is used for R1x000 framemask */
6580 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
6581 switch (sel) {
6582 case 0:
6583 gen_helper_mtc0_framemask(tcg_env, arg);
6584 register_name = "Framemask";
6585 break;
6586 default:
6587 goto cp0_unimplemented;
6588 }
6589 break;
6590 case CP0_REGISTER_22:
6591 /* ignored */
6592 register_name = "Diagnostic"; /* implementation dependent */
6593 break;
6594 case CP0_REGISTER_23:
6595 switch (sel) {
6596 case CP0_REG23__DEBUG:
6597 gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */
6598 /* DISAS_STOP isn't good enough here, hflags may have changed. */
6599 gen_save_pc(ctx->base.pc_next + 4);
6600 ctx->base.is_jmp = DISAS_EXIT;
6601 register_name = "Debug";
6602 break;
6603 case CP0_REG23__TRACECONTROL:
6604 /* PDtrace support */
6605 /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */
6606 register_name = "TraceControl";
6607 /* Stop translation as we may have switched the execution mode */
6608 ctx->base.is_jmp = DISAS_STOP;
6609 goto cp0_unimplemented;
6610 case CP0_REG23__TRACECONTROL2:
6611 /* PDtrace support */
6612 /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */
6613 register_name = "TraceControl2";
6614 /* Stop translation as we may have switched the execution mode */
6615 ctx->base.is_jmp = DISAS_STOP;
6616 goto cp0_unimplemented;
6617 case CP0_REG23__USERTRACEDATA1:
6618 /* Stop translation as we may have switched the execution mode */
6619 ctx->base.is_jmp = DISAS_STOP;
6620 /* PDtrace support */
6621 /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/
6622 register_name = "UserTraceData";
6623 /* Stop translation as we may have switched the execution mode */
6624 ctx->base.is_jmp = DISAS_STOP;
6625 goto cp0_unimplemented;
6626 case CP0_REG23__TRACEIBPC:
6627 /* PDtrace support */
6628 /* gen_helper_mtc0_traceibpc(tcg_env, arg); */
6629 /* Stop translation as we may have switched the execution mode */
6630 ctx->base.is_jmp = DISAS_STOP;
6631 register_name = "TraceIBPC";
6632 goto cp0_unimplemented;
6633 case CP0_REG23__TRACEDBPC:
6634 /* PDtrace support */
6635 /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */
6636 /* Stop translation as we may have switched the execution mode */
6637 ctx->base.is_jmp = DISAS_STOP;
6638 register_name = "TraceDBPC";
6639 goto cp0_unimplemented;
6640 default:
6641 goto cp0_unimplemented;
6642 }
6643 break;
6644 case CP0_REGISTER_24:
6645 switch (sel) {
6646 case CP0_REG24__DEPC:
6647 /* EJTAG support */
6648 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
6649 register_name = "DEPC";
6650 break;
6651 default:
6652 goto cp0_unimplemented;
6653 }
6654 break;
6655 case CP0_REGISTER_25:
6656 switch (sel) {
6657 case CP0_REG25__PERFCTL0:
6658 gen_helper_mtc0_performance0(tcg_env, arg);
6659 register_name = "Performance0";
6660 break;
6661 case CP0_REG25__PERFCNT0:
6662 /* gen_helper_mtc0_performance1(arg); */
6663 register_name = "Performance1";
6664 goto cp0_unimplemented;
6665 case CP0_REG25__PERFCTL1:
6666 /* gen_helper_mtc0_performance2(arg); */
6667 register_name = "Performance2";
6668 goto cp0_unimplemented;
6669 case CP0_REG25__PERFCNT1:
6670 /* gen_helper_mtc0_performance3(arg); */
6671 register_name = "Performance3";
6672 goto cp0_unimplemented;
6673 case CP0_REG25__PERFCTL2:
6674 /* gen_helper_mtc0_performance4(arg); */
6675 register_name = "Performance4";
6676 goto cp0_unimplemented;
6677 case CP0_REG25__PERFCNT2:
6678 /* gen_helper_mtc0_performance5(arg); */
6679 register_name = "Performance5";
6680 goto cp0_unimplemented;
6681 case CP0_REG25__PERFCTL3:
6682 /* gen_helper_mtc0_performance6(arg); */
6683 register_name = "Performance6";
6684 goto cp0_unimplemented;
6685 case CP0_REG25__PERFCNT3:
6686 /* gen_helper_mtc0_performance7(arg); */
6687 register_name = "Performance7";
6688 goto cp0_unimplemented;
6689 default:
6690 goto cp0_unimplemented;
6691 }
6692 break;
6693 case CP0_REGISTER_26:
6694 switch (sel) {
6695 case CP0_REG26__ERRCTL:
6696 gen_helper_mtc0_errctl(tcg_env, arg);
6697 ctx->base.is_jmp = DISAS_STOP;
6698 register_name = "ErrCtl";
6699 break;
6700 default:
6701 goto cp0_unimplemented;
6702 }
6703 break;
6704 case CP0_REGISTER_27:
6705 switch (sel) {
6706 case CP0_REG27__CACHERR:
6707 /* ignored */
6708 register_name = "CacheErr";
6709 break;
6710 default:
6711 goto cp0_unimplemented;
6712 }
6713 break;
6714 case CP0_REGISTER_28:
6715 switch (sel) {
6716 case CP0_REG28__TAGLO:
6717 case CP0_REG28__TAGLO1:
6718 case CP0_REG28__TAGLO2:
6719 case CP0_REG28__TAGLO3:
6720 gen_helper_mtc0_taglo(tcg_env, arg);
6721 register_name = "TagLo";
6722 break;
6723 case CP0_REG28__DATALO:
6724 case CP0_REG28__DATALO1:
6725 case CP0_REG28__DATALO2:
6726 case CP0_REG28__DATALO3:
6727 gen_helper_mtc0_datalo(tcg_env, arg);
6728 register_name = "DataLo";
6729 break;
6730 default:
6731 goto cp0_unimplemented;
6732 }
6733 break;
6734 case CP0_REGISTER_29:
6735 switch (sel) {
6736 case CP0_REG29__TAGHI:
6737 case CP0_REG29__TAGHI1:
6738 case CP0_REG29__TAGHI2:
6739 case CP0_REG29__TAGHI3:
6740 gen_helper_mtc0_taghi(tcg_env, arg);
6741 register_name = "TagHi";
6742 break;
6743 case CP0_REG29__DATAHI:
6744 case CP0_REG29__DATAHI1:
6745 case CP0_REG29__DATAHI2:
6746 case CP0_REG29__DATAHI3:
6747 gen_helper_mtc0_datahi(tcg_env, arg);
6748 register_name = "DataHi";
6749 break;
6750 default:
6751 register_name = "invalid sel";
6752 goto cp0_unimplemented;
6753 }
6754 break;
6755 case CP0_REGISTER_30:
6756 switch (sel) {
6757 case CP0_REG30__ERROREPC:
6758 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
6759 register_name = "ErrorEPC";
6760 break;
6761 default:
6762 goto cp0_unimplemented;
6763 }
6764 break;
6765 case CP0_REGISTER_31:
6766 switch (sel) {
6767 case CP0_REG31__DESAVE:
6768 /* EJTAG support */
6769 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
6770 register_name = "DESAVE";
6771 break;
6772 case CP0_REG31__KSCRATCH1:
6773 case CP0_REG31__KSCRATCH2:
6774 case CP0_REG31__KSCRATCH3:
6775 case CP0_REG31__KSCRATCH4:
6776 case CP0_REG31__KSCRATCH5:
6777 case CP0_REG31__KSCRATCH6:
6778 CP0_CHECK(ctx->kscrexist & (1 << sel));
6779 tcg_gen_st_tl(arg, tcg_env,
6780 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
6781 register_name = "KScratch";
6782 break;
6783 default:
6784 goto cp0_unimplemented;
6785 }
6786 break;
6787 default:
6788 goto cp0_unimplemented;
6789 }
6790 trace_mips_translate_c0("mtc0", register_name, reg, sel);
6791
6792 /* For simplicity assume that all writes can cause interrupts. */
6793 if (icount) {
6794 /*
6795 * DISAS_STOP isn't sufficient, we need to ensure we break out of
6796 * translated code to check for pending interrupts.
6797 */
6798 gen_save_pc(ctx->base.pc_next + 4);
6799 ctx->base.is_jmp = DISAS_EXIT;
6800 }
6801 return;
6802
6803 cp0_unimplemented:
6804 qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n",
6805 register_name, reg, sel);
6806 }
6807
6808 #if defined(TARGET_MIPS64)
6809 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
6810 {
6811 const char *register_name = "invalid";
6812
6813 if (sel != 0) {
6814 check_insn(ctx, ISA_MIPS_R1);
6815 }
6816
6817 switch (reg) {
6818 case CP0_REGISTER_00:
6819 switch (sel) {
6820 case CP0_REG00__INDEX:
6821 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
6822 register_name = "Index";
6823 break;
6824 case CP0_REG00__MVPCONTROL:
6825 CP0_CHECK(ctx->insn_flags & ASE_MT);
6826 gen_helper_mfc0_mvpcontrol(arg, tcg_env);
6827 register_name = "MVPControl";
6828 break;
6829 case CP0_REG00__MVPCONF0:
6830 CP0_CHECK(ctx->insn_flags & ASE_MT);
6831 gen_helper_mfc0_mvpconf0(arg, tcg_env);
6832 register_name = "MVPConf0";
6833 break;
6834 case CP0_REG00__MVPCONF1:
6835 CP0_CHECK(ctx->insn_flags & ASE_MT);
6836 gen_helper_mfc0_mvpconf1(arg, tcg_env);
6837 register_name = "MVPConf1";
6838 break;
6839 case CP0_REG00__VPCONTROL:
6840 CP0_CHECK(ctx->vp);
6841 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
6842 register_name = "VPControl";
6843 break;
6844 default:
6845 goto cp0_unimplemented;
6846 }
6847 break;
6848 case CP0_REGISTER_01:
6849 switch (sel) {
6850 case CP0_REG01__RANDOM:
6851 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
6852 gen_helper_mfc0_random(arg, tcg_env);
6853 register_name = "Random";
6854 break;
6855 case CP0_REG01__VPECONTROL:
6856 CP0_CHECK(ctx->insn_flags & ASE_MT);
6857 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
6858 register_name = "VPEControl";
6859 break;
6860 case CP0_REG01__VPECONF0:
6861 CP0_CHECK(ctx->insn_flags & ASE_MT);
6862 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
6863 register_name = "VPEConf0";
6864 break;
6865 case CP0_REG01__VPECONF1:
6866 CP0_CHECK(ctx->insn_flags & ASE_MT);
6867 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
6868 register_name = "VPEConf1";
6869 break;
6870 case CP0_REG01__YQMASK:
6871 CP0_CHECK(ctx->insn_flags & ASE_MT);
6872 tcg_gen_ld_tl(arg, tcg_env,
6873 offsetof(CPUMIPSState, CP0_YQMask));
6874 register_name = "YQMask";
6875 break;
6876 case CP0_REG01__VPESCHEDULE:
6877 CP0_CHECK(ctx->insn_flags & ASE_MT);
6878 tcg_gen_ld_tl(arg, tcg_env,
6879 offsetof(CPUMIPSState, CP0_VPESchedule));
6880 register_name = "VPESchedule";
6881 break;
6882 case CP0_REG01__VPESCHEFBACK:
6883 CP0_CHECK(ctx->insn_flags & ASE_MT);
6884 tcg_gen_ld_tl(arg, tcg_env,
6885 offsetof(CPUMIPSState, CP0_VPEScheFBack));
6886 register_name = "VPEScheFBack";
6887 break;
6888 case CP0_REG01__VPEOPT:
6889 CP0_CHECK(ctx->insn_flags & ASE_MT);
6890 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
6891 register_name = "VPEOpt";
6892 break;
6893 default:
6894 goto cp0_unimplemented;
6895 }
6896 break;
6897 case CP0_REGISTER_02:
6898 switch (sel) {
6899 case CP0_REG02__ENTRYLO0:
6900 tcg_gen_ld_tl(arg, tcg_env,
6901 offsetof(CPUMIPSState, CP0_EntryLo0));
6902 register_name = "EntryLo0";
6903 break;
6904 case CP0_REG02__TCSTATUS:
6905 CP0_CHECK(ctx->insn_flags & ASE_MT);
6906 gen_helper_mfc0_tcstatus(arg, tcg_env);
6907 register_name = "TCStatus";
6908 break;
6909 case CP0_REG02__TCBIND:
6910 CP0_CHECK(ctx->insn_flags & ASE_MT);
6911 gen_helper_mfc0_tcbind(arg, tcg_env);
6912 register_name = "TCBind";
6913 break;
6914 case CP0_REG02__TCRESTART:
6915 CP0_CHECK(ctx->insn_flags & ASE_MT);
6916 gen_helper_dmfc0_tcrestart(arg, tcg_env);
6917 register_name = "TCRestart";
6918 break;
6919 case CP0_REG02__TCHALT:
6920 CP0_CHECK(ctx->insn_flags & ASE_MT);
6921 gen_helper_dmfc0_tchalt(arg, tcg_env);
6922 register_name = "TCHalt";
6923 break;
6924 case CP0_REG02__TCCONTEXT:
6925 CP0_CHECK(ctx->insn_flags & ASE_MT);
6926 gen_helper_dmfc0_tccontext(arg, tcg_env);
6927 register_name = "TCContext";
6928 break;
6929 case CP0_REG02__TCSCHEDULE:
6930 CP0_CHECK(ctx->insn_flags & ASE_MT);
6931 gen_helper_dmfc0_tcschedule(arg, tcg_env);
6932 register_name = "TCSchedule";
6933 break;
6934 case CP0_REG02__TCSCHEFBACK:
6935 CP0_CHECK(ctx->insn_flags & ASE_MT);
6936 gen_helper_dmfc0_tcschefback(arg, tcg_env);
6937 register_name = "TCScheFBack";
6938 break;
6939 default:
6940 goto cp0_unimplemented;
6941 }
6942 break;
6943 case CP0_REGISTER_03:
6944 switch (sel) {
6945 case CP0_REG03__ENTRYLO1:
6946 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo1));
6947 register_name = "EntryLo1";
6948 break;
6949 case CP0_REG03__GLOBALNUM:
6950 CP0_CHECK(ctx->vp);
6951 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
6952 register_name = "GlobalNumber";
6953 break;
6954 default:
6955 goto cp0_unimplemented;
6956 }
6957 break;
6958 case CP0_REGISTER_04:
6959 switch (sel) {
6960 case CP0_REG04__CONTEXT:
6961 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context));
6962 register_name = "Context";
6963 break;
6964 case CP0_REG04__CONTEXTCONFIG:
6965 /* SmartMIPS ASE */
6966 /* gen_helper_dmfc0_contextconfig(arg); */
6967 register_name = "ContextConfig";
6968 goto cp0_unimplemented;
6969 case CP0_REG04__USERLOCAL:
6970 CP0_CHECK(ctx->ulri);
6971 tcg_gen_ld_tl(arg, tcg_env,
6972 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
6973 register_name = "UserLocal";
6974 break;
6975 case CP0_REG04__MMID:
6976 CP0_CHECK(ctx->mi);
6977 gen_helper_mtc0_memorymapid(tcg_env, arg);
6978 register_name = "MMID";
6979 break;
6980 default:
6981 goto cp0_unimplemented;
6982 }
6983 break;
6984 case CP0_REGISTER_05:
6985 switch (sel) {
6986 case CP0_REG05__PAGEMASK:
6987 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
6988 register_name = "PageMask";
6989 break;
6990 case CP0_REG05__PAGEGRAIN:
6991 check_insn(ctx, ISA_MIPS_R2);
6992 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
6993 register_name = "PageGrain";
6994 break;
6995 case CP0_REG05__SEGCTL0:
6996 CP0_CHECK(ctx->sc);
6997 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0));
6998 register_name = "SegCtl0";
6999 break;
7000 case CP0_REG05__SEGCTL1:
7001 CP0_CHECK(ctx->sc);
7002 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1));
7003 register_name = "SegCtl1";
7004 break;
7005 case CP0_REG05__SEGCTL2:
7006 CP0_CHECK(ctx->sc);
7007 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2));
7008 register_name = "SegCtl2";
7009 break;
7010 case CP0_REG05__PWBASE:
7011 check_pw(ctx);
7012 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase));
7013 register_name = "PWBase";
7014 break;
7015 case CP0_REG05__PWFIELD:
7016 check_pw(ctx);
7017 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWField));
7018 register_name = "PWField";
7019 break;
7020 case CP0_REG05__PWSIZE:
7021 check_pw(ctx);
7022 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWSize));
7023 register_name = "PWSize";
7024 break;
7025 default:
7026 goto cp0_unimplemented;
7027 }
7028 break;
7029 case CP0_REGISTER_06:
7030 switch (sel) {
7031 case CP0_REG06__WIRED:
7032 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
7033 register_name = "Wired";
7034 break;
7035 case CP0_REG06__SRSCONF0:
7036 check_insn(ctx, ISA_MIPS_R2);
7037 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
7038 register_name = "SRSConf0";
7039 break;
7040 case CP0_REG06__SRSCONF1:
7041 check_insn(ctx, ISA_MIPS_R2);
7042 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
7043 register_name = "SRSConf1";
7044 break;
7045 case CP0_REG06__SRSCONF2:
7046 check_insn(ctx, ISA_MIPS_R2);
7047 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
7048 register_name = "SRSConf2";
7049 break;
7050 case CP0_REG06__SRSCONF3:
7051 check_insn(ctx, ISA_MIPS_R2);
7052 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
7053 register_name = "SRSConf3";
7054 break;
7055 case CP0_REG06__SRSCONF4:
7056 check_insn(ctx, ISA_MIPS_R2);
7057 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
7058 register_name = "SRSConf4";
7059 break;
7060 case CP0_REG06__PWCTL:
7061 check_pw(ctx);
7062 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
7063 register_name = "PWCtl";
7064 break;
7065 default:
7066 goto cp0_unimplemented;
7067 }
7068 break;
7069 case CP0_REGISTER_07:
7070 switch (sel) {
7071 case CP0_REG07__HWRENA:
7072 check_insn(ctx, ISA_MIPS_R2);
7073 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
7074 register_name = "HWREna";
7075 break;
7076 default:
7077 goto cp0_unimplemented;
7078 }
7079 break;
7080 case CP0_REGISTER_08:
7081 switch (sel) {
7082 case CP0_REG08__BADVADDR:
7083 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr));
7084 register_name = "BadVAddr";
7085 break;
7086 case CP0_REG08__BADINSTR:
7087 CP0_CHECK(ctx->bi);
7088 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
7089 register_name = "BadInstr";
7090 break;
7091 case CP0_REG08__BADINSTRP:
7092 CP0_CHECK(ctx->bp);
7093 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
7094 register_name = "BadInstrP";
7095 break;
7096 case CP0_REG08__BADINSTRX:
7097 CP0_CHECK(ctx->bi);
7098 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
7099 tcg_gen_andi_tl(arg, arg, ~0xffff);
7100 register_name = "BadInstrX";
7101 break;
7102 default:
7103 goto cp0_unimplemented;
7104 }
7105 break;
7106 case CP0_REGISTER_09:
7107 switch (sel) {
7108 case CP0_REG09__COUNT:
7109 /* Mark as an IO operation because we read the time. */
7110 translator_io_start(&ctx->base);
7111 gen_helper_mfc0_count(arg, tcg_env);
7112 /*
7113 * Break the TB to be able to take timer interrupts immediately
7114 * after reading count. DISAS_STOP isn't sufficient, we need to
7115 * ensure we break completely out of translated code.
7116 */
7117 gen_save_pc(ctx->base.pc_next + 4);
7118 ctx->base.is_jmp = DISAS_EXIT;
7119 register_name = "Count";
7120 break;
7121 default:
7122 goto cp0_unimplemented;
7123 }
7124 break;
7125 case CP0_REGISTER_10:
7126 switch (sel) {
7127 case CP0_REG10__ENTRYHI:
7128 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi));
7129 register_name = "EntryHi";
7130 break;
7131 default:
7132 goto cp0_unimplemented;
7133 }
7134 break;
7135 case CP0_REGISTER_11:
7136 switch (sel) {
7137 case CP0_REG11__COMPARE:
7138 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
7139 register_name = "Compare";
7140 break;
7141 /* 6,7 are implementation dependent */
7142 default:
7143 goto cp0_unimplemented;
7144 }
7145 break;
7146 case CP0_REGISTER_12:
7147 switch (sel) {
7148 case CP0_REG12__STATUS:
7149 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
7150 register_name = "Status";
7151 break;
7152 case CP0_REG12__INTCTL:
7153 check_insn(ctx, ISA_MIPS_R2);
7154 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
7155 register_name = "IntCtl";
7156 break;
7157 case CP0_REG12__SRSCTL:
7158 check_insn(ctx, ISA_MIPS_R2);
7159 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
7160 register_name = "SRSCtl";
7161 break;
7162 case CP0_REG12__SRSMAP:
7163 check_insn(ctx, ISA_MIPS_R2);
7164 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7165 register_name = "SRSMap";
7166 break;
7167 default:
7168 goto cp0_unimplemented;
7169 }
7170 break;
7171 case CP0_REGISTER_13:
7172 switch (sel) {
7173 case CP0_REG13__CAUSE:
7174 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
7175 register_name = "Cause";
7176 break;
7177 default:
7178 goto cp0_unimplemented;
7179 }
7180 break;
7181 case CP0_REGISTER_14:
7182 switch (sel) {
7183 case CP0_REG14__EPC:
7184 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
7185 register_name = "EPC";
7186 break;
7187 default:
7188 goto cp0_unimplemented;
7189 }
7190 break;
7191 case CP0_REGISTER_15:
7192 switch (sel) {
7193 case CP0_REG15__PRID:
7194 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
7195 register_name = "PRid";
7196 break;
7197 case CP0_REG15__EBASE:
7198 check_insn(ctx, ISA_MIPS_R2);
7199 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase));
7200 register_name = "EBase";
7201 break;
7202 case CP0_REG15__CMGCRBASE:
7203 check_insn(ctx, ISA_MIPS_R2);
7204 CP0_CHECK(ctx->cmgcr);
7205 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
7206 register_name = "CMGCRBase";
7207 break;
7208 default:
7209 goto cp0_unimplemented;
7210 }
7211 break;
7212 case CP0_REGISTER_16:
7213 switch (sel) {
7214 case CP0_REG16__CONFIG:
7215 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
7216 register_name = "Config";
7217 break;
7218 case CP0_REG16__CONFIG1:
7219 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
7220 register_name = "Config1";
7221 break;
7222 case CP0_REG16__CONFIG2:
7223 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
7224 register_name = "Config2";
7225 break;
7226 case CP0_REG16__CONFIG3:
7227 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
7228 register_name = "Config3";
7229 break;
7230 case CP0_REG16__CONFIG4:
7231 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
7232 register_name = "Config4";
7233 break;
7234 case CP0_REG16__CONFIG5:
7235 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
7236 register_name = "Config5";
7237 break;
7238 /* 6,7 are implementation dependent */
7239 case CP0_REG16__CONFIG6:
7240 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
7241 register_name = "Config6";
7242 break;
7243 case CP0_REG16__CONFIG7:
7244 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
7245 register_name = "Config7";
7246 break;
7247 default:
7248 goto cp0_unimplemented;
7249 }
7250 break;
7251 case CP0_REGISTER_17:
7252 switch (sel) {
7253 case CP0_REG17__LLADDR:
7254 gen_helper_dmfc0_lladdr(arg, tcg_env);
7255 register_name = "LLAddr";
7256 break;
7257 case CP0_REG17__MAAR:
7258 CP0_CHECK(ctx->mrp);
7259 gen_helper_dmfc0_maar(arg, tcg_env);
7260 register_name = "MAAR";
7261 break;
7262 case CP0_REG17__MAARI:
7263 CP0_CHECK(ctx->mrp);
7264 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
7265 register_name = "MAARI";
7266 break;
7267 default:
7268 goto cp0_unimplemented;
7269 }
7270 break;
7271 case CP0_REGISTER_18:
7272 switch (sel) {
7273 case CP0_REG18__WATCHLO0:
7274 case CP0_REG18__WATCHLO1:
7275 case CP0_REG18__WATCHLO2:
7276 case CP0_REG18__WATCHLO3:
7277 case CP0_REG18__WATCHLO4:
7278 case CP0_REG18__WATCHLO5:
7279 case CP0_REG18__WATCHLO6:
7280 case CP0_REG18__WATCHLO7:
7281 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7282 gen_helper_1e0i(dmfc0_watchlo, arg, sel);
7283 register_name = "WatchLo";
7284 break;
7285 default:
7286 goto cp0_unimplemented;
7287 }
7288 break;
7289 case CP0_REGISTER_19:
7290 switch (sel) {
7291 case CP0_REG19__WATCHHI0:
7292 case CP0_REG19__WATCHHI1:
7293 case CP0_REG19__WATCHHI2:
7294 case CP0_REG19__WATCHHI3:
7295 case CP0_REG19__WATCHHI4:
7296 case CP0_REG19__WATCHHI5:
7297 case CP0_REG19__WATCHHI6:
7298 case CP0_REG19__WATCHHI7:
7299 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
7300 gen_helper_1e0i(dmfc0_watchhi, arg, sel);
7301 register_name = "WatchHi";
7302 break;
7303 default:
7304 goto cp0_unimplemented;
7305 }
7306 break;
7307 case CP0_REGISTER_20:
7308 switch (sel) {
7309 case CP0_REG20__XCONTEXT:
7310 check_insn(ctx, ISA_MIPS3);
7311 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContext));
7312 register_name = "XContext";
7313 break;
7314 default:
7315 goto cp0_unimplemented;
7316 }
7317 break;
7318 case CP0_REGISTER_21:
7319 /* Officially reserved, but sel 0 is used for R1x000 framemask */
7320 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
7321 switch (sel) {
7322 case 0:
7323 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Framemask));
7324 register_name = "Framemask";
7325 break;
7326 default:
7327 goto cp0_unimplemented;
7328 }
7329 break;
7330 case CP0_REGISTER_22:
7331 tcg_gen_movi_tl(arg, 0); /* unimplemented */
7332 register_name = "'Diagnostic"; /* implementation dependent */
7333 break;
7334 case CP0_REGISTER_23:
7335 switch (sel) {
7336 case CP0_REG23__DEBUG:
7337 gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */
7338 register_name = "Debug";
7339 break;
7340 case CP0_REG23__TRACECONTROL:
7341 /* PDtrace support */
7342 /* gen_helper_dmfc0_tracecontrol(arg, tcg_env); */
7343 register_name = "TraceControl";
7344 goto cp0_unimplemented;
7345 case CP0_REG23__TRACECONTROL2:
7346 /* PDtrace support */
7347 /* gen_helper_dmfc0_tracecontrol2(arg, tcg_env); */
7348 register_name = "TraceControl2";
7349 goto cp0_unimplemented;
7350 case CP0_REG23__USERTRACEDATA1:
7351 /* PDtrace support */
7352 /* gen_helper_dmfc0_usertracedata1(arg, tcg_env);*/
7353 register_name = "UserTraceData1";
7354 goto cp0_unimplemented;
7355 case CP0_REG23__TRACEIBPC:
7356 /* PDtrace support */
7357 /* gen_helper_dmfc0_traceibpc(arg, tcg_env); */
7358 register_name = "TraceIBPC";
7359 goto cp0_unimplemented;
7360 case CP0_REG23__TRACEDBPC:
7361 /* PDtrace support */
7362 /* gen_helper_dmfc0_tracedbpc(arg, tcg_env); */
7363 register_name = "TraceDBPC";
7364 goto cp0_unimplemented;
7365 default:
7366 goto cp0_unimplemented;
7367 }
7368 break;
7369 case CP0_REGISTER_24:
7370 switch (sel) {
7371 case CP0_REG24__DEPC:
7372 /* EJTAG support */
7373 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
7374 register_name = "DEPC";
7375 break;
7376 default:
7377 goto cp0_unimplemented;
7378 }
7379 break;
7380 case CP0_REGISTER_25:
7381 switch (sel) {
7382 case CP0_REG25__PERFCTL0:
7383 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
7384 register_name = "Performance0";
7385 break;
7386 case CP0_REG25__PERFCNT0:
7387 /* gen_helper_dmfc0_performance1(arg); */
7388 register_name = "Performance1";
7389 goto cp0_unimplemented;
7390 case CP0_REG25__PERFCTL1:
7391 /* gen_helper_dmfc0_performance2(arg); */
7392 register_name = "Performance2";
7393 goto cp0_unimplemented;
7394 case CP0_REG25__PERFCNT1:
7395 /* gen_helper_dmfc0_performance3(arg); */
7396 register_name = "Performance3";
7397 goto cp0_unimplemented;
7398 case CP0_REG25__PERFCTL2:
7399 /* gen_helper_dmfc0_performance4(arg); */
7400 register_name = "Performance4";
7401 goto cp0_unimplemented;
7402 case CP0_REG25__PERFCNT2:
7403 /* gen_helper_dmfc0_performance5(arg); */
7404 register_name = "Performance5";
7405 goto cp0_unimplemented;
7406 case CP0_REG25__PERFCTL3:
7407 /* gen_helper_dmfc0_performance6(arg); */
7408 register_name = "Performance6";
7409 goto cp0_unimplemented;
7410 case CP0_REG25__PERFCNT3:
7411 /* gen_helper_dmfc0_performance7(arg); */
7412 register_name = "Performance7";
7413 goto cp0_unimplemented;
7414 default:
7415 goto cp0_unimplemented;
7416 }
7417 break;
7418 case CP0_REGISTER_26:
7419 switch (sel) {
7420 case CP0_REG26__ERRCTL:
7421 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
7422 register_name = "ErrCtl";
7423 break;
7424 default:
7425 goto cp0_unimplemented;
7426 }
7427 break;
7428 case CP0_REGISTER_27:
7429 switch (sel) {
7430 /* ignored */
7431 case CP0_REG27__CACHERR:
7432 tcg_gen_movi_tl(arg, 0); /* unimplemented */
7433 register_name = "CacheErr";
7434 break;
7435 default:
7436 goto cp0_unimplemented;
7437 }
7438 break;
7439 case CP0_REGISTER_28:
7440 switch (sel) {
7441 case CP0_REG28__TAGLO:
7442 case CP0_REG28__TAGLO1:
7443 case CP0_REG28__TAGLO2:
7444 case CP0_REG28__TAGLO3:
7445 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
7446 register_name = "TagLo";
7447 break;
7448 case CP0_REG28__DATALO:
7449 case CP0_REG28__DATALO1:
7450 case CP0_REG28__DATALO2:
7451 case CP0_REG28__DATALO3:
7452 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
7453 register_name = "DataLo";
7454 break;
7455 default:
7456 goto cp0_unimplemented;
7457 }
7458 break;
7459 case CP0_REGISTER_29:
7460 switch (sel) {
7461 case CP0_REG29__TAGHI:
7462 case CP0_REG29__TAGHI1:
7463 case CP0_REG29__TAGHI2:
7464 case CP0_REG29__TAGHI3:
7465 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
7466 register_name = "TagHi";
7467 break;
7468 case CP0_REG29__DATAHI:
7469 case CP0_REG29__DATAHI1:
7470 case CP0_REG29__DATAHI2:
7471 case CP0_REG29__DATAHI3:
7472 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
7473 register_name = "DataHi";
7474 break;
7475 default:
7476 goto cp0_unimplemented;
7477 }
7478 break;
7479 case CP0_REGISTER_30:
7480 switch (sel) {
7481 case CP0_REG30__ERROREPC:
7482 tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
7483 register_name = "ErrorEPC";
7484 break;
7485 default:
7486 goto cp0_unimplemented;
7487 }
7488 break;
7489 case CP0_REGISTER_31:
7490 switch (sel) {
7491 case CP0_REG31__DESAVE:
7492 /* EJTAG support */
7493 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
7494 register_name = "DESAVE";
7495 break;
7496 case CP0_REG31__KSCRATCH1:
7497 case CP0_REG31__KSCRATCH2:
7498 case CP0_REG31__KSCRATCH3:
7499 case CP0_REG31__KSCRATCH4:
7500 case CP0_REG31__KSCRATCH5:
7501 case CP0_REG31__KSCRATCH6:
7502 CP0_CHECK(ctx->kscrexist & (1 << sel));
7503 tcg_gen_ld_tl(arg, tcg_env,
7504 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
7505 register_name = "KScratch";
7506 break;
7507 default:
7508 goto cp0_unimplemented;
7509 }
7510 break;
7511 default:
7512 goto cp0_unimplemented;
7513 }
7514 trace_mips_translate_c0("dmfc0", register_name, reg, sel);
7515 return;
7516
7517 cp0_unimplemented:
7518 qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n",
7519 register_name, reg, sel);
7520 gen_mfc0_unimplemented(ctx, arg);
7521 }
7522
7523 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
7524 {
7525 const char *register_name = "invalid";
7526 bool icount;
7527
7528 if (sel != 0) {
7529 check_insn(ctx, ISA_MIPS_R1);
7530 }
7531
7532 icount = translator_io_start(&ctx->base);
7533
7534 switch (reg) {
7535 case CP0_REGISTER_00:
7536 switch (sel) {
7537 case CP0_REG00__INDEX:
7538 gen_helper_mtc0_index(tcg_env, arg);
7539 register_name = "Index";
7540 break;
7541 case CP0_REG00__MVPCONTROL:
7542 CP0_CHECK(ctx->insn_flags & ASE_MT);
7543 gen_helper_mtc0_mvpcontrol(tcg_env, arg);
7544 register_name = "MVPControl";
7545 break;
7546 case CP0_REG00__MVPCONF0:
7547 CP0_CHECK(ctx->insn_flags & ASE_MT);
7548 /* ignored */
7549 register_name = "MVPConf0";
7550 break;
7551 case CP0_REG00__MVPCONF1:
7552 CP0_CHECK(ctx->insn_flags & ASE_MT);
7553 /* ignored */
7554 register_name = "MVPConf1";
7555 break;
7556 case CP0_REG00__VPCONTROL:
7557 CP0_CHECK(ctx->vp);
7558 /* ignored */
7559 register_name = "VPControl";
7560 break;
7561 default:
7562 goto cp0_unimplemented;
7563 }
7564 break;
7565 case CP0_REGISTER_01:
7566 switch (sel) {
7567 case CP0_REG01__RANDOM:
7568 /* ignored */
7569 register_name = "Random";
7570 break;
7571 case CP0_REG01__VPECONTROL:
7572 CP0_CHECK(ctx->insn_flags & ASE_MT);
7573 gen_helper_mtc0_vpecontrol(tcg_env, arg);
7574 register_name = "VPEControl";
7575 break;
7576 case CP0_REG01__VPECONF0:
7577 CP0_CHECK(ctx->insn_flags & ASE_MT);
7578 gen_helper_mtc0_vpeconf0(tcg_env, arg);
7579 register_name = "VPEConf0";
7580 break;
7581 case CP0_REG01__VPECONF1:
7582 CP0_CHECK(ctx->insn_flags & ASE_MT);
7583 gen_helper_mtc0_vpeconf1(tcg_env, arg);
7584 register_name = "VPEConf1";
7585 break;
7586 case CP0_REG01__YQMASK:
7587 CP0_CHECK(ctx->insn_flags & ASE_MT);
7588 gen_helper_mtc0_yqmask(tcg_env, arg);
7589 register_name = "YQMask";
7590 break;
7591 case CP0_REG01__VPESCHEDULE:
7592 CP0_CHECK(ctx->insn_flags & ASE_MT);
7593 tcg_gen_st_tl(arg, tcg_env,
7594 offsetof(CPUMIPSState, CP0_VPESchedule));
7595 register_name = "VPESchedule";
7596 break;
7597 case CP0_REG01__VPESCHEFBACK:
7598 CP0_CHECK(ctx->insn_flags & ASE_MT);
7599 tcg_gen_st_tl(arg, tcg_env,
7600 offsetof(CPUMIPSState, CP0_VPEScheFBack));
7601 register_name = "VPEScheFBack";
7602 break;
7603 case CP0_REG01__VPEOPT:
7604 CP0_CHECK(ctx->insn_flags & ASE_MT);
7605 gen_helper_mtc0_vpeopt(tcg_env, arg);
7606 register_name = "VPEOpt";
7607 break;
7608 default:
7609 goto cp0_unimplemented;
7610 }
7611 break;
7612 case CP0_REGISTER_02:
7613 switch (sel) {
7614 case CP0_REG02__ENTRYLO0:
7615 gen_helper_dmtc0_entrylo0(tcg_env, arg);
7616 register_name = "EntryLo0";
7617 break;
7618 case CP0_REG02__TCSTATUS:
7619 CP0_CHECK(ctx->insn_flags & ASE_MT);
7620 gen_helper_mtc0_tcstatus(tcg_env, arg);
7621 register_name = "TCStatus";
7622 break;
7623 case CP0_REG02__TCBIND:
7624 CP0_CHECK(ctx->insn_flags & ASE_MT);
7625 gen_helper_mtc0_tcbind(tcg_env, arg);
7626 register_name = "TCBind";
7627 break;
7628 case CP0_REG02__TCRESTART:
7629 CP0_CHECK(ctx->insn_flags & ASE_MT);
7630 gen_helper_mtc0_tcrestart(tcg_env, arg);
7631 register_name = "TCRestart";
7632 break;
7633 case CP0_REG02__TCHALT:
7634 CP0_CHECK(ctx->insn_flags & ASE_MT);
7635 gen_helper_mtc0_tchalt(tcg_env, arg);
7636 register_name = "TCHalt";
7637 break;
7638 case CP0_REG02__TCCONTEXT:
7639 CP0_CHECK(ctx->insn_flags & ASE_MT);
7640 gen_helper_mtc0_tccontext(tcg_env, arg);
7641 register_name = "TCContext";
7642 break;
7643 case CP0_REG02__TCSCHEDULE:
7644 CP0_CHECK(ctx->insn_flags & ASE_MT);
7645 gen_helper_mtc0_tcschedule(tcg_env, arg);
7646 register_name = "TCSchedule";
7647 break;
7648 case CP0_REG02__TCSCHEFBACK:
7649 CP0_CHECK(ctx->insn_flags & ASE_MT);
7650 gen_helper_mtc0_tcschefback(tcg_env, arg);
7651 register_name = "TCScheFBack";
7652 break;
7653 default:
7654 goto cp0_unimplemented;
7655 }
7656 break;
7657 case CP0_REGISTER_03:
7658 switch (sel) {
7659 case CP0_REG03__ENTRYLO1:
7660 gen_helper_dmtc0_entrylo1(tcg_env, arg);
7661 register_name = "EntryLo1";
7662 break;
7663 case CP0_REG03__GLOBALNUM:
7664 CP0_CHECK(ctx->vp);
7665 /* ignored */
7666 register_name = "GlobalNumber";
7667 break;
7668 default:
7669 goto cp0_unimplemented;
7670 }
7671 break;
7672 case CP0_REGISTER_04:
7673 switch (sel) {
7674 case CP0_REG04__CONTEXT:
7675 gen_helper_mtc0_context(tcg_env, arg);
7676 register_name = "Context";
7677 break;
7678 case CP0_REG04__CONTEXTCONFIG:
7679 /* SmartMIPS ASE */
7680 /* gen_helper_dmtc0_contextconfig(arg); */
7681 register_name = "ContextConfig";
7682 goto cp0_unimplemented;
7683 case CP0_REG04__USERLOCAL:
7684 CP0_CHECK(ctx->ulri);
7685 tcg_gen_st_tl(arg, tcg_env,
7686 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
7687 register_name = "UserLocal";
7688 break;
7689 case CP0_REG04__MMID:
7690 CP0_CHECK(ctx->mi);
7691 gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MemoryMapID));
7692 register_name = "MMID";
7693 break;
7694 default:
7695 goto cp0_unimplemented;
7696 }
7697 break;
7698 case CP0_REGISTER_05:
7699 switch (sel) {
7700 case CP0_REG05__PAGEMASK:
7701 gen_helper_mtc0_pagemask(tcg_env, arg);
7702 register_name = "PageMask";
7703 break;
7704 case CP0_REG05__PAGEGRAIN:
7705 check_insn(ctx, ISA_MIPS_R2);
7706 gen_helper_mtc0_pagegrain(tcg_env, arg);
7707 register_name = "PageGrain";
7708 break;
7709 case CP0_REG05__SEGCTL0:
7710 CP0_CHECK(ctx->sc);
7711 gen_helper_mtc0_segctl0(tcg_env, arg);
7712 register_name = "SegCtl0";
7713 break;
7714 case CP0_REG05__SEGCTL1:
7715 CP0_CHECK(ctx->sc);
7716 gen_helper_mtc0_segctl1(tcg_env, arg);
7717 register_name = "SegCtl1";
7718 break;
7719 case CP0_REG05__SEGCTL2:
7720 CP0_CHECK(ctx->sc);
7721 gen_helper_mtc0_segctl2(tcg_env, arg);
7722 register_name = "SegCtl2";
7723 break;
7724 case CP0_REG05__PWBASE:
7725 check_pw(ctx);
7726 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase));
7727 register_name = "PWBase";
7728 break;
7729 case CP0_REG05__PWFIELD:
7730 check_pw(ctx);
7731 gen_helper_mtc0_pwfield(tcg_env, arg);
7732 register_name = "PWField";
7733 break;
7734 case CP0_REG05__PWSIZE:
7735 check_pw(ctx);
7736 gen_helper_mtc0_pwsize(tcg_env, arg);
7737 register_name = "PWSize";
7738 break;
7739 default:
7740 goto cp0_unimplemented;
7741 }
7742 break;
7743 case CP0_REGISTER_06:
7744 switch (sel) {
7745 case CP0_REG06__WIRED:
7746 gen_helper_mtc0_wired(tcg_env, arg);
7747 register_name = "Wired";
7748 break;
7749 case CP0_REG06__SRSCONF0:
7750 check_insn(ctx, ISA_MIPS_R2);
7751 gen_helper_mtc0_srsconf0(tcg_env, arg);
7752 register_name = "SRSConf0";
7753 break;
7754 case CP0_REG06__SRSCONF1:
7755 check_insn(ctx, ISA_MIPS_R2);
7756 gen_helper_mtc0_srsconf1(tcg_env, arg);
7757 register_name = "SRSConf1";
7758 break;
7759 case CP0_REG06__SRSCONF2:
7760 check_insn(ctx, ISA_MIPS_R2);
7761 gen_helper_mtc0_srsconf2(tcg_env, arg);
7762 register_name = "SRSConf2";
7763 break;
7764 case CP0_REG06__SRSCONF3:
7765 check_insn(ctx, ISA_MIPS_R2);
7766 gen_helper_mtc0_srsconf3(tcg_env, arg);
7767 register_name = "SRSConf3";
7768 break;
7769 case CP0_REG06__SRSCONF4:
7770 check_insn(ctx, ISA_MIPS_R2);
7771 gen_helper_mtc0_srsconf4(tcg_env, arg);
7772 register_name = "SRSConf4";
7773 break;
7774 case CP0_REG06__PWCTL:
7775 check_pw(ctx);
7776 gen_helper_mtc0_pwctl(tcg_env, arg);
7777 register_name = "PWCtl";
7778 break;
7779 default:
7780 goto cp0_unimplemented;
7781 }
7782 break;
7783 case CP0_REGISTER_07:
7784 switch (sel) {
7785 case CP0_REG07__HWRENA:
7786 check_insn(ctx, ISA_MIPS_R2);
7787 gen_helper_mtc0_hwrena(tcg_env, arg);
7788 ctx->base.is_jmp = DISAS_STOP;
7789 register_name = "HWREna";
7790 break;
7791 default:
7792 goto cp0_unimplemented;
7793 }
7794 break;
7795 case CP0_REGISTER_08:
7796 switch (sel) {
7797 case CP0_REG08__BADVADDR:
7798 /* ignored */
7799 register_name = "BadVAddr";
7800 break;
7801 case CP0_REG08__BADINSTR:
7802 /* ignored */
7803 register_name = "BadInstr";
7804 break;
7805 case CP0_REG08__BADINSTRP:
7806 /* ignored */
7807 register_name = "BadInstrP";
7808 break;
7809 case CP0_REG08__BADINSTRX:
7810 /* ignored */
7811 register_name = "BadInstrX";
7812 break;
7813 default:
7814 goto cp0_unimplemented;
7815 }
7816 break;
7817 case CP0_REGISTER_09:
7818 switch (sel) {
7819 case CP0_REG09__COUNT:
7820 gen_helper_mtc0_count(tcg_env, arg);
7821 register_name = "Count";
7822 break;
7823 default:
7824 goto cp0_unimplemented;
7825 }
7826 /* Stop translation as we may have switched the execution mode */
7827 ctx->base.is_jmp = DISAS_STOP;
7828 break;
7829 case CP0_REGISTER_10:
7830 switch (sel) {
7831 case CP0_REG10__ENTRYHI:
7832 gen_helper_mtc0_entryhi(tcg_env, arg);
7833 register_name = "EntryHi";
7834 break;
7835 default:
7836 goto cp0_unimplemented;
7837 }
7838 break;
7839 case CP0_REGISTER_11:
7840 switch (sel) {
7841 case CP0_REG11__COMPARE:
7842 gen_helper_mtc0_compare(tcg_env, arg);
7843 register_name = "Compare";
7844 break;
7845 /* 6,7 are implementation dependent */
7846 default:
7847 goto cp0_unimplemented;
7848 }
7849 /* Stop translation as we may have switched the execution mode */
7850 ctx->base.is_jmp = DISAS_STOP;
7851 break;
7852 case CP0_REGISTER_12:
7853 switch (sel) {
7854 case CP0_REG12__STATUS:
7855 save_cpu_state(ctx, 1);
7856 gen_helper_mtc0_status(tcg_env, arg);
7857 /* DISAS_STOP isn't good enough here, hflags may have changed. */
7858 gen_save_pc(ctx->base.pc_next + 4);
7859 ctx->base.is_jmp = DISAS_EXIT;
7860 register_name = "Status";
7861 break;
7862 case CP0_REG12__INTCTL:
7863 check_insn(ctx, ISA_MIPS_R2);
7864 gen_helper_mtc0_intctl(tcg_env, arg);
7865 /* Stop translation as we may have switched the execution mode */
7866 ctx->base.is_jmp = DISAS_STOP;
7867 register_name = "IntCtl";
7868 break;
7869 case CP0_REG12__SRSCTL:
7870 check_insn(ctx, ISA_MIPS_R2);
7871 gen_helper_mtc0_srsctl(tcg_env, arg);
7872 /* Stop translation as we may have switched the execution mode */
7873 ctx->base.is_jmp = DISAS_STOP;
7874 register_name = "SRSCtl";
7875 break;
7876 case CP0_REG12__SRSMAP:
7877 check_insn(ctx, ISA_MIPS_R2);
7878 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
7879 /* Stop translation as we may have switched the execution mode */
7880 ctx->base.is_jmp = DISAS_STOP;
7881 register_name = "SRSMap";
7882 break;
7883 default:
7884 goto cp0_unimplemented;
7885 }
7886 break;
7887 case CP0_REGISTER_13:
7888 switch (sel) {
7889 case CP0_REG13__CAUSE:
7890 save_cpu_state(ctx, 1);
7891 gen_helper_mtc0_cause(tcg_env, arg);
7892 /*
7893 * Stop translation as we may have triggered an interrupt.
7894 * DISAS_STOP isn't sufficient, we need to ensure we break out of
7895 * translated code to check for pending interrupts.
7896 */
7897 gen_save_pc(ctx->base.pc_next + 4);
7898 ctx->base.is_jmp = DISAS_EXIT;
7899 register_name = "Cause";
7900 break;
7901 default:
7902 goto cp0_unimplemented;
7903 }
7904 break;
7905 case CP0_REGISTER_14:
7906 switch (sel) {
7907 case CP0_REG14__EPC:
7908 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC));
7909 register_name = "EPC";
7910 break;
7911 default:
7912 goto cp0_unimplemented;
7913 }
7914 break;
7915 case CP0_REGISTER_15:
7916 switch (sel) {
7917 case CP0_REG15__PRID:
7918 /* ignored */
7919 register_name = "PRid";
7920 break;
7921 case CP0_REG15__EBASE:
7922 check_insn(ctx, ISA_MIPS_R2);
7923 gen_helper_mtc0_ebase(tcg_env, arg);
7924 register_name = "EBase";
7925 break;
7926 default:
7927 goto cp0_unimplemented;
7928 }
7929 break;
7930 case CP0_REGISTER_16:
7931 switch (sel) {
7932 case CP0_REG16__CONFIG:
7933 gen_helper_mtc0_config0(tcg_env, arg);
7934 register_name = "Config";
7935 /* Stop translation as we may have switched the execution mode */
7936 ctx->base.is_jmp = DISAS_STOP;
7937 break;
7938 case CP0_REG16__CONFIG1:
7939 /* ignored, read only */
7940 register_name = "Config1";
7941 break;
7942 case CP0_REG16__CONFIG2:
7943 gen_helper_mtc0_config2(tcg_env, arg);
7944 register_name = "Config2";
7945 /* Stop translation as we may have switched the execution mode */
7946 ctx->base.is_jmp = DISAS_STOP;
7947 break;
7948 case CP0_REG16__CONFIG3:
7949 gen_helper_mtc0_config3(tcg_env, arg);
7950 register_name = "Config3";
7951 /* Stop translation as we may have switched the execution mode */
7952 ctx->base.is_jmp = DISAS_STOP;
7953 break;
7954 case CP0_REG16__CONFIG4:
7955 /* currently ignored */
7956 register_name = "Config4";
7957 break;
7958 case CP0_REG16__CONFIG5:
7959 gen_helper_mtc0_config5(tcg_env, arg);
7960 register_name = "Config5";
7961 /* Stop translation as we may have switched the execution mode */
7962 ctx->base.is_jmp = DISAS_STOP;
7963 break;
7964 /* 6,7 are implementation dependent */
7965 default:
7966 register_name = "Invalid config selector";
7967 goto cp0_unimplemented;
7968 }
7969 break;
7970 case CP0_REGISTER_17:
7971 switch (sel) {
7972 case CP0_REG17__LLADDR:
7973 gen_helper_mtc0_lladdr(tcg_env, arg);
7974 register_name = "LLAddr";
7975 break;
7976 case CP0_REG17__MAAR:
7977 CP0_CHECK(ctx->mrp);
7978 gen_helper_mtc0_maar(tcg_env, arg);
7979 register_name = "MAAR";
7980 break;
7981 case CP0_REG17__MAARI:
7982 CP0_CHECK(ctx->mrp);
7983 gen_helper_mtc0_maari(tcg_env, arg);
7984 register_name = "MAARI";
7985 break;
7986 default:
7987 goto cp0_unimplemented;
7988 }
7989 break;
7990 case CP0_REGISTER_18:
7991 switch (sel) {
7992 case CP0_REG18__WATCHLO0:
7993 case CP0_REG18__WATCHLO1:
7994 case CP0_REG18__WATCHLO2:
7995 case CP0_REG18__WATCHLO3:
7996 case CP0_REG18__WATCHLO4:
7997 case CP0_REG18__WATCHLO5:
7998 case CP0_REG18__WATCHLO6:
7999 case CP0_REG18__WATCHLO7:
8000 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
8001 gen_helper_0e1i(mtc0_watchlo, arg, sel);
8002 register_name = "WatchLo";
8003 break;
8004 default:
8005 goto cp0_unimplemented;
8006 }
8007 break;
8008 case CP0_REGISTER_19:
8009 switch (sel) {
8010 case CP0_REG19__WATCHHI0:
8011 case CP0_REG19__WATCHHI1:
8012 case CP0_REG19__WATCHHI2:
8013 case CP0_REG19__WATCHHI3:
8014 case CP0_REG19__WATCHHI4:
8015 case CP0_REG19__WATCHHI5:
8016 case CP0_REG19__WATCHHI6:
8017 case CP0_REG19__WATCHHI7:
8018 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
8019 gen_helper_0e1i(mtc0_watchhi, arg, sel);
8020 register_name = "WatchHi";
8021 break;
8022 default:
8023 goto cp0_unimplemented;
8024 }
8025 break;
8026 case CP0_REGISTER_20:
8027 switch (sel) {
8028 case CP0_REG20__XCONTEXT:
8029 check_insn(ctx, ISA_MIPS3);
8030 gen_helper_mtc0_xcontext(tcg_env, arg);
8031 register_name = "XContext";
8032 break;
8033 default:
8034 goto cp0_unimplemented;
8035 }
8036 break;
8037 case CP0_REGISTER_21:
8038 /* Officially reserved, but sel 0 is used for R1x000 framemask */
8039 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6));
8040 switch (sel) {
8041 case 0:
8042 gen_helper_mtc0_framemask(tcg_env, arg);
8043 register_name = "Framemask";
8044 break;
8045 default:
8046 goto cp0_unimplemented;
8047 }
8048 break;
8049 case CP0_REGISTER_22:
8050 /* ignored */
8051 register_name = "Diagnostic"; /* implementation dependent */
8052 break;
8053 case CP0_REGISTER_23:
8054 switch (sel) {
8055 case CP0_REG23__DEBUG:
8056 gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */
8057 /* DISAS_STOP isn't good enough here, hflags may have changed. */
8058 gen_save_pc(ctx->base.pc_next + 4);
8059 ctx->base.is_jmp = DISAS_EXIT;
8060 register_name = "Debug";
8061 break;
8062 case CP0_REG23__TRACECONTROL:
8063 /* PDtrace support */
8064 /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */
8065 /* Stop translation as we may have switched the execution mode */
8066 ctx->base.is_jmp = DISAS_STOP;
8067 register_name = "TraceControl";
8068 goto cp0_unimplemented;
8069 case CP0_REG23__TRACECONTROL2:
8070 /* PDtrace support */
8071 /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */
8072 /* Stop translation as we may have switched the execution mode */
8073 ctx->base.is_jmp = DISAS_STOP;
8074 register_name = "TraceControl2";
8075 goto cp0_unimplemented;
8076 case CP0_REG23__USERTRACEDATA1:
8077 /* PDtrace support */
8078 /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/
8079 /* Stop translation as we may have switched the execution mode */
8080 ctx->base.is_jmp = DISAS_STOP;
8081 register_name = "UserTraceData1";
8082 goto cp0_unimplemented;
8083 case CP0_REG23__TRACEIBPC:
8084 /* PDtrace support */
8085 /* gen_helper_mtc0_traceibpc(tcg_env, arg); */
8086 /* Stop translation as we may have switched the execution mode */
8087 ctx->base.is_jmp = DISAS_STOP;
8088 register_name = "TraceIBPC";
8089 goto cp0_unimplemented;
8090 case CP0_REG23__TRACEDBPC:
8091 /* PDtrace support */
8092 /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */
8093 /* Stop translation as we may have switched the execution mode */
8094 ctx->base.is_jmp = DISAS_STOP;
8095 register_name = "TraceDBPC";
8096 goto cp0_unimplemented;
8097 default:
8098 goto cp0_unimplemented;
8099 }
8100 break;
8101 case CP0_REGISTER_24:
8102 switch (sel) {
8103 case CP0_REG24__DEPC:
8104 /* EJTAG support */
8105 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC));
8106 register_name = "DEPC";
8107 break;
8108 default:
8109 goto cp0_unimplemented;
8110 }
8111 break;
8112 case CP0_REGISTER_25:
8113 switch (sel) {
8114 case CP0_REG25__PERFCTL0:
8115 gen_helper_mtc0_performance0(tcg_env, arg);
8116 register_name = "Performance0";
8117 break;
8118 case CP0_REG25__PERFCNT0:
8119 /* gen_helper_mtc0_performance1(tcg_env, arg); */
8120 register_name = "Performance1";
8121 goto cp0_unimplemented;
8122 case CP0_REG25__PERFCTL1:
8123 /* gen_helper_mtc0_performance2(tcg_env, arg); */
8124 register_name = "Performance2";
8125 goto cp0_unimplemented;
8126 case CP0_REG25__PERFCNT1:
8127 /* gen_helper_mtc0_performance3(tcg_env, arg); */
8128 register_name = "Performance3";
8129 goto cp0_unimplemented;
8130 case CP0_REG25__PERFCTL2:
8131 /* gen_helper_mtc0_performance4(tcg_env, arg); */
8132 register_name = "Performance4";
8133 goto cp0_unimplemented;
8134 case CP0_REG25__PERFCNT2:
8135 /* gen_helper_mtc0_performance5(tcg_env, arg); */
8136 register_name = "Performance5";
8137 goto cp0_unimplemented;
8138 case CP0_REG25__PERFCTL3:
8139 /* gen_helper_mtc0_performance6(tcg_env, arg); */
8140 register_name = "Performance6";
8141 goto cp0_unimplemented;
8142 case CP0_REG25__PERFCNT3:
8143 /* gen_helper_mtc0_performance7(tcg_env, arg); */
8144 register_name = "Performance7";
8145 goto cp0_unimplemented;
8146 default:
8147 goto cp0_unimplemented;
8148 }
8149 break;
8150 case CP0_REGISTER_26:
8151 switch (sel) {
8152 case CP0_REG26__ERRCTL:
8153 gen_helper_mtc0_errctl(tcg_env, arg);
8154 ctx->base.is_jmp = DISAS_STOP;
8155 register_name = "ErrCtl";
8156 break;
8157 default:
8158 goto cp0_unimplemented;
8159 }
8160 break;
8161 case CP0_REGISTER_27:
8162 switch (sel) {
8163 case CP0_REG27__CACHERR:
8164 /* ignored */
8165 register_name = "CacheErr";
8166 break;
8167 default:
8168 goto cp0_unimplemented;
8169 }
8170 break;
8171 case CP0_REGISTER_28:
8172 switch (sel) {
8173 case CP0_REG28__TAGLO:
8174 case CP0_REG28__TAGLO1:
8175 case CP0_REG28__TAGLO2:
8176 case CP0_REG28__TAGLO3:
8177 gen_helper_mtc0_taglo(tcg_env, arg);
8178 register_name = "TagLo";
8179 break;
8180 case CP0_REG28__DATALO:
8181 case CP0_REG28__DATALO1:
8182 case CP0_REG28__DATALO2:
8183 case CP0_REG28__DATALO3:
8184 gen_helper_mtc0_datalo(tcg_env, arg);
8185 register_name = "DataLo";
8186 break;
8187 default:
8188 goto cp0_unimplemented;
8189 }
8190 break;
8191 case CP0_REGISTER_29:
8192 switch (sel) {
8193 case CP0_REG29__TAGHI:
8194 case CP0_REG29__TAGHI1:
8195 case CP0_REG29__TAGHI2:
8196 case CP0_REG29__TAGHI3:
8197 gen_helper_mtc0_taghi(tcg_env, arg);
8198 register_name = "TagHi";
8199 break;
8200 case CP0_REG29__DATAHI:
8201 case CP0_REG29__DATAHI1:
8202 case CP0_REG29__DATAHI2:
8203 case CP0_REG29__DATAHI3:
8204 gen_helper_mtc0_datahi(tcg_env, arg);
8205 register_name = "DataHi";
8206 break;
8207 default:
8208 register_name = "invalid sel";
8209 goto cp0_unimplemented;
8210 }
8211 break;
8212 case CP0_REGISTER_30:
8213 switch (sel) {
8214 case CP0_REG30__ERROREPC:
8215 tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
8216 register_name = "ErrorEPC";
8217 break;
8218 default:
8219 goto cp0_unimplemented;
8220 }
8221 break;
8222 case CP0_REGISTER_31:
8223 switch (sel) {
8224 case CP0_REG31__DESAVE:
8225 /* EJTAG support */
8226 gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
8227 register_name = "DESAVE";
8228 break;
8229 case CP0_REG31__KSCRATCH1:
8230 case CP0_REG31__KSCRATCH2:
8231 case CP0_REG31__KSCRATCH3:
8232 case CP0_REG31__KSCRATCH4:
8233 case CP0_REG31__KSCRATCH5:
8234 case CP0_REG31__KSCRATCH6:
8235 CP0_CHECK(ctx->kscrexist & (1 << sel));
8236 tcg_gen_st_tl(arg, tcg_env,
8237 offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
8238 register_name = "KScratch";
8239 break;
8240 default:
8241 goto cp0_unimplemented;
8242 }
8243 break;
8244 default:
8245 goto cp0_unimplemented;
8246 }
8247 trace_mips_translate_c0("dmtc0", register_name, reg, sel);
8248
8249 /* For simplicity assume that all writes can cause interrupts. */
8250 if (icount) {
8251 /*
8252 * DISAS_STOP isn't sufficient, we need to ensure we break out of
8253 * translated code to check for pending interrupts.
8254 */
8255 gen_save_pc(ctx->base.pc_next + 4);
8256 ctx->base.is_jmp = DISAS_EXIT;
8257 }
8258 return;
8259
8260 cp0_unimplemented:
8261 qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n",
8262 register_name, reg, sel);
8263 }
8264 #endif /* TARGET_MIPS64 */
8265
8266 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
8267 int u, int sel, int h)
8268 {
8269 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
8270 TCGv t0 = tcg_temp_new();
8271
8272 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
8273 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
8274 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
8275 tcg_gen_movi_tl(t0, -1);
8276 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
8277 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
8278 tcg_gen_movi_tl(t0, -1);
8279 } else if (u == 0) {
8280 switch (rt) {
8281 case 1:
8282 switch (sel) {
8283 case 1:
8284 gen_helper_mftc0_vpecontrol(t0, tcg_env);
8285 break;
8286 case 2:
8287 gen_helper_mftc0_vpeconf0(t0, tcg_env);
8288 break;
8289 default:
8290 goto die;
8291 break;
8292 }
8293 break;
8294 case 2:
8295 switch (sel) {
8296 case 1:
8297 gen_helper_mftc0_tcstatus(t0, tcg_env);
8298 break;
8299 case 2:
8300 gen_helper_mftc0_tcbind(t0, tcg_env);
8301 break;
8302 case 3:
8303 gen_helper_mftc0_tcrestart(t0, tcg_env);
8304 break;
8305 case 4:
8306 gen_helper_mftc0_tchalt(t0, tcg_env);
8307 break;
8308 case 5:
8309 gen_helper_mftc0_tccontext(t0, tcg_env);
8310 break;
8311 case 6:
8312 gen_helper_mftc0_tcschedule(t0, tcg_env);
8313 break;
8314 case 7:
8315 gen_helper_mftc0_tcschefback(t0, tcg_env);
8316 break;
8317 default:
8318 gen_mfc0(ctx, t0, rt, sel);
8319 break;
8320 }
8321 break;
8322 case 10:
8323 switch (sel) {
8324 case 0:
8325 gen_helper_mftc0_entryhi(t0, tcg_env);
8326 break;
8327 default:
8328 gen_mfc0(ctx, t0, rt, sel);
8329 break;
8330 }
8331 break;
8332 case 12:
8333 switch (sel) {
8334 case 0:
8335 gen_helper_mftc0_status(t0, tcg_env);
8336 break;
8337 default:
8338 gen_mfc0(ctx, t0, rt, sel);
8339 break;
8340 }
8341 break;
8342 case 13:
8343 switch (sel) {
8344 case 0:
8345 gen_helper_mftc0_cause(t0, tcg_env);
8346 break;
8347 default:
8348 goto die;
8349 break;
8350 }
8351 break;
8352 case 14:
8353 switch (sel) {
8354 case 0:
8355 gen_helper_mftc0_epc(t0, tcg_env);
8356 break;
8357 default:
8358 goto die;
8359 break;
8360 }
8361 break;
8362 case 15:
8363 switch (sel) {
8364 case 1:
8365 gen_helper_mftc0_ebase(t0, tcg_env);
8366 break;
8367 default:
8368 goto die;
8369 break;
8370 }
8371 break;
8372 case 16:
8373 switch (sel) {
8374 case 0:
8375 case 1:
8376 case 2:
8377 case 3:
8378 case 4:
8379 case 5:
8380 case 6:
8381 case 7:
8382 gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel));
8383 break;
8384 default:
8385 goto die;
8386 break;
8387 }
8388 break;
8389 case 23:
8390 switch (sel) {
8391 case 0:
8392 gen_helper_mftc0_debug(t0, tcg_env);
8393 break;
8394 default:
8395 gen_mfc0(ctx, t0, rt, sel);
8396 break;
8397 }
8398 break;
8399 default:
8400 gen_mfc0(ctx, t0, rt, sel);
8401 }
8402 } else {
8403 switch (sel) {
8404 /* GPR registers. */
8405 case 0:
8406 gen_helper_1e0i(mftgpr, t0, rt);
8407 break;
8408 /* Auxiliary CPU registers */
8409 case 1:
8410 switch (rt) {
8411 case 0:
8412 gen_helper_1e0i(mftlo, t0, 0);
8413 break;
8414 case 1:
8415 gen_helper_1e0i(mfthi, t0, 0);
8416 break;
8417 case 2:
8418 gen_helper_1e0i(mftacx, t0, 0);
8419 break;
8420 case 4:
8421 gen_helper_1e0i(mftlo, t0, 1);
8422 break;
8423 case 5:
8424 gen_helper_1e0i(mfthi, t0, 1);
8425 break;
8426 case 6:
8427 gen_helper_1e0i(mftacx, t0, 1);
8428 break;
8429 case 8:
8430 gen_helper_1e0i(mftlo, t0, 2);
8431 break;
8432 case 9:
8433 gen_helper_1e0i(mfthi, t0, 2);
8434 break;
8435 case 10:
8436 gen_helper_1e0i(mftacx, t0, 2);
8437 break;
8438 case 12:
8439 gen_helper_1e0i(mftlo, t0, 3);
8440 break;
8441 case 13:
8442 gen_helper_1e0i(mfthi, t0, 3);
8443 break;
8444 case 14:
8445 gen_helper_1e0i(mftacx, t0, 3);
8446 break;
8447 case 16:
8448 gen_helper_mftdsp(t0, tcg_env);
8449 break;
8450 default:
8451 goto die;
8452 }
8453 break;
8454 /* Floating point (COP1). */
8455 case 2:
8456 /* XXX: For now we support only a single FPU context. */
8457 if (h == 0) {
8458 TCGv_i32 fp0 = tcg_temp_new_i32();
8459
8460 gen_load_fpr32(ctx, fp0, rt);
8461 tcg_gen_ext_i32_tl(t0, fp0);
8462 } else {
8463 TCGv_i32 fp0 = tcg_temp_new_i32();
8464
8465 gen_load_fpr32h(ctx, fp0, rt);
8466 tcg_gen_ext_i32_tl(t0, fp0);
8467 }
8468 break;
8469 case 3:
8470 /* XXX: For now we support only a single FPU context. */
8471 gen_helper_1e0i(cfc1, t0, rt);
8472 break;
8473 /* COP2: Not implemented. */
8474 case 4:
8475 case 5:
8476 /* fall through */
8477 default:
8478 goto die;
8479 }
8480 }
8481 trace_mips_translate_tr("mftr", rt, u, sel, h);
8482 gen_store_gpr(t0, rd);
8483 return;
8484
8485 die:
8486 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
8487 gen_reserved_instruction(ctx);
8488 }
8489
8490 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
8491 int u, int sel, int h)
8492 {
8493 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
8494 TCGv t0 = tcg_temp_new();
8495
8496 gen_load_gpr(t0, rt);
8497 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 &&
8498 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) !=
8499 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) {
8500 /* NOP */
8501 ;
8502 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
8503 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) {
8504 /* NOP */
8505 ;
8506 } else if (u == 0) {
8507 switch (rd) {
8508 case 1:
8509 switch (sel) {
8510 case 1:
8511 gen_helper_mttc0_vpecontrol(tcg_env, t0);
8512 break;
8513 case 2:
8514 gen_helper_mttc0_vpeconf0(tcg_env, t0);
8515 break;
8516 default:
8517 goto die;
8518 break;
8519 }
8520 break;
8521 case 2:
8522 switch (sel) {
8523 case 1:
8524 gen_helper_mttc0_tcstatus(tcg_env, t0);
8525 break;
8526 case 2:
8527 gen_helper_mttc0_tcbind(tcg_env, t0);
8528 break;
8529 case 3:
8530 gen_helper_mttc0_tcrestart(tcg_env, t0);
8531 break;
8532 case 4:
8533 gen_helper_mttc0_tchalt(tcg_env, t0);
8534 break;
8535 case 5:
8536 gen_helper_mttc0_tccontext(tcg_env, t0);
8537 break;
8538 case 6:
8539 gen_helper_mttc0_tcschedule(tcg_env, t0);
8540 break;
8541 case 7:
8542 gen_helper_mttc0_tcschefback(tcg_env, t0);
8543 break;
8544 default:
8545 gen_mtc0(ctx, t0, rd, sel);
8546 break;
8547 }
8548 break;
8549 case 10:
8550 switch (sel) {
8551 case 0:
8552 gen_helper_mttc0_entryhi(tcg_env, t0);
8553 break;
8554 default:
8555 gen_mtc0(ctx, t0, rd, sel);
8556 break;
8557 }
8558 break;
8559 case 12:
8560 switch (sel) {
8561 case 0:
8562 gen_helper_mttc0_status(tcg_env, t0);
8563 break;
8564 default:
8565 gen_mtc0(ctx, t0, rd, sel);
8566 break;
8567 }
8568 break;
8569 case 13:
8570 switch (sel) {
8571 case 0:
8572 gen_helper_mttc0_cause(tcg_env, t0);
8573 break;
8574 default:
8575 goto die;
8576 break;
8577 }
8578 break;
8579 case 15:
8580 switch (sel) {
8581 case 1:
8582 gen_helper_mttc0_ebase(tcg_env, t0);
8583 break;
8584 default:
8585 goto die;
8586 break;
8587 }
8588 break;
8589 case 23:
8590 switch (sel) {
8591 case 0:
8592 gen_helper_mttc0_debug(tcg_env, t0);
8593 break;
8594 default:
8595 gen_mtc0(ctx, t0, rd, sel);
8596 break;
8597 }
8598 break;
8599 default:
8600 gen_mtc0(ctx, t0, rd, sel);
8601 }
8602 } else {
8603 switch (sel) {
8604 /* GPR registers. */
8605 case 0:
8606 gen_helper_0e1i(mttgpr, t0, rd);
8607 break;
8608 /* Auxiliary CPU registers */
8609 case 1:
8610 switch (rd) {
8611 case 0:
8612 gen_helper_0e1i(mttlo, t0, 0);
8613 break;
8614 case 1:
8615 gen_helper_0e1i(mtthi, t0, 0);
8616 break;
8617 case 2:
8618 gen_helper_0e1i(mttacx, t0, 0);
8619 break;
8620 case 4:
8621 gen_helper_0e1i(mttlo, t0, 1);
8622 break;
8623 case 5:
8624 gen_helper_0e1i(mtthi, t0, 1);
8625 break;
8626 case 6:
8627 gen_helper_0e1i(mttacx, t0, 1);
8628 break;
8629 case 8:
8630 gen_helper_0e1i(mttlo, t0, 2);
8631 break;
8632 case 9:
8633 gen_helper_0e1i(mtthi, t0, 2);
8634 break;
8635 case 10:
8636 gen_helper_0e1i(mttacx, t0, 2);
8637 break;
8638 case 12:
8639 gen_helper_0e1i(mttlo, t0, 3);
8640 break;
8641 case 13:
8642 gen_helper_0e1i(mtthi, t0, 3);
8643 break;
8644 case 14:
8645 gen_helper_0e1i(mttacx, t0, 3);
8646 break;
8647 case 16:
8648 gen_helper_mttdsp(tcg_env, t0);
8649 break;
8650 default:
8651 goto die;
8652 }
8653 break;
8654 /* Floating point (COP1). */
8655 case 2:
8656 /* XXX: For now we support only a single FPU context. */
8657 if (h == 0) {
8658 TCGv_i32 fp0 = tcg_temp_new_i32();
8659
8660 tcg_gen_trunc_tl_i32(fp0, t0);
8661 gen_store_fpr32(ctx, fp0, rd);
8662 } else {
8663 TCGv_i32 fp0 = tcg_temp_new_i32();
8664
8665 tcg_gen_trunc_tl_i32(fp0, t0);
8666 gen_store_fpr32h(ctx, fp0, rd);
8667 }
8668 break;
8669 case 3:
8670 /* XXX: For now we support only a single FPU context. */
8671 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(rd), rt);
8672 /* Stop translation as we may have changed hflags */
8673 ctx->base.is_jmp = DISAS_STOP;
8674 break;
8675 /* COP2: Not implemented. */
8676 case 4:
8677 case 5:
8678 /* fall through */
8679 default:
8680 goto die;
8681 }
8682 }
8683 trace_mips_translate_tr("mttr", rd, u, sel, h);
8684 return;
8685
8686 die:
8687 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
8688 gen_reserved_instruction(ctx);
8689 }
8690
8691 static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
8692 int rt, int rd)
8693 {
8694 const char *opn = "ldst";
8695
8696 check_cp0_enabled(ctx);
8697 switch (opc) {
8698 case OPC_MFC0:
8699 if (rt == 0) {
8700 /* Treat as NOP. */
8701 return;
8702 }
8703 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
8704 opn = "mfc0";
8705 break;
8706 case OPC_MTC0:
8707 {
8708 TCGv t0 = tcg_temp_new();
8709
8710 gen_load_gpr(t0, rt);
8711 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7);
8712 }
8713 opn = "mtc0";
8714 break;
8715 #if defined(TARGET_MIPS64)
8716 case OPC_DMFC0:
8717 check_insn(ctx, ISA_MIPS3);
8718 if (rt == 0) {
8719 /* Treat as NOP. */
8720 return;
8721 }
8722 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
8723 opn = "dmfc0";
8724 break;
8725 case OPC_DMTC0:
8726 check_insn(ctx, ISA_MIPS3);
8727 {
8728 TCGv t0 = tcg_temp_new();
8729
8730 gen_load_gpr(t0, rt);
8731 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7);
8732 }
8733 opn = "dmtc0";
8734 break;
8735 #endif
8736 case OPC_MFHC0:
8737 check_mvh(ctx);
8738 if (rt == 0) {
8739 /* Treat as NOP. */
8740 return;
8741 }
8742 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7);
8743 opn = "mfhc0";
8744 break;
8745 case OPC_MTHC0:
8746 check_mvh(ctx);
8747 {
8748 TCGv t0 = tcg_temp_new();
8749 gen_load_gpr(t0, rt);
8750 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7);
8751 }
8752 opn = "mthc0";
8753 break;
8754 case OPC_MFTR:
8755 check_cp0_enabled(ctx);
8756 if (rd == 0) {
8757 /* Treat as NOP. */
8758 return;
8759 }
8760 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1,
8761 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
8762 opn = "mftr";
8763 break;
8764 case OPC_MTTR:
8765 check_cp0_enabled(ctx);
8766 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1,
8767 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1);
8768 opn = "mttr";
8769 break;
8770 case OPC_TLBWI:
8771 opn = "tlbwi";
8772 if (!env->tlb->helper_tlbwi) {
8773 goto die;
8774 }
8775 gen_helper_tlbwi(tcg_env);
8776 break;
8777 case OPC_TLBINV:
8778 opn = "tlbinv";
8779 if (ctx->ie >= 2) {
8780 if (!env->tlb->helper_tlbinv) {
8781 goto die;
8782 }
8783 gen_helper_tlbinv(tcg_env);
8784 } /* treat as nop if TLBINV not supported */
8785 break;
8786 case OPC_TLBINVF:
8787 opn = "tlbinvf";
8788 if (ctx->ie >= 2) {
8789 if (!env->tlb->helper_tlbinvf) {
8790 goto die;
8791 }
8792 gen_helper_tlbinvf(tcg_env);
8793 } /* treat as nop if TLBINV not supported */
8794 break;
8795 case OPC_TLBWR:
8796 opn = "tlbwr";
8797 if (!env->tlb->helper_tlbwr) {
8798 goto die;
8799 }
8800 gen_helper_tlbwr(tcg_env);
8801 break;
8802 case OPC_TLBP:
8803 opn = "tlbp";
8804 if (!env->tlb->helper_tlbp) {
8805 goto die;
8806 }
8807 gen_helper_tlbp(tcg_env);
8808 break;
8809 case OPC_TLBR:
8810 opn = "tlbr";
8811 if (!env->tlb->helper_tlbr) {
8812 goto die;
8813 }
8814 gen_helper_tlbr(tcg_env);
8815 break;
8816 case OPC_ERET: /* OPC_ERETNC */
8817 if ((ctx->insn_flags & ISA_MIPS_R6) &&
8818 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8819 goto die;
8820 } else {
8821 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6;
8822 if (ctx->opcode & (1 << bit_shift)) {
8823 /* OPC_ERETNC */
8824 opn = "eretnc";
8825 check_insn(ctx, ISA_MIPS_R5);
8826 gen_helper_eretnc(tcg_env);
8827 } else {
8828 /* OPC_ERET */
8829 opn = "eret";
8830 check_insn(ctx, ISA_MIPS2);
8831 gen_helper_eret(tcg_env);
8832 }
8833 ctx->base.is_jmp = DISAS_EXIT;
8834 }
8835 break;
8836 case OPC_DERET:
8837 opn = "deret";
8838 check_insn(ctx, ISA_MIPS_R1);
8839 if ((ctx->insn_flags & ISA_MIPS_R6) &&
8840 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8841 goto die;
8842 }
8843 if (!(ctx->hflags & MIPS_HFLAG_DM)) {
8844 MIPS_INVAL(opn);
8845 gen_reserved_instruction(ctx);
8846 } else {
8847 gen_helper_deret(tcg_env);
8848 ctx->base.is_jmp = DISAS_EXIT;
8849 }
8850 break;
8851 case OPC_WAIT:
8852 opn = "wait";
8853 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
8854 if ((ctx->insn_flags & ISA_MIPS_R6) &&
8855 (ctx->hflags & MIPS_HFLAG_BMASK)) {
8856 goto die;
8857 }
8858 /* If we get an exception, we want to restart at next instruction */
8859 ctx->base.pc_next += 4;
8860 save_cpu_state(ctx, 1);
8861 ctx->base.pc_next -= 4;
8862 gen_helper_wait(tcg_env);
8863 ctx->base.is_jmp = DISAS_NORETURN;
8864 break;
8865 default:
8866 die:
8867 MIPS_INVAL(opn);
8868 gen_reserved_instruction(ctx);
8869 return;
8870 }
8871 (void)opn; /* avoid a compiler warning */
8872 }
8873 #endif /* !CONFIG_USER_ONLY */
8874
8875 /* CP1 Branches (before delay slot) */
8876 static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
8877 int32_t cc, int32_t offset)
8878 {
8879 target_ulong btarget;
8880 TCGv_i32 t0 = tcg_temp_new_i32();
8881
8882 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
8883 gen_reserved_instruction(ctx);
8884 return;
8885 }
8886
8887 if (cc != 0) {
8888 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
8889 }
8890
8891 btarget = ctx->base.pc_next + 4 + offset;
8892
8893 switch (op) {
8894 case OPC_BC1F:
8895 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8896 tcg_gen_not_i32(t0, t0);
8897 tcg_gen_andi_i32(t0, t0, 1);
8898 tcg_gen_extu_i32_tl(bcond, t0);
8899 goto not_likely;
8900 case OPC_BC1FL:
8901 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8902 tcg_gen_not_i32(t0, t0);
8903 tcg_gen_andi_i32(t0, t0, 1);
8904 tcg_gen_extu_i32_tl(bcond, t0);
8905 goto likely;
8906 case OPC_BC1T:
8907 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8908 tcg_gen_andi_i32(t0, t0, 1);
8909 tcg_gen_extu_i32_tl(bcond, t0);
8910 goto not_likely;
8911 case OPC_BC1TL:
8912 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8913 tcg_gen_andi_i32(t0, t0, 1);
8914 tcg_gen_extu_i32_tl(bcond, t0);
8915 likely:
8916 ctx->hflags |= MIPS_HFLAG_BL;
8917 break;
8918 case OPC_BC1FANY2:
8919 {
8920 TCGv_i32 t1 = tcg_temp_new_i32();
8921 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8922 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
8923 tcg_gen_nand_i32(t0, t0, t1);
8924 tcg_gen_andi_i32(t0, t0, 1);
8925 tcg_gen_extu_i32_tl(bcond, t0);
8926 }
8927 goto not_likely;
8928 case OPC_BC1TANY2:
8929 {
8930 TCGv_i32 t1 = tcg_temp_new_i32();
8931 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8932 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
8933 tcg_gen_or_i32(t0, t0, t1);
8934 tcg_gen_andi_i32(t0, t0, 1);
8935 tcg_gen_extu_i32_tl(bcond, t0);
8936 }
8937 goto not_likely;
8938 case OPC_BC1FANY4:
8939 {
8940 TCGv_i32 t1 = tcg_temp_new_i32();
8941 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8942 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
8943 tcg_gen_and_i32(t0, t0, t1);
8944 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
8945 tcg_gen_and_i32(t0, t0, t1);
8946 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
8947 tcg_gen_nand_i32(t0, t0, t1);
8948 tcg_gen_andi_i32(t0, t0, 1);
8949 tcg_gen_extu_i32_tl(bcond, t0);
8950 }
8951 goto not_likely;
8952 case OPC_BC1TANY4:
8953 {
8954 TCGv_i32 t1 = tcg_temp_new_i32();
8955 tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
8956 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1));
8957 tcg_gen_or_i32(t0, t0, t1);
8958 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 2));
8959 tcg_gen_or_i32(t0, t0, t1);
8960 tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3));
8961 tcg_gen_or_i32(t0, t0, t1);
8962 tcg_gen_andi_i32(t0, t0, 1);
8963 tcg_gen_extu_i32_tl(bcond, t0);
8964 }
8965 not_likely:
8966 ctx->hflags |= MIPS_HFLAG_BC;
8967 break;
8968 default:
8969 MIPS_INVAL("cp1 cond branch");
8970 gen_reserved_instruction(ctx);
8971 return;
8972 }
8973 ctx->btarget = btarget;
8974 ctx->hflags |= MIPS_HFLAG_BDS32;
8975 }
8976
8977 /* R6 CP1 Branches */
8978 static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
8979 int32_t ft, int32_t offset,
8980 int delayslot_size)
8981 {
8982 target_ulong btarget;
8983 TCGv_i64 t0 = tcg_temp_new_i64();
8984
8985 if (ctx->hflags & MIPS_HFLAG_BMASK) {
8986 #ifdef MIPS_DEBUG_DISAS
8987 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
8988 VADDR_PRIx "\n", ctx->base.pc_next);
8989 #endif
8990 gen_reserved_instruction(ctx);
8991 return;
8992 }
8993
8994 gen_load_fpr64(ctx, t0, ft);
8995 tcg_gen_andi_i64(t0, t0, 1);
8996
8997 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
8998
8999 switch (op) {
9000 case OPC_BC1EQZ:
9001 tcg_gen_xori_i64(t0, t0, 1);
9002 ctx->hflags |= MIPS_HFLAG_BC;
9003 break;
9004 case OPC_BC1NEZ:
9005 /* t0 already set */
9006 ctx->hflags |= MIPS_HFLAG_BC;
9007 break;
9008 default:
9009 MIPS_INVAL("cp1 cond branch");
9010 gen_reserved_instruction(ctx);
9011 return;
9012 }
9013
9014 tcg_gen_trunc_i64_tl(bcond, t0);
9015
9016 ctx->btarget = btarget;
9017
9018 switch (delayslot_size) {
9019 case 2:
9020 ctx->hflags |= MIPS_HFLAG_BDS16;
9021 break;
9022 case 4:
9023 ctx->hflags |= MIPS_HFLAG_BDS32;
9024 break;
9025 }
9026 }
9027
9028 /* Coprocessor 1 (FPU) */
9029
9030 #define FOP(func, fmt) (((fmt) << 21) | (func))
9031
9032 enum fopcode {
9033 OPC_ADD_S = FOP(0, FMT_S),
9034 OPC_SUB_S = FOP(1, FMT_S),
9035 OPC_MUL_S = FOP(2, FMT_S),
9036 OPC_DIV_S = FOP(3, FMT_S),
9037 OPC_SQRT_S = FOP(4, FMT_S),
9038 OPC_ABS_S = FOP(5, FMT_S),
9039 OPC_MOV_S = FOP(6, FMT_S),
9040 OPC_NEG_S = FOP(7, FMT_S),
9041 OPC_ROUND_L_S = FOP(8, FMT_S),
9042 OPC_TRUNC_L_S = FOP(9, FMT_S),
9043 OPC_CEIL_L_S = FOP(10, FMT_S),
9044 OPC_FLOOR_L_S = FOP(11, FMT_S),
9045 OPC_ROUND_W_S = FOP(12, FMT_S),
9046 OPC_TRUNC_W_S = FOP(13, FMT_S),
9047 OPC_CEIL_W_S = FOP(14, FMT_S),
9048 OPC_FLOOR_W_S = FOP(15, FMT_S),
9049 OPC_SEL_S = FOP(16, FMT_S),
9050 OPC_MOVCF_S = FOP(17, FMT_S),
9051 OPC_MOVZ_S = FOP(18, FMT_S),
9052 OPC_MOVN_S = FOP(19, FMT_S),
9053 OPC_SELEQZ_S = FOP(20, FMT_S),
9054 OPC_RECIP_S = FOP(21, FMT_S),
9055 OPC_RSQRT_S = FOP(22, FMT_S),
9056 OPC_SELNEZ_S = FOP(23, FMT_S),
9057 OPC_MADDF_S = FOP(24, FMT_S),
9058 OPC_MSUBF_S = FOP(25, FMT_S),
9059 OPC_RINT_S = FOP(26, FMT_S),
9060 OPC_CLASS_S = FOP(27, FMT_S),
9061 OPC_MIN_S = FOP(28, FMT_S),
9062 OPC_RECIP2_S = FOP(28, FMT_S),
9063 OPC_MINA_S = FOP(29, FMT_S),
9064 OPC_RECIP1_S = FOP(29, FMT_S),
9065 OPC_MAX_S = FOP(30, FMT_S),
9066 OPC_RSQRT1_S = FOP(30, FMT_S),
9067 OPC_MAXA_S = FOP(31, FMT_S),
9068 OPC_RSQRT2_S = FOP(31, FMT_S),
9069 OPC_CVT_D_S = FOP(33, FMT_S),
9070 OPC_CVT_W_S = FOP(36, FMT_S),
9071 OPC_CVT_L_S = FOP(37, FMT_S),
9072 OPC_CVT_PS_S = FOP(38, FMT_S),
9073 OPC_CMP_F_S = FOP(48, FMT_S),
9074 OPC_CMP_UN_S = FOP(49, FMT_S),
9075 OPC_CMP_EQ_S = FOP(50, FMT_S),
9076 OPC_CMP_UEQ_S = FOP(51, FMT_S),
9077 OPC_CMP_OLT_S = FOP(52, FMT_S),
9078 OPC_CMP_ULT_S = FOP(53, FMT_S),
9079 OPC_CMP_OLE_S = FOP(54, FMT_S),
9080 OPC_CMP_ULE_S = FOP(55, FMT_S),
9081 OPC_CMP_SF_S = FOP(56, FMT_S),
9082 OPC_CMP_NGLE_S = FOP(57, FMT_S),
9083 OPC_CMP_SEQ_S = FOP(58, FMT_S),
9084 OPC_CMP_NGL_S = FOP(59, FMT_S),
9085 OPC_CMP_LT_S = FOP(60, FMT_S),
9086 OPC_CMP_NGE_S = FOP(61, FMT_S),
9087 OPC_CMP_LE_S = FOP(62, FMT_S),
9088 OPC_CMP_NGT_S = FOP(63, FMT_S),
9089
9090 OPC_ADD_D = FOP(0, FMT_D),
9091 OPC_SUB_D = FOP(1, FMT_D),
9092 OPC_MUL_D = FOP(2, FMT_D),
9093 OPC_DIV_D = FOP(3, FMT_D),
9094 OPC_SQRT_D = FOP(4, FMT_D),
9095 OPC_ABS_D = FOP(5, FMT_D),
9096 OPC_MOV_D = FOP(6, FMT_D),
9097 OPC_NEG_D = FOP(7, FMT_D),
9098 OPC_ROUND_L_D = FOP(8, FMT_D),
9099 OPC_TRUNC_L_D = FOP(9, FMT_D),
9100 OPC_CEIL_L_D = FOP(10, FMT_D),
9101 OPC_FLOOR_L_D = FOP(11, FMT_D),
9102 OPC_ROUND_W_D = FOP(12, FMT_D),
9103 OPC_TRUNC_W_D = FOP(13, FMT_D),
9104 OPC_CEIL_W_D = FOP(14, FMT_D),
9105 OPC_FLOOR_W_D = FOP(15, FMT_D),
9106 OPC_SEL_D = FOP(16, FMT_D),
9107 OPC_MOVCF_D = FOP(17, FMT_D),
9108 OPC_MOVZ_D = FOP(18, FMT_D),
9109 OPC_MOVN_D = FOP(19, FMT_D),
9110 OPC_SELEQZ_D = FOP(20, FMT_D),
9111 OPC_RECIP_D = FOP(21, FMT_D),
9112 OPC_RSQRT_D = FOP(22, FMT_D),
9113 OPC_SELNEZ_D = FOP(23, FMT_D),
9114 OPC_MADDF_D = FOP(24, FMT_D),
9115 OPC_MSUBF_D = FOP(25, FMT_D),
9116 OPC_RINT_D = FOP(26, FMT_D),
9117 OPC_CLASS_D = FOP(27, FMT_D),
9118 OPC_MIN_D = FOP(28, FMT_D),
9119 OPC_RECIP2_D = FOP(28, FMT_D),
9120 OPC_MINA_D = FOP(29, FMT_D),
9121 OPC_RECIP1_D = FOP(29, FMT_D),
9122 OPC_MAX_D = FOP(30, FMT_D),
9123 OPC_RSQRT1_D = FOP(30, FMT_D),
9124 OPC_MAXA_D = FOP(31, FMT_D),
9125 OPC_RSQRT2_D = FOP(31, FMT_D),
9126 OPC_CVT_S_D = FOP(32, FMT_D),
9127 OPC_CVT_W_D = FOP(36, FMT_D),
9128 OPC_CVT_L_D = FOP(37, FMT_D),
9129 OPC_CMP_F_D = FOP(48, FMT_D),
9130 OPC_CMP_UN_D = FOP(49, FMT_D),
9131 OPC_CMP_EQ_D = FOP(50, FMT_D),
9132 OPC_CMP_UEQ_D = FOP(51, FMT_D),
9133 OPC_CMP_OLT_D = FOP(52, FMT_D),
9134 OPC_CMP_ULT_D = FOP(53, FMT_D),
9135 OPC_CMP_OLE_D = FOP(54, FMT_D),
9136 OPC_CMP_ULE_D = FOP(55, FMT_D),
9137 OPC_CMP_SF_D = FOP(56, FMT_D),
9138 OPC_CMP_NGLE_D = FOP(57, FMT_D),
9139 OPC_CMP_SEQ_D = FOP(58, FMT_D),
9140 OPC_CMP_NGL_D = FOP(59, FMT_D),
9141 OPC_CMP_LT_D = FOP(60, FMT_D),
9142 OPC_CMP_NGE_D = FOP(61, FMT_D),
9143 OPC_CMP_LE_D = FOP(62, FMT_D),
9144 OPC_CMP_NGT_D = FOP(63, FMT_D),
9145
9146 OPC_CVT_S_W = FOP(32, FMT_W),
9147 OPC_CVT_D_W = FOP(33, FMT_W),
9148 OPC_CVT_S_L = FOP(32, FMT_L),
9149 OPC_CVT_D_L = FOP(33, FMT_L),
9150 OPC_CVT_PS_PW = FOP(38, FMT_W),
9151
9152 OPC_ADD_PS = FOP(0, FMT_PS),
9153 OPC_SUB_PS = FOP(1, FMT_PS),
9154 OPC_MUL_PS = FOP(2, FMT_PS),
9155 OPC_DIV_PS = FOP(3, FMT_PS),
9156 OPC_ABS_PS = FOP(5, FMT_PS),
9157 OPC_MOV_PS = FOP(6, FMT_PS),
9158 OPC_NEG_PS = FOP(7, FMT_PS),
9159 OPC_MOVCF_PS = FOP(17, FMT_PS),
9160 OPC_MOVZ_PS = FOP(18, FMT_PS),
9161 OPC_MOVN_PS = FOP(19, FMT_PS),
9162 OPC_ADDR_PS = FOP(24, FMT_PS),
9163 OPC_MULR_PS = FOP(26, FMT_PS),
9164 OPC_RECIP2_PS = FOP(28, FMT_PS),
9165 OPC_RECIP1_PS = FOP(29, FMT_PS),
9166 OPC_RSQRT1_PS = FOP(30, FMT_PS),
9167 OPC_RSQRT2_PS = FOP(31, FMT_PS),
9168
9169 OPC_CVT_S_PU = FOP(32, FMT_PS),
9170 OPC_CVT_PW_PS = FOP(36, FMT_PS),
9171 OPC_CVT_S_PL = FOP(40, FMT_PS),
9172 OPC_PLL_PS = FOP(44, FMT_PS),
9173 OPC_PLU_PS = FOP(45, FMT_PS),
9174 OPC_PUL_PS = FOP(46, FMT_PS),
9175 OPC_PUU_PS = FOP(47, FMT_PS),
9176 OPC_CMP_F_PS = FOP(48, FMT_PS),
9177 OPC_CMP_UN_PS = FOP(49, FMT_PS),
9178 OPC_CMP_EQ_PS = FOP(50, FMT_PS),
9179 OPC_CMP_UEQ_PS = FOP(51, FMT_PS),
9180 OPC_CMP_OLT_PS = FOP(52, FMT_PS),
9181 OPC_CMP_ULT_PS = FOP(53, FMT_PS),
9182 OPC_CMP_OLE_PS = FOP(54, FMT_PS),
9183 OPC_CMP_ULE_PS = FOP(55, FMT_PS),
9184 OPC_CMP_SF_PS = FOP(56, FMT_PS),
9185 OPC_CMP_NGLE_PS = FOP(57, FMT_PS),
9186 OPC_CMP_SEQ_PS = FOP(58, FMT_PS),
9187 OPC_CMP_NGL_PS = FOP(59, FMT_PS),
9188 OPC_CMP_LT_PS = FOP(60, FMT_PS),
9189 OPC_CMP_NGE_PS = FOP(61, FMT_PS),
9190 OPC_CMP_LE_PS = FOP(62, FMT_PS),
9191 OPC_CMP_NGT_PS = FOP(63, FMT_PS),
9192 };
9193
9194 enum r6_f_cmp_op {
9195 R6_OPC_CMP_AF_S = FOP(0, FMT_W),
9196 R6_OPC_CMP_UN_S = FOP(1, FMT_W),
9197 R6_OPC_CMP_EQ_S = FOP(2, FMT_W),
9198 R6_OPC_CMP_UEQ_S = FOP(3, FMT_W),
9199 R6_OPC_CMP_LT_S = FOP(4, FMT_W),
9200 R6_OPC_CMP_ULT_S = FOP(5, FMT_W),
9201 R6_OPC_CMP_LE_S = FOP(6, FMT_W),
9202 R6_OPC_CMP_ULE_S = FOP(7, FMT_W),
9203 R6_OPC_CMP_SAF_S = FOP(8, FMT_W),
9204 R6_OPC_CMP_SUN_S = FOP(9, FMT_W),
9205 R6_OPC_CMP_SEQ_S = FOP(10, FMT_W),
9206 R6_OPC_CMP_SEUQ_S = FOP(11, FMT_W),
9207 R6_OPC_CMP_SLT_S = FOP(12, FMT_W),
9208 R6_OPC_CMP_SULT_S = FOP(13, FMT_W),
9209 R6_OPC_CMP_SLE_S = FOP(14, FMT_W),
9210 R6_OPC_CMP_SULE_S = FOP(15, FMT_W),
9211 R6_OPC_CMP_OR_S = FOP(17, FMT_W),
9212 R6_OPC_CMP_UNE_S = FOP(18, FMT_W),
9213 R6_OPC_CMP_NE_S = FOP(19, FMT_W),
9214 R6_OPC_CMP_SOR_S = FOP(25, FMT_W),
9215 R6_OPC_CMP_SUNE_S = FOP(26, FMT_W),
9216 R6_OPC_CMP_SNE_S = FOP(27, FMT_W),
9217
9218 R6_OPC_CMP_AF_D = FOP(0, FMT_L),
9219 R6_OPC_CMP_UN_D = FOP(1, FMT_L),
9220 R6_OPC_CMP_EQ_D = FOP(2, FMT_L),
9221 R6_OPC_CMP_UEQ_D = FOP(3, FMT_L),
9222 R6_OPC_CMP_LT_D = FOP(4, FMT_L),
9223 R6_OPC_CMP_ULT_D = FOP(5, FMT_L),
9224 R6_OPC_CMP_LE_D = FOP(6, FMT_L),
9225 R6_OPC_CMP_ULE_D = FOP(7, FMT_L),
9226 R6_OPC_CMP_SAF_D = FOP(8, FMT_L),
9227 R6_OPC_CMP_SUN_D = FOP(9, FMT_L),
9228 R6_OPC_CMP_SEQ_D = FOP(10, FMT_L),
9229 R6_OPC_CMP_SEUQ_D = FOP(11, FMT_L),
9230 R6_OPC_CMP_SLT_D = FOP(12, FMT_L),
9231 R6_OPC_CMP_SULT_D = FOP(13, FMT_L),
9232 R6_OPC_CMP_SLE_D = FOP(14, FMT_L),
9233 R6_OPC_CMP_SULE_D = FOP(15, FMT_L),
9234 R6_OPC_CMP_OR_D = FOP(17, FMT_L),
9235 R6_OPC_CMP_UNE_D = FOP(18, FMT_L),
9236 R6_OPC_CMP_NE_D = FOP(19, FMT_L),
9237 R6_OPC_CMP_SOR_D = FOP(25, FMT_L),
9238 R6_OPC_CMP_SUNE_D = FOP(26, FMT_L),
9239 R6_OPC_CMP_SNE_D = FOP(27, FMT_L),
9240 };
9241
9242 static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
9243 {
9244 TCGv t0 = tcg_temp_new();
9245
9246 switch (opc) {
9247 case OPC_MFC1:
9248 {
9249 TCGv_i32 fp0 = tcg_temp_new_i32();
9250
9251 gen_load_fpr32(ctx, fp0, fs);
9252 tcg_gen_ext_i32_tl(t0, fp0);
9253 }
9254 gen_store_gpr(t0, rt);
9255 break;
9256 case OPC_MTC1:
9257 gen_load_gpr(t0, rt);
9258 {
9259 TCGv_i32 fp0 = tcg_temp_new_i32();
9260
9261 tcg_gen_trunc_tl_i32(fp0, t0);
9262 gen_store_fpr32(ctx, fp0, fs);
9263 }
9264 break;
9265 case OPC_CFC1:
9266 gen_helper_1e0i(cfc1, t0, fs);
9267 gen_store_gpr(t0, rt);
9268 break;
9269 case OPC_CTC1:
9270 gen_load_gpr(t0, rt);
9271 save_cpu_state(ctx, 0);
9272 gen_helper_0e2i(ctc1, t0, tcg_constant_i32(fs), rt);
9273 /* Stop translation as we may have changed hflags */
9274 ctx->base.is_jmp = DISAS_STOP;
9275 break;
9276 #if defined(TARGET_MIPS64)
9277 case OPC_DMFC1:
9278 gen_load_fpr64(ctx, t0, fs);
9279 gen_store_gpr(t0, rt);
9280 break;
9281 case OPC_DMTC1:
9282 gen_load_gpr(t0, rt);
9283 gen_store_fpr64(ctx, t0, fs);
9284 break;
9285 #endif
9286 case OPC_MFHC1:
9287 {
9288 TCGv_i32 fp0 = tcg_temp_new_i32();
9289
9290 gen_load_fpr32h(ctx, fp0, fs);
9291 tcg_gen_ext_i32_tl(t0, fp0);
9292 }
9293 gen_store_gpr(t0, rt);
9294 break;
9295 case OPC_MTHC1:
9296 gen_load_gpr(t0, rt);
9297 {
9298 TCGv_i32 fp0 = tcg_temp_new_i32();
9299
9300 tcg_gen_trunc_tl_i32(fp0, t0);
9301 gen_store_fpr32h(ctx, fp0, fs);
9302 }
9303 break;
9304 default:
9305 MIPS_INVAL("cp1 move");
9306 gen_reserved_instruction(ctx);
9307 return;
9308 }
9309 }
9310
9311 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf)
9312 {
9313 TCGLabel *l1;
9314 TCGCond cond;
9315 TCGv_i32 t0;
9316
9317 if (rd == 0) {
9318 /* Treat as NOP. */
9319 return;
9320 }
9321
9322 if (tf) {
9323 cond = TCG_COND_EQ;
9324 } else {
9325 cond = TCG_COND_NE;
9326 }
9327
9328 l1 = gen_new_label();
9329 t0 = tcg_temp_new_i32();
9330 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9331 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9332 gen_load_gpr(cpu_gpr[rd], rs);
9333 gen_set_label(l1);
9334 }
9335
9336 static inline void gen_movcf_s(DisasContext *ctx, int fs, int fd, int cc,
9337 int tf)
9338 {
9339 int cond;
9340 TCGv_i32 t0 = tcg_temp_new_i32();
9341 TCGLabel *l1 = gen_new_label();
9342
9343 if (tf) {
9344 cond = TCG_COND_EQ;
9345 } else {
9346 cond = TCG_COND_NE;
9347 }
9348
9349 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9350 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9351 gen_load_fpr32(ctx, t0, fs);
9352 gen_store_fpr32(ctx, t0, fd);
9353 gen_set_label(l1);
9354 }
9355
9356 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc,
9357 int tf)
9358 {
9359 int cond;
9360 TCGv_i32 t0 = tcg_temp_new_i32();
9361 TCGv_i64 fp0;
9362 TCGLabel *l1 = gen_new_label();
9363
9364 if (tf) {
9365 cond = TCG_COND_EQ;
9366 } else {
9367 cond = TCG_COND_NE;
9368 }
9369
9370 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9371 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9372 fp0 = tcg_temp_new_i64();
9373 gen_load_fpr64(ctx, fp0, fs);
9374 gen_store_fpr64(ctx, fp0, fd);
9375 gen_set_label(l1);
9376 }
9377
9378 static inline void gen_movcf_ps(DisasContext *ctx, int fs, int fd,
9379 int cc, int tf)
9380 {
9381 int cond;
9382 TCGv_i32 t0 = tcg_temp_new_i32();
9383 TCGLabel *l1 = gen_new_label();
9384 TCGLabel *l2 = gen_new_label();
9385
9386 if (tf) {
9387 cond = TCG_COND_EQ;
9388 } else {
9389 cond = TCG_COND_NE;
9390 }
9391
9392 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc));
9393 tcg_gen_brcondi_i32(cond, t0, 0, l1);
9394 gen_load_fpr32(ctx, t0, fs);
9395 gen_store_fpr32(ctx, t0, fd);
9396 gen_set_label(l1);
9397
9398 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc + 1));
9399 tcg_gen_brcondi_i32(cond, t0, 0, l2);
9400 gen_load_fpr32h(ctx, t0, fs);
9401 gen_store_fpr32h(ctx, t0, fd);
9402 gen_set_label(l2);
9403 }
9404
9405 static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
9406 int fs)
9407 {
9408 TCGv_i32 t1 = tcg_constant_i32(0);
9409 TCGv_i32 fp0 = tcg_temp_new_i32();
9410 TCGv_i32 fp1 = tcg_temp_new_i32();
9411 TCGv_i32 fp2 = tcg_temp_new_i32();
9412 gen_load_fpr32(ctx, fp0, fd);
9413 gen_load_fpr32(ctx, fp1, ft);
9414 gen_load_fpr32(ctx, fp2, fs);
9415
9416 switch (op1) {
9417 case OPC_SEL_S:
9418 tcg_gen_andi_i32(fp0, fp0, 1);
9419 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
9420 break;
9421 case OPC_SELEQZ_S:
9422 tcg_gen_andi_i32(fp1, fp1, 1);
9423 tcg_gen_movcond_i32(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
9424 break;
9425 case OPC_SELNEZ_S:
9426 tcg_gen_andi_i32(fp1, fp1, 1);
9427 tcg_gen_movcond_i32(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
9428 break;
9429 default:
9430 MIPS_INVAL("gen_sel_s");
9431 gen_reserved_instruction(ctx);
9432 break;
9433 }
9434
9435 gen_store_fpr32(ctx, fp0, fd);
9436 }
9437
9438 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
9439 int fs)
9440 {
9441 TCGv_i64 t1 = tcg_constant_i64(0);
9442 TCGv_i64 fp0 = tcg_temp_new_i64();
9443 TCGv_i64 fp1 = tcg_temp_new_i64();
9444 TCGv_i64 fp2 = tcg_temp_new_i64();
9445 gen_load_fpr64(ctx, fp0, fd);
9446 gen_load_fpr64(ctx, fp1, ft);
9447 gen_load_fpr64(ctx, fp2, fs);
9448
9449 switch (op1) {
9450 case OPC_SEL_D:
9451 tcg_gen_andi_i64(fp0, fp0, 1);
9452 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp0, t1, fp1, fp2);
9453 break;
9454 case OPC_SELEQZ_D:
9455 tcg_gen_andi_i64(fp1, fp1, 1);
9456 tcg_gen_movcond_i64(TCG_COND_EQ, fp0, fp1, t1, fp2, t1);
9457 break;
9458 case OPC_SELNEZ_D:
9459 tcg_gen_andi_i64(fp1, fp1, 1);
9460 tcg_gen_movcond_i64(TCG_COND_NE, fp0, fp1, t1, fp2, t1);
9461 break;
9462 default:
9463 MIPS_INVAL("gen_sel_d");
9464 gen_reserved_instruction(ctx);
9465 break;
9466 }
9467
9468 gen_store_fpr64(ctx, fp0, fd);
9469 }
9470
9471 static void gen_farith(DisasContext *ctx, enum fopcode op1,
9472 int ft, int fs, int fd, int cc)
9473 {
9474 uint32_t func = ctx->opcode & 0x3f;
9475 switch (op1) {
9476 case OPC_ADD_S:
9477 {
9478 TCGv_i32 fp0 = tcg_temp_new_i32();
9479 TCGv_i32 fp1 = tcg_temp_new_i32();
9480
9481 gen_load_fpr32(ctx, fp0, fs);
9482 gen_load_fpr32(ctx, fp1, ft);
9483 gen_helper_float_add_s(fp0, tcg_env, fp0, fp1);
9484 gen_store_fpr32(ctx, fp0, fd);
9485 }
9486 break;
9487 case OPC_SUB_S:
9488 {
9489 TCGv_i32 fp0 = tcg_temp_new_i32();
9490 TCGv_i32 fp1 = tcg_temp_new_i32();
9491
9492 gen_load_fpr32(ctx, fp0, fs);
9493 gen_load_fpr32(ctx, fp1, ft);
9494 gen_helper_float_sub_s(fp0, tcg_env, fp0, fp1);
9495 gen_store_fpr32(ctx, fp0, fd);
9496 }
9497 break;
9498 case OPC_MUL_S:
9499 {
9500 TCGv_i32 fp0 = tcg_temp_new_i32();
9501 TCGv_i32 fp1 = tcg_temp_new_i32();
9502
9503 gen_load_fpr32(ctx, fp0, fs);
9504 gen_load_fpr32(ctx, fp1, ft);
9505 gen_helper_float_mul_s(fp0, tcg_env, fp0, fp1);
9506 gen_store_fpr32(ctx, fp0, fd);
9507 }
9508 break;
9509 case OPC_DIV_S:
9510 {
9511 TCGv_i32 fp0 = tcg_temp_new_i32();
9512 TCGv_i32 fp1 = tcg_temp_new_i32();
9513
9514 gen_load_fpr32(ctx, fp0, fs);
9515 gen_load_fpr32(ctx, fp1, ft);
9516 gen_helper_float_div_s(fp0, tcg_env, fp0, fp1);
9517 gen_store_fpr32(ctx, fp0, fd);
9518 }
9519 break;
9520 case OPC_SQRT_S:
9521 {
9522 TCGv_i32 fp0 = tcg_temp_new_i32();
9523
9524 gen_load_fpr32(ctx, fp0, fs);
9525 gen_helper_float_sqrt_s(fp0, tcg_env, fp0);
9526 gen_store_fpr32(ctx, fp0, fd);
9527 }
9528 break;
9529 case OPC_ABS_S:
9530 {
9531 TCGv_i32 fp0 = tcg_temp_new_i32();
9532
9533 gen_load_fpr32(ctx, fp0, fs);
9534 if (ctx->abs2008) {
9535 tcg_gen_andi_i32(fp0, fp0, 0x7fffffffUL);
9536 } else {
9537 gen_helper_float_abs_s(fp0, fp0);
9538 }
9539 gen_store_fpr32(ctx, fp0, fd);
9540 }
9541 break;
9542 case OPC_MOV_S:
9543 {
9544 TCGv_i32 fp0 = tcg_temp_new_i32();
9545
9546 gen_load_fpr32(ctx, fp0, fs);
9547 gen_store_fpr32(ctx, fp0, fd);
9548 }
9549 break;
9550 case OPC_NEG_S:
9551 {
9552 TCGv_i32 fp0 = tcg_temp_new_i32();
9553
9554 gen_load_fpr32(ctx, fp0, fs);
9555 if (ctx->abs2008) {
9556 tcg_gen_xori_i32(fp0, fp0, 1UL << 31);
9557 } else {
9558 gen_helper_float_chs_s(fp0, fp0);
9559 }
9560 gen_store_fpr32(ctx, fp0, fd);
9561 }
9562 break;
9563 case OPC_ROUND_L_S:
9564 check_cp1_64bitmode(ctx);
9565 {
9566 TCGv_i32 fp32 = tcg_temp_new_i32();
9567 TCGv_i64 fp64 = tcg_temp_new_i64();
9568
9569 gen_load_fpr32(ctx, fp32, fs);
9570 if (ctx->nan2008) {
9571 gen_helper_float_round_2008_l_s(fp64, tcg_env, fp32);
9572 } else {
9573 gen_helper_float_round_l_s(fp64, tcg_env, fp32);
9574 }
9575 gen_store_fpr64(ctx, fp64, fd);
9576 }
9577 break;
9578 case OPC_TRUNC_L_S:
9579 check_cp1_64bitmode(ctx);
9580 {
9581 TCGv_i32 fp32 = tcg_temp_new_i32();
9582 TCGv_i64 fp64 = tcg_temp_new_i64();
9583
9584 gen_load_fpr32(ctx, fp32, fs);
9585 if (ctx->nan2008) {
9586 gen_helper_float_trunc_2008_l_s(fp64, tcg_env, fp32);
9587 } else {
9588 gen_helper_float_trunc_l_s(fp64, tcg_env, fp32);
9589 }
9590 gen_store_fpr64(ctx, fp64, fd);
9591 }
9592 break;
9593 case OPC_CEIL_L_S:
9594 check_cp1_64bitmode(ctx);
9595 {
9596 TCGv_i32 fp32 = tcg_temp_new_i32();
9597 TCGv_i64 fp64 = tcg_temp_new_i64();
9598
9599 gen_load_fpr32(ctx, fp32, fs);
9600 if (ctx->nan2008) {
9601 gen_helper_float_ceil_2008_l_s(fp64, tcg_env, fp32);
9602 } else {
9603 gen_helper_float_ceil_l_s(fp64, tcg_env, fp32);
9604 }
9605 gen_store_fpr64(ctx, fp64, fd);
9606 }
9607 break;
9608 case OPC_FLOOR_L_S:
9609 check_cp1_64bitmode(ctx);
9610 {
9611 TCGv_i32 fp32 = tcg_temp_new_i32();
9612 TCGv_i64 fp64 = tcg_temp_new_i64();
9613
9614 gen_load_fpr32(ctx, fp32, fs);
9615 if (ctx->nan2008) {
9616 gen_helper_float_floor_2008_l_s(fp64, tcg_env, fp32);
9617 } else {
9618 gen_helper_float_floor_l_s(fp64, tcg_env, fp32);
9619 }
9620 gen_store_fpr64(ctx, fp64, fd);
9621 }
9622 break;
9623 case OPC_ROUND_W_S:
9624 {
9625 TCGv_i32 fp0 = tcg_temp_new_i32();
9626
9627 gen_load_fpr32(ctx, fp0, fs);
9628 if (ctx->nan2008) {
9629 gen_helper_float_round_2008_w_s(fp0, tcg_env, fp0);
9630 } else {
9631 gen_helper_float_round_w_s(fp0, tcg_env, fp0);
9632 }
9633 gen_store_fpr32(ctx, fp0, fd);
9634 }
9635 break;
9636 case OPC_TRUNC_W_S:
9637 {
9638 TCGv_i32 fp0 = tcg_temp_new_i32();
9639
9640 gen_load_fpr32(ctx, fp0, fs);
9641 if (ctx->nan2008) {
9642 gen_helper_float_trunc_2008_w_s(fp0, tcg_env, fp0);
9643 } else {
9644 gen_helper_float_trunc_w_s(fp0, tcg_env, fp0);
9645 }
9646 gen_store_fpr32(ctx, fp0, fd);
9647 }
9648 break;
9649 case OPC_CEIL_W_S:
9650 {
9651 TCGv_i32 fp0 = tcg_temp_new_i32();
9652
9653 gen_load_fpr32(ctx, fp0, fs);
9654 if (ctx->nan2008) {
9655 gen_helper_float_ceil_2008_w_s(fp0, tcg_env, fp0);
9656 } else {
9657 gen_helper_float_ceil_w_s(fp0, tcg_env, fp0);
9658 }
9659 gen_store_fpr32(ctx, fp0, fd);
9660 }
9661 break;
9662 case OPC_FLOOR_W_S:
9663 {
9664 TCGv_i32 fp0 = tcg_temp_new_i32();
9665
9666 gen_load_fpr32(ctx, fp0, fs);
9667 if (ctx->nan2008) {
9668 gen_helper_float_floor_2008_w_s(fp0, tcg_env, fp0);
9669 } else {
9670 gen_helper_float_floor_w_s(fp0, tcg_env, fp0);
9671 }
9672 gen_store_fpr32(ctx, fp0, fd);
9673 }
9674 break;
9675 case OPC_SEL_S:
9676 check_insn(ctx, ISA_MIPS_R6);
9677 gen_sel_s(ctx, op1, fd, ft, fs);
9678 break;
9679 case OPC_SELEQZ_S:
9680 check_insn(ctx, ISA_MIPS_R6);
9681 gen_sel_s(ctx, op1, fd, ft, fs);
9682 break;
9683 case OPC_SELNEZ_S:
9684 check_insn(ctx, ISA_MIPS_R6);
9685 gen_sel_s(ctx, op1, fd, ft, fs);
9686 break;
9687 case OPC_MOVCF_S:
9688 check_insn_opc_removed(ctx, ISA_MIPS_R6);
9689 gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
9690 break;
9691 case OPC_MOVZ_S:
9692 check_insn_opc_removed(ctx, ISA_MIPS_R6);
9693 {
9694 TCGLabel *l1 = gen_new_label();
9695 TCGv_i32 fp0;
9696
9697 if (ft != 0) {
9698 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
9699 }
9700 fp0 = tcg_temp_new_i32();
9701 gen_load_fpr32(ctx, fp0, fs);
9702 gen_store_fpr32(ctx, fp0, fd);
9703 gen_set_label(l1);
9704 }
9705 break;
9706 case OPC_MOVN_S:
9707 check_insn_opc_removed(ctx, ISA_MIPS_R6);
9708 {
9709 TCGLabel *l1 = gen_new_label();
9710 TCGv_i32 fp0;
9711
9712 if (ft != 0) {
9713 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
9714 fp0 = tcg_temp_new_i32();
9715 gen_load_fpr32(ctx, fp0, fs);
9716 gen_store_fpr32(ctx, fp0, fd);
9717 gen_set_label(l1);
9718 }
9719 }
9720 break;
9721 case OPC_RECIP_S:
9722 {
9723 TCGv_i32 fp0 = tcg_temp_new_i32();
9724
9725 gen_load_fpr32(ctx, fp0, fs);
9726 gen_helper_float_recip_s(fp0, tcg_env, fp0);
9727 gen_store_fpr32(ctx, fp0, fd);
9728 }
9729 break;
9730 case OPC_RSQRT_S:
9731 {
9732 TCGv_i32 fp0 = tcg_temp_new_i32();
9733
9734 gen_load_fpr32(ctx, fp0, fs);
9735 gen_helper_float_rsqrt_s(fp0, tcg_env, fp0);
9736 gen_store_fpr32(ctx, fp0, fd);
9737 }
9738 break;
9739 case OPC_MADDF_S:
9740 check_insn(ctx, ISA_MIPS_R6);
9741 {
9742 TCGv_i32 fp0 = tcg_temp_new_i32();
9743 TCGv_i32 fp1 = tcg_temp_new_i32();
9744 TCGv_i32 fp2 = tcg_temp_new_i32();
9745 gen_load_fpr32(ctx, fp0, fs);
9746 gen_load_fpr32(ctx, fp1, ft);
9747 gen_load_fpr32(ctx, fp2, fd);
9748 gen_helper_float_maddf_s(fp2, tcg_env, fp0, fp1, fp2);
9749 gen_store_fpr32(ctx, fp2, fd);
9750 }
9751 break;
9752 case OPC_MSUBF_S:
9753 check_insn(ctx, ISA_MIPS_R6);
9754 {
9755 TCGv_i32 fp0 = tcg_temp_new_i32();
9756 TCGv_i32 fp1 = tcg_temp_new_i32();
9757 TCGv_i32 fp2 = tcg_temp_new_i32();
9758 gen_load_fpr32(ctx, fp0, fs);
9759 gen_load_fpr32(ctx, fp1, ft);
9760 gen_load_fpr32(ctx, fp2, fd);
9761 gen_helper_float_msubf_s(fp2, tcg_env, fp0, fp1, fp2);
9762 gen_store_fpr32(ctx, fp2, fd);
9763 }
9764 break;
9765 case OPC_RINT_S:
9766 check_insn(ctx, ISA_MIPS_R6);
9767 {
9768 TCGv_i32 fp0 = tcg_temp_new_i32();
9769 gen_load_fpr32(ctx, fp0, fs);
9770 gen_helper_float_rint_s(fp0, tcg_env, fp0);
9771 gen_store_fpr32(ctx, fp0, fd);
9772 }
9773 break;
9774 case OPC_CLASS_S:
9775 check_insn(ctx, ISA_MIPS_R6);
9776 {
9777 TCGv_i32 fp0 = tcg_temp_new_i32();
9778 gen_load_fpr32(ctx, fp0, fs);
9779 gen_helper_float_class_s(fp0, tcg_env, fp0);
9780 gen_store_fpr32(ctx, fp0, fd);
9781 }
9782 break;
9783 case OPC_MIN_S: /* OPC_RECIP2_S */
9784 if (ctx->insn_flags & ISA_MIPS_R6) {
9785 /* OPC_MIN_S */
9786 TCGv_i32 fp0 = tcg_temp_new_i32();
9787 TCGv_i32 fp1 = tcg_temp_new_i32();
9788 TCGv_i32 fp2 = tcg_temp_new_i32();
9789 gen_load_fpr32(ctx, fp0, fs);
9790 gen_load_fpr32(ctx, fp1, ft);
9791 gen_helper_float_min_s(fp2, tcg_env, fp0, fp1);
9792 gen_store_fpr32(ctx, fp2, fd);
9793 } else {
9794 /* OPC_RECIP2_S */
9795 check_cp1_64bitmode(ctx);
9796 {
9797 TCGv_i32 fp0 = tcg_temp_new_i32();
9798 TCGv_i32 fp1 = tcg_temp_new_i32();
9799
9800 gen_load_fpr32(ctx, fp0, fs);
9801 gen_load_fpr32(ctx, fp1, ft);
9802 gen_helper_float_recip2_s(fp0, tcg_env, fp0, fp1);
9803 gen_store_fpr32(ctx, fp0, fd);
9804 }
9805 }
9806 break;
9807 case OPC_MINA_S: /* OPC_RECIP1_S */
9808 if (ctx->insn_flags & ISA_MIPS_R6) {
9809 /* OPC_MINA_S */
9810 TCGv_i32 fp0 = tcg_temp_new_i32();
9811 TCGv_i32 fp1 = tcg_temp_new_i32();
9812 TCGv_i32 fp2 = tcg_temp_new_i32();
9813 gen_load_fpr32(ctx, fp0, fs);
9814 gen_load_fpr32(ctx, fp1, ft);
9815 gen_helper_float_mina_s(fp2, tcg_env, fp0, fp1);
9816 gen_store_fpr32(ctx, fp2, fd);
9817 } else {
9818 /* OPC_RECIP1_S */
9819 check_cp1_64bitmode(ctx);
9820 {
9821 TCGv_i32 fp0 = tcg_temp_new_i32();
9822
9823 gen_load_fpr32(ctx, fp0, fs);
9824 gen_helper_float_recip1_s(fp0, tcg_env, fp0);
9825 gen_store_fpr32(ctx, fp0, fd);
9826 }
9827 }
9828 break;
9829 case OPC_MAX_S: /* OPC_RSQRT1_S */
9830 if (ctx->insn_flags & ISA_MIPS_R6) {
9831 /* OPC_MAX_S */
9832 TCGv_i32 fp0 = tcg_temp_new_i32();
9833 TCGv_i32 fp1 = tcg_temp_new_i32();
9834 gen_load_fpr32(ctx, fp0, fs);
9835 gen_load_fpr32(ctx, fp1, ft);
9836 gen_helper_float_max_s(fp1, tcg_env, fp0, fp1);
9837 gen_store_fpr32(ctx, fp1, fd);
9838 } else {
9839 /* OPC_RSQRT1_S */
9840 check_cp1_64bitmode(ctx);
9841 {
9842 TCGv_i32 fp0 = tcg_temp_new_i32();
9843
9844 gen_load_fpr32(ctx, fp0, fs);
9845 gen_helper_float_rsqrt1_s(fp0, tcg_env, fp0);
9846 gen_store_fpr32(ctx, fp0, fd);
9847 }
9848 }
9849 break;
9850 case OPC_MAXA_S: /* OPC_RSQRT2_S */
9851 if (ctx->insn_flags & ISA_MIPS_R6) {
9852 /* OPC_MAXA_S */
9853 TCGv_i32 fp0 = tcg_temp_new_i32();
9854 TCGv_i32 fp1 = tcg_temp_new_i32();
9855 gen_load_fpr32(ctx, fp0, fs);
9856 gen_load_fpr32(ctx, fp1, ft);
9857 gen_helper_float_maxa_s(fp1, tcg_env, fp0, fp1);
9858 gen_store_fpr32(ctx, fp1, fd);
9859 } else {
9860 /* OPC_RSQRT2_S */
9861 check_cp1_64bitmode(ctx);
9862 {
9863 TCGv_i32 fp0 = tcg_temp_new_i32();
9864 TCGv_i32 fp1 = tcg_temp_new_i32();
9865
9866 gen_load_fpr32(ctx, fp0, fs);
9867 gen_load_fpr32(ctx, fp1, ft);
9868 gen_helper_float_rsqrt2_s(fp0, tcg_env, fp0, fp1);
9869 gen_store_fpr32(ctx, fp0, fd);
9870 }
9871 }
9872 break;
9873 case OPC_CVT_D_S:
9874 check_cp1_registers(ctx, fd);
9875 {
9876 TCGv_i32 fp32 = tcg_temp_new_i32();
9877 TCGv_i64 fp64 = tcg_temp_new_i64();
9878
9879 gen_load_fpr32(ctx, fp32, fs);
9880 gen_helper_float_cvtd_s(fp64, tcg_env, fp32);
9881 gen_store_fpr64(ctx, fp64, fd);
9882 }
9883 break;
9884 case OPC_CVT_W_S:
9885 {
9886 TCGv_i32 fp0 = tcg_temp_new_i32();
9887
9888 gen_load_fpr32(ctx, fp0, fs);
9889 if (ctx->nan2008) {
9890 gen_helper_float_cvt_2008_w_s(fp0, tcg_env, fp0);
9891 } else {
9892 gen_helper_float_cvt_w_s(fp0, tcg_env, fp0);
9893 }
9894 gen_store_fpr32(ctx, fp0, fd);
9895 }
9896 break;
9897 case OPC_CVT_L_S:
9898 check_cp1_64bitmode(ctx);
9899 {
9900 TCGv_i32 fp32 = tcg_temp_new_i32();
9901 TCGv_i64 fp64 = tcg_temp_new_i64();
9902
9903 gen_load_fpr32(ctx, fp32, fs);
9904 if (ctx->nan2008) {
9905 gen_helper_float_cvt_2008_l_s(fp64, tcg_env, fp32);
9906 } else {
9907 gen_helper_float_cvt_l_s(fp64, tcg_env, fp32);
9908 }
9909 gen_store_fpr64(ctx, fp64, fd);
9910 }
9911 break;
9912 case OPC_CVT_PS_S:
9913 check_ps(ctx);
9914 {
9915 TCGv_i64 fp64 = tcg_temp_new_i64();
9916 TCGv_i32 fp32_0 = tcg_temp_new_i32();
9917 TCGv_i32 fp32_1 = tcg_temp_new_i32();
9918
9919 gen_load_fpr32(ctx, fp32_0, fs);
9920 gen_load_fpr32(ctx, fp32_1, ft);
9921 tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0);
9922 gen_store_fpr64(ctx, fp64, fd);
9923 }
9924 break;
9925 case OPC_CMP_F_S:
9926 case OPC_CMP_UN_S:
9927 case OPC_CMP_EQ_S:
9928 case OPC_CMP_UEQ_S:
9929 case OPC_CMP_OLT_S:
9930 case OPC_CMP_ULT_S:
9931 case OPC_CMP_OLE_S:
9932 case OPC_CMP_ULE_S:
9933 case OPC_CMP_SF_S:
9934 case OPC_CMP_NGLE_S:
9935 case OPC_CMP_SEQ_S:
9936 case OPC_CMP_NGL_S:
9937 case OPC_CMP_LT_S:
9938 case OPC_CMP_NGE_S:
9939 case OPC_CMP_LE_S:
9940 case OPC_CMP_NGT_S:
9941 check_insn_opc_removed(ctx, ISA_MIPS_R6);
9942 if (ctx->opcode & (1 << 6)) {
9943 gen_cmpabs_s(ctx, func - 48, ft, fs, cc);
9944 } else {
9945 gen_cmp_s(ctx, func - 48, ft, fs, cc);
9946 }
9947 break;
9948 case OPC_ADD_D:
9949 check_cp1_registers(ctx, fs | ft | fd);
9950 {
9951 TCGv_i64 fp0 = tcg_temp_new_i64();
9952 TCGv_i64 fp1 = tcg_temp_new_i64();
9953
9954 gen_load_fpr64(ctx, fp0, fs);
9955 gen_load_fpr64(ctx, fp1, ft);
9956 gen_helper_float_add_d(fp0, tcg_env, fp0, fp1);
9957 gen_store_fpr64(ctx, fp0, fd);
9958 }
9959 break;
9960 case OPC_SUB_D:
9961 check_cp1_registers(ctx, fs | ft | fd);
9962 {
9963 TCGv_i64 fp0 = tcg_temp_new_i64();
9964 TCGv_i64 fp1 = tcg_temp_new_i64();
9965
9966 gen_load_fpr64(ctx, fp0, fs);
9967 gen_load_fpr64(ctx, fp1, ft);
9968 gen_helper_float_sub_d(fp0, tcg_env, fp0, fp1);
9969 gen_store_fpr64(ctx, fp0, fd);
9970 }
9971 break;
9972 case OPC_MUL_D:
9973 check_cp1_registers(ctx, fs | ft | fd);
9974 {
9975 TCGv_i64 fp0 = tcg_temp_new_i64();
9976 TCGv_i64 fp1 = tcg_temp_new_i64();
9977
9978 gen_load_fpr64(ctx, fp0, fs);
9979 gen_load_fpr64(ctx, fp1, ft);
9980 gen_helper_float_mul_d(fp0, tcg_env, fp0, fp1);
9981 gen_store_fpr64(ctx, fp0, fd);
9982 }
9983 break;
9984 case OPC_DIV_D:
9985 check_cp1_registers(ctx, fs | ft | fd);
9986 {
9987 TCGv_i64 fp0 = tcg_temp_new_i64();
9988 TCGv_i64 fp1 = tcg_temp_new_i64();
9989
9990 gen_load_fpr64(ctx, fp0, fs);
9991 gen_load_fpr64(ctx, fp1, ft);
9992 gen_helper_float_div_d(fp0, tcg_env, fp0, fp1);
9993 gen_store_fpr64(ctx, fp0, fd);
9994 }
9995 break;
9996 case OPC_SQRT_D:
9997 check_cp1_registers(ctx, fs | fd);
9998 {
9999 TCGv_i64 fp0 = tcg_temp_new_i64();
10000
10001 gen_load_fpr64(ctx, fp0, fs);
10002 gen_helper_float_sqrt_d(fp0, tcg_env, fp0);
10003 gen_store_fpr64(ctx, fp0, fd);
10004 }
10005 break;
10006 case OPC_ABS_D:
10007 check_cp1_registers(ctx, fs | fd);
10008 {
10009 TCGv_i64 fp0 = tcg_temp_new_i64();
10010
10011 gen_load_fpr64(ctx, fp0, fs);
10012 if (ctx->abs2008) {
10013 tcg_gen_andi_i64(fp0, fp0, 0x7fffffffffffffffULL);
10014 } else {
10015 gen_helper_float_abs_d(fp0, fp0);
10016 }
10017 gen_store_fpr64(ctx, fp0, fd);
10018 }
10019 break;
10020 case OPC_MOV_D:
10021 check_cp1_registers(ctx, fs | fd);
10022 {
10023 TCGv_i64 fp0 = tcg_temp_new_i64();
10024
10025 gen_load_fpr64(ctx, fp0, fs);
10026 gen_store_fpr64(ctx, fp0, fd);
10027 }
10028 break;
10029 case OPC_NEG_D:
10030 check_cp1_registers(ctx, fs | fd);
10031 {
10032 TCGv_i64 fp0 = tcg_temp_new_i64();
10033
10034 gen_load_fpr64(ctx, fp0, fs);
10035 if (ctx->abs2008) {
10036 tcg_gen_xori_i64(fp0, fp0, 1ULL << 63);
10037 } else {
10038 gen_helper_float_chs_d(fp0, fp0);
10039 }
10040 gen_store_fpr64(ctx, fp0, fd);
10041 }
10042 break;
10043 case OPC_ROUND_L_D:
10044 check_cp1_64bitmode(ctx);
10045 {
10046 TCGv_i64 fp0 = tcg_temp_new_i64();
10047
10048 gen_load_fpr64(ctx, fp0, fs);
10049 if (ctx->nan2008) {
10050 gen_helper_float_round_2008_l_d(fp0, tcg_env, fp0);
10051 } else {
10052 gen_helper_float_round_l_d(fp0, tcg_env, fp0);
10053 }
10054 gen_store_fpr64(ctx, fp0, fd);
10055 }
10056 break;
10057 case OPC_TRUNC_L_D:
10058 check_cp1_64bitmode(ctx);
10059 {
10060 TCGv_i64 fp0 = tcg_temp_new_i64();
10061
10062 gen_load_fpr64(ctx, fp0, fs);
10063 if (ctx->nan2008) {
10064 gen_helper_float_trunc_2008_l_d(fp0, tcg_env, fp0);
10065 } else {
10066 gen_helper_float_trunc_l_d(fp0, tcg_env, fp0);
10067 }
10068 gen_store_fpr64(ctx, fp0, fd);
10069 }
10070 break;
10071 case OPC_CEIL_L_D:
10072 check_cp1_64bitmode(ctx);
10073 {
10074 TCGv_i64 fp0 = tcg_temp_new_i64();
10075
10076 gen_load_fpr64(ctx, fp0, fs);
10077 if (ctx->nan2008) {
10078 gen_helper_float_ceil_2008_l_d(fp0, tcg_env, fp0);
10079 } else {
10080 gen_helper_float_ceil_l_d(fp0, tcg_env, fp0);
10081 }
10082 gen_store_fpr64(ctx, fp0, fd);
10083 }
10084 break;
10085 case OPC_FLOOR_L_D:
10086 check_cp1_64bitmode(ctx);
10087 {
10088 TCGv_i64 fp0 = tcg_temp_new_i64();
10089
10090 gen_load_fpr64(ctx, fp0, fs);
10091 if (ctx->nan2008) {
10092 gen_helper_float_floor_2008_l_d(fp0, tcg_env, fp0);
10093 } else {
10094 gen_helper_float_floor_l_d(fp0, tcg_env, fp0);
10095 }
10096 gen_store_fpr64(ctx, fp0, fd);
10097 }
10098 break;
10099 case OPC_ROUND_W_D:
10100 check_cp1_registers(ctx, fs);
10101 {
10102 TCGv_i32 fp32 = tcg_temp_new_i32();
10103 TCGv_i64 fp64 = tcg_temp_new_i64();
10104
10105 gen_load_fpr64(ctx, fp64, fs);
10106 if (ctx->nan2008) {
10107 gen_helper_float_round_2008_w_d(fp32, tcg_env, fp64);
10108 } else {
10109 gen_helper_float_round_w_d(fp32, tcg_env, fp64);
10110 }
10111 gen_store_fpr32(ctx, fp32, fd);
10112 }
10113 break;
10114 case OPC_TRUNC_W_D:
10115 check_cp1_registers(ctx, fs);
10116 {
10117 TCGv_i32 fp32 = tcg_temp_new_i32();
10118 TCGv_i64 fp64 = tcg_temp_new_i64();
10119
10120 gen_load_fpr64(ctx, fp64, fs);
10121 if (ctx->nan2008) {
10122 gen_helper_float_trunc_2008_w_d(fp32, tcg_env, fp64);
10123 } else {
10124 gen_helper_float_trunc_w_d(fp32, tcg_env, fp64);
10125 }
10126 gen_store_fpr32(ctx, fp32, fd);
10127 }
10128 break;
10129 case OPC_CEIL_W_D:
10130 check_cp1_registers(ctx, fs);
10131 {
10132 TCGv_i32 fp32 = tcg_temp_new_i32();
10133 TCGv_i64 fp64 = tcg_temp_new_i64();
10134
10135 gen_load_fpr64(ctx, fp64, fs);
10136 if (ctx->nan2008) {
10137 gen_helper_float_ceil_2008_w_d(fp32, tcg_env, fp64);
10138 } else {
10139 gen_helper_float_ceil_w_d(fp32, tcg_env, fp64);
10140 }
10141 gen_store_fpr32(ctx, fp32, fd);
10142 }
10143 break;
10144 case OPC_FLOOR_W_D:
10145 check_cp1_registers(ctx, fs);
10146 {
10147 TCGv_i32 fp32 = tcg_temp_new_i32();
10148 TCGv_i64 fp64 = tcg_temp_new_i64();
10149
10150 gen_load_fpr64(ctx, fp64, fs);
10151 if (ctx->nan2008) {
10152 gen_helper_float_floor_2008_w_d(fp32, tcg_env, fp64);
10153 } else {
10154 gen_helper_float_floor_w_d(fp32, tcg_env, fp64);
10155 }
10156 gen_store_fpr32(ctx, fp32, fd);
10157 }
10158 break;
10159 case OPC_SEL_D:
10160 check_insn(ctx, ISA_MIPS_R6);
10161 gen_sel_d(ctx, op1, fd, ft, fs);
10162 break;
10163 case OPC_SELEQZ_D:
10164 check_insn(ctx, ISA_MIPS_R6);
10165 gen_sel_d(ctx, op1, fd, ft, fs);
10166 break;
10167 case OPC_SELNEZ_D:
10168 check_insn(ctx, ISA_MIPS_R6);
10169 gen_sel_d(ctx, op1, fd, ft, fs);
10170 break;
10171 case OPC_MOVCF_D:
10172 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10173 gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
10174 break;
10175 case OPC_MOVZ_D:
10176 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10177 {
10178 TCGLabel *l1 = gen_new_label();
10179 TCGv_i64 fp0;
10180
10181 if (ft != 0) {
10182 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
10183 }
10184 fp0 = tcg_temp_new_i64();
10185 gen_load_fpr64(ctx, fp0, fs);
10186 gen_store_fpr64(ctx, fp0, fd);
10187 gen_set_label(l1);
10188 }
10189 break;
10190 case OPC_MOVN_D:
10191 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10192 {
10193 TCGLabel *l1 = gen_new_label();
10194 TCGv_i64 fp0;
10195
10196 if (ft != 0) {
10197 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
10198 fp0 = tcg_temp_new_i64();
10199 gen_load_fpr64(ctx, fp0, fs);
10200 gen_store_fpr64(ctx, fp0, fd);
10201 gen_set_label(l1);
10202 }
10203 }
10204 break;
10205 case OPC_RECIP_D:
10206 check_cp1_registers(ctx, fs | fd);
10207 {
10208 TCGv_i64 fp0 = tcg_temp_new_i64();
10209
10210 gen_load_fpr64(ctx, fp0, fs);
10211 gen_helper_float_recip_d(fp0, tcg_env, fp0);
10212 gen_store_fpr64(ctx, fp0, fd);
10213 }
10214 break;
10215 case OPC_RSQRT_D:
10216 check_cp1_registers(ctx, fs | fd);
10217 {
10218 TCGv_i64 fp0 = tcg_temp_new_i64();
10219
10220 gen_load_fpr64(ctx, fp0, fs);
10221 gen_helper_float_rsqrt_d(fp0, tcg_env, fp0);
10222 gen_store_fpr64(ctx, fp0, fd);
10223 }
10224 break;
10225 case OPC_MADDF_D:
10226 check_insn(ctx, ISA_MIPS_R6);
10227 {
10228 TCGv_i64 fp0 = tcg_temp_new_i64();
10229 TCGv_i64 fp1 = tcg_temp_new_i64();
10230 TCGv_i64 fp2 = tcg_temp_new_i64();
10231 gen_load_fpr64(ctx, fp0, fs);
10232 gen_load_fpr64(ctx, fp1, ft);
10233 gen_load_fpr64(ctx, fp2, fd);
10234 gen_helper_float_maddf_d(fp2, tcg_env, fp0, fp1, fp2);
10235 gen_store_fpr64(ctx, fp2, fd);
10236 }
10237 break;
10238 case OPC_MSUBF_D:
10239 check_insn(ctx, ISA_MIPS_R6);
10240 {
10241 TCGv_i64 fp0 = tcg_temp_new_i64();
10242 TCGv_i64 fp1 = tcg_temp_new_i64();
10243 TCGv_i64 fp2 = tcg_temp_new_i64();
10244 gen_load_fpr64(ctx, fp0, fs);
10245 gen_load_fpr64(ctx, fp1, ft);
10246 gen_load_fpr64(ctx, fp2, fd);
10247 gen_helper_float_msubf_d(fp2, tcg_env, fp0, fp1, fp2);
10248 gen_store_fpr64(ctx, fp2, fd);
10249 }
10250 break;
10251 case OPC_RINT_D:
10252 check_insn(ctx, ISA_MIPS_R6);
10253 {
10254 TCGv_i64 fp0 = tcg_temp_new_i64();
10255 gen_load_fpr64(ctx, fp0, fs);
10256 gen_helper_float_rint_d(fp0, tcg_env, fp0);
10257 gen_store_fpr64(ctx, fp0, fd);
10258 }
10259 break;
10260 case OPC_CLASS_D:
10261 check_insn(ctx, ISA_MIPS_R6);
10262 {
10263 TCGv_i64 fp0 = tcg_temp_new_i64();
10264 gen_load_fpr64(ctx, fp0, fs);
10265 gen_helper_float_class_d(fp0, tcg_env, fp0);
10266 gen_store_fpr64(ctx, fp0, fd);
10267 }
10268 break;
10269 case OPC_MIN_D: /* OPC_RECIP2_D */
10270 if (ctx->insn_flags & ISA_MIPS_R6) {
10271 /* OPC_MIN_D */
10272 TCGv_i64 fp0 = tcg_temp_new_i64();
10273 TCGv_i64 fp1 = tcg_temp_new_i64();
10274 gen_load_fpr64(ctx, fp0, fs);
10275 gen_load_fpr64(ctx, fp1, ft);
10276 gen_helper_float_min_d(fp1, tcg_env, fp0, fp1);
10277 gen_store_fpr64(ctx, fp1, fd);
10278 } else {
10279 /* OPC_RECIP2_D */
10280 check_cp1_64bitmode(ctx);
10281 {
10282 TCGv_i64 fp0 = tcg_temp_new_i64();
10283 TCGv_i64 fp1 = tcg_temp_new_i64();
10284
10285 gen_load_fpr64(ctx, fp0, fs);
10286 gen_load_fpr64(ctx, fp1, ft);
10287 gen_helper_float_recip2_d(fp0, tcg_env, fp0, fp1);
10288 gen_store_fpr64(ctx, fp0, fd);
10289 }
10290 }
10291 break;
10292 case OPC_MINA_D: /* OPC_RECIP1_D */
10293 if (ctx->insn_flags & ISA_MIPS_R6) {
10294 /* OPC_MINA_D */
10295 TCGv_i64 fp0 = tcg_temp_new_i64();
10296 TCGv_i64 fp1 = tcg_temp_new_i64();
10297 gen_load_fpr64(ctx, fp0, fs);
10298 gen_load_fpr64(ctx, fp1, ft);
10299 gen_helper_float_mina_d(fp1, tcg_env, fp0, fp1);
10300 gen_store_fpr64(ctx, fp1, fd);
10301 } else {
10302 /* OPC_RECIP1_D */
10303 check_cp1_64bitmode(ctx);
10304 {
10305 TCGv_i64 fp0 = tcg_temp_new_i64();
10306
10307 gen_load_fpr64(ctx, fp0, fs);
10308 gen_helper_float_recip1_d(fp0, tcg_env, fp0);
10309 gen_store_fpr64(ctx, fp0, fd);
10310 }
10311 }
10312 break;
10313 case OPC_MAX_D: /* OPC_RSQRT1_D */
10314 if (ctx->insn_flags & ISA_MIPS_R6) {
10315 /* OPC_MAX_D */
10316 TCGv_i64 fp0 = tcg_temp_new_i64();
10317 TCGv_i64 fp1 = tcg_temp_new_i64();
10318 gen_load_fpr64(ctx, fp0, fs);
10319 gen_load_fpr64(ctx, fp1, ft);
10320 gen_helper_float_max_d(fp1, tcg_env, fp0, fp1);
10321 gen_store_fpr64(ctx, fp1, fd);
10322 } else {
10323 /* OPC_RSQRT1_D */
10324 check_cp1_64bitmode(ctx);
10325 {
10326 TCGv_i64 fp0 = tcg_temp_new_i64();
10327
10328 gen_load_fpr64(ctx, fp0, fs);
10329 gen_helper_float_rsqrt1_d(fp0, tcg_env, fp0);
10330 gen_store_fpr64(ctx, fp0, fd);
10331 }
10332 }
10333 break;
10334 case OPC_MAXA_D: /* OPC_RSQRT2_D */
10335 if (ctx->insn_flags & ISA_MIPS_R6) {
10336 /* OPC_MAXA_D */
10337 TCGv_i64 fp0 = tcg_temp_new_i64();
10338 TCGv_i64 fp1 = tcg_temp_new_i64();
10339 gen_load_fpr64(ctx, fp0, fs);
10340 gen_load_fpr64(ctx, fp1, ft);
10341 gen_helper_float_maxa_d(fp1, tcg_env, fp0, fp1);
10342 gen_store_fpr64(ctx, fp1, fd);
10343 } else {
10344 /* OPC_RSQRT2_D */
10345 check_cp1_64bitmode(ctx);
10346 {
10347 TCGv_i64 fp0 = tcg_temp_new_i64();
10348 TCGv_i64 fp1 = tcg_temp_new_i64();
10349
10350 gen_load_fpr64(ctx, fp0, fs);
10351 gen_load_fpr64(ctx, fp1, ft);
10352 gen_helper_float_rsqrt2_d(fp0, tcg_env, fp0, fp1);
10353 gen_store_fpr64(ctx, fp0, fd);
10354 }
10355 }
10356 break;
10357 case OPC_CMP_F_D:
10358 case OPC_CMP_UN_D:
10359 case OPC_CMP_EQ_D:
10360 case OPC_CMP_UEQ_D:
10361 case OPC_CMP_OLT_D:
10362 case OPC_CMP_ULT_D:
10363 case OPC_CMP_OLE_D:
10364 case OPC_CMP_ULE_D:
10365 case OPC_CMP_SF_D:
10366 case OPC_CMP_NGLE_D:
10367 case OPC_CMP_SEQ_D:
10368 case OPC_CMP_NGL_D:
10369 case OPC_CMP_LT_D:
10370 case OPC_CMP_NGE_D:
10371 case OPC_CMP_LE_D:
10372 case OPC_CMP_NGT_D:
10373 check_insn_opc_removed(ctx, ISA_MIPS_R6);
10374 if (ctx->opcode & (1 << 6)) {
10375 gen_cmpabs_d(ctx, func - 48, ft, fs, cc);
10376 } else {
10377 gen_cmp_d(ctx, func - 48, ft, fs, cc);
10378 }
10379 break;
10380 case OPC_CVT_S_D:
10381 check_cp1_registers(ctx, fs);
10382 {
10383 TCGv_i32 fp32 = tcg_temp_new_i32();
10384 TCGv_i64 fp64 = tcg_temp_new_i64();
10385
10386 gen_load_fpr64(ctx, fp64, fs);
10387 gen_helper_float_cvts_d(fp32, tcg_env, fp64);
10388 gen_store_fpr32(ctx, fp32, fd);
10389 }
10390 break;
10391 case OPC_CVT_W_D:
10392 check_cp1_registers(ctx, fs);
10393 {
10394 TCGv_i32 fp32 = tcg_temp_new_i32();
10395 TCGv_i64 fp64 = tcg_temp_new_i64();
10396
10397 gen_load_fpr64(ctx, fp64, fs);
10398 if (ctx->nan2008) {
10399 gen_helper_float_cvt_2008_w_d(fp32, tcg_env, fp64);
10400 } else {
10401 gen_helper_float_cvt_w_d(fp32, tcg_env, fp64);
10402 }
10403 gen_store_fpr32(ctx, fp32, fd);
10404 }
10405 break;
10406 case OPC_CVT_L_D:
10407 check_cp1_64bitmode(ctx);
10408 {
10409 TCGv_i64 fp0 = tcg_temp_new_i64();
10410
10411 gen_load_fpr64(ctx, fp0, fs);
10412 if (ctx->nan2008) {
10413 gen_helper_float_cvt_2008_l_d(fp0, tcg_env, fp0);
10414 } else {
10415 gen_helper_float_cvt_l_d(fp0, tcg_env, fp0);
10416 }
10417 gen_store_fpr64(ctx, fp0, fd);
10418 }
10419 break;
10420 case OPC_CVT_S_W:
10421 {
10422 TCGv_i32 fp0 = tcg_temp_new_i32();
10423
10424 gen_load_fpr32(ctx, fp0, fs);
10425 gen_helper_float_cvts_w(fp0, tcg_env, fp0);
10426 gen_store_fpr32(ctx, fp0, fd);
10427 }
10428 break;
10429 case OPC_CVT_D_W:
10430 check_cp1_registers(ctx, fd);
10431 {
10432 TCGv_i32 fp32 = tcg_temp_new_i32();
10433 TCGv_i64 fp64 = tcg_temp_new_i64();
10434
10435 gen_load_fpr32(ctx, fp32, fs);
10436 gen_helper_float_cvtd_w(fp64, tcg_env, fp32);
10437 gen_store_fpr64(ctx, fp64, fd);
10438 }
10439 break;
10440 case OPC_CVT_S_L:
10441 check_cp1_64bitmode(ctx);
10442 {
10443 TCGv_i32 fp32 = tcg_temp_new_i32();
10444 TCGv_i64 fp64 = tcg_temp_new_i64();
10445
10446 gen_load_fpr64(ctx, fp64, fs);
10447 gen_helper_float_cvts_l(fp32, tcg_env, fp64);
10448 gen_store_fpr32(ctx, fp32, fd);
10449 }
10450 break;
10451 case OPC_CVT_D_L:
10452 check_cp1_64bitmode(ctx);
10453 {
10454 TCGv_i64 fp0 = tcg_temp_new_i64();
10455
10456 gen_load_fpr64(ctx, fp0, fs);
10457 gen_helper_float_cvtd_l(fp0, tcg_env, fp0);
10458 gen_store_fpr64(ctx, fp0, fd);
10459 }
10460 break;
10461 case OPC_CVT_PS_PW:
10462 check_ps(ctx);
10463 {
10464 TCGv_i64 fp0 = tcg_temp_new_i64();
10465
10466 gen_load_fpr64(ctx, fp0, fs);
10467 gen_helper_float_cvtps_pw(fp0, tcg_env, fp0);
10468 gen_store_fpr64(ctx, fp0, fd);
10469 }
10470 break;
10471 case OPC_ADD_PS:
10472 check_ps(ctx);
10473 {
10474 TCGv_i64 fp0 = tcg_temp_new_i64();
10475 TCGv_i64 fp1 = tcg_temp_new_i64();
10476
10477 gen_load_fpr64(ctx, fp0, fs);
10478 gen_load_fpr64(ctx, fp1, ft);
10479 gen_helper_float_add_ps(fp0, tcg_env, fp0, fp1);
10480 gen_store_fpr64(ctx, fp0, fd);
10481 }
10482 break;
10483 case OPC_SUB_PS:
10484 check_ps(ctx);
10485 {
10486 TCGv_i64 fp0 = tcg_temp_new_i64();
10487 TCGv_i64 fp1 = tcg_temp_new_i64();
10488
10489 gen_load_fpr64(ctx, fp0, fs);
10490 gen_load_fpr64(ctx, fp1, ft);
10491 gen_helper_float_sub_ps(fp0, tcg_env, fp0, fp1);
10492 gen_store_fpr64(ctx, fp0, fd);
10493 }
10494 break;
10495 case OPC_MUL_PS:
10496 check_ps(ctx);
10497 {
10498 TCGv_i64 fp0 = tcg_temp_new_i64();
10499 TCGv_i64 fp1 = tcg_temp_new_i64();
10500
10501 gen_load_fpr64(ctx, fp0, fs);
10502 gen_load_fpr64(ctx, fp1, ft);
10503 gen_helper_float_mul_ps(fp0, tcg_env, fp0, fp1);
10504 gen_store_fpr64(ctx, fp0, fd);
10505 }
10506 break;
10507 case OPC_ABS_PS:
10508 check_ps(ctx);
10509 {
10510 TCGv_i64 fp0 = tcg_temp_new_i64();
10511
10512 gen_load_fpr64(ctx, fp0, fs);
10513 gen_helper_float_abs_ps(fp0, fp0);
10514 gen_store_fpr64(ctx, fp0, fd);
10515 }
10516 break;
10517 case OPC_MOV_PS:
10518 check_ps(ctx);
10519 {
10520 TCGv_i64 fp0 = tcg_temp_new_i64();
10521
10522 gen_load_fpr64(ctx, fp0, fs);
10523 gen_store_fpr64(ctx, fp0, fd);
10524 }
10525 break;
10526 case OPC_NEG_PS:
10527 check_ps(ctx);
10528 {
10529 TCGv_i64 fp0 = tcg_temp_new_i64();
10530
10531 gen_load_fpr64(ctx, fp0, fs);
10532 gen_helper_float_chs_ps(fp0, fp0);
10533 gen_store_fpr64(ctx, fp0, fd);
10534 }
10535 break;
10536 case OPC_MOVCF_PS:
10537 check_ps(ctx);
10538 gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
10539 break;
10540 case OPC_MOVZ_PS:
10541 check_ps(ctx);
10542 {
10543 TCGLabel *l1 = gen_new_label();
10544 TCGv_i64 fp0;
10545
10546 if (ft != 0) {
10547 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1);
10548 }
10549 fp0 = tcg_temp_new_i64();
10550 gen_load_fpr64(ctx, fp0, fs);
10551 gen_store_fpr64(ctx, fp0, fd);
10552 gen_set_label(l1);
10553 }
10554 break;
10555 case OPC_MOVN_PS:
10556 check_ps(ctx);
10557 {
10558 TCGLabel *l1 = gen_new_label();
10559 TCGv_i64 fp0;
10560
10561 if (ft != 0) {
10562 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1);
10563 fp0 = tcg_temp_new_i64();
10564 gen_load_fpr64(ctx, fp0, fs);
10565 gen_store_fpr64(ctx, fp0, fd);
10566 gen_set_label(l1);
10567 }
10568 }
10569 break;
10570 case OPC_ADDR_PS:
10571 check_ps(ctx);
10572 {
10573 TCGv_i64 fp0 = tcg_temp_new_i64();
10574 TCGv_i64 fp1 = tcg_temp_new_i64();
10575
10576 gen_load_fpr64(ctx, fp0, ft);
10577 gen_load_fpr64(ctx, fp1, fs);
10578 gen_helper_float_addr_ps(fp0, tcg_env, fp0, fp1);
10579 gen_store_fpr64(ctx, fp0, fd);
10580 }
10581 break;
10582 case OPC_MULR_PS:
10583 check_ps(ctx);
10584 {
10585 TCGv_i64 fp0 = tcg_temp_new_i64();
10586 TCGv_i64 fp1 = tcg_temp_new_i64();
10587
10588 gen_load_fpr64(ctx, fp0, ft);
10589 gen_load_fpr64(ctx, fp1, fs);
10590 gen_helper_float_mulr_ps(fp0, tcg_env, fp0, fp1);
10591 gen_store_fpr64(ctx, fp0, fd);
10592 }
10593 break;
10594 case OPC_RECIP2_PS:
10595 check_ps(ctx);
10596 {
10597 TCGv_i64 fp0 = tcg_temp_new_i64();
10598 TCGv_i64 fp1 = tcg_temp_new_i64();
10599
10600 gen_load_fpr64(ctx, fp0, fs);
10601 gen_load_fpr64(ctx, fp1, ft);
10602 gen_helper_float_recip2_ps(fp0, tcg_env, fp0, fp1);
10603 gen_store_fpr64(ctx, fp0, fd);
10604 }
10605 break;
10606 case OPC_RECIP1_PS:
10607 check_ps(ctx);
10608 {
10609 TCGv_i64 fp0 = tcg_temp_new_i64();
10610
10611 gen_load_fpr64(ctx, fp0, fs);
10612 gen_helper_float_recip1_ps(fp0, tcg_env, fp0);
10613 gen_store_fpr64(ctx, fp0, fd);
10614 }
10615 break;
10616 case OPC_RSQRT1_PS:
10617 check_ps(ctx);
10618 {
10619 TCGv_i64 fp0 = tcg_temp_new_i64();
10620
10621 gen_load_fpr64(ctx, fp0, fs);
10622 gen_helper_float_rsqrt1_ps(fp0, tcg_env, fp0);
10623 gen_store_fpr64(ctx, fp0, fd);
10624 }
10625 break;
10626 case OPC_RSQRT2_PS:
10627 check_ps(ctx);
10628 {
10629 TCGv_i64 fp0 = tcg_temp_new_i64();
10630 TCGv_i64 fp1 = tcg_temp_new_i64();
10631
10632 gen_load_fpr64(ctx, fp0, fs);
10633 gen_load_fpr64(ctx, fp1, ft);
10634 gen_helper_float_rsqrt2_ps(fp0, tcg_env, fp0, fp1);
10635 gen_store_fpr64(ctx, fp0, fd);
10636 }
10637 break;
10638 case OPC_CVT_S_PU:
10639 check_cp1_64bitmode(ctx);
10640 {
10641 TCGv_i32 fp0 = tcg_temp_new_i32();
10642
10643 gen_load_fpr32h(ctx, fp0, fs);
10644 gen_helper_float_cvts_pu(fp0, tcg_env, fp0);
10645 gen_store_fpr32(ctx, fp0, fd);
10646 }
10647 break;
10648 case OPC_CVT_PW_PS:
10649 check_ps(ctx);
10650 {
10651 TCGv_i64 fp0 = tcg_temp_new_i64();
10652
10653 gen_load_fpr64(ctx, fp0, fs);
10654 gen_helper_float_cvtpw_ps(fp0, tcg_env, fp0);
10655 gen_store_fpr64(ctx, fp0, fd);
10656 }
10657 break;
10658 case OPC_CVT_S_PL:
10659 check_cp1_64bitmode(ctx);
10660 {
10661 TCGv_i32 fp0 = tcg_temp_new_i32();
10662
10663 gen_load_fpr32(ctx, fp0, fs);
10664 gen_helper_float_cvts_pl(fp0, tcg_env, fp0);
10665 gen_store_fpr32(ctx, fp0, fd);
10666 }
10667 break;
10668 case OPC_PLL_PS:
10669 check_ps(ctx);
10670 {
10671 TCGv_i32 fp0 = tcg_temp_new_i32();
10672 TCGv_i32 fp1 = tcg_temp_new_i32();
10673
10674 gen_load_fpr32(ctx, fp0, fs);
10675 gen_load_fpr32(ctx, fp1, ft);
10676 gen_store_fpr32h(ctx, fp0, fd);
10677 gen_store_fpr32(ctx, fp1, fd);
10678 }
10679 break;
10680 case OPC_PLU_PS:
10681 check_ps(ctx);
10682 {
10683 TCGv_i32 fp0 = tcg_temp_new_i32();
10684 TCGv_i32 fp1 = tcg_temp_new_i32();
10685
10686 gen_load_fpr32(ctx, fp0, fs);
10687 gen_load_fpr32h(ctx, fp1, ft);
10688 gen_store_fpr32(ctx, fp1, fd);
10689 gen_store_fpr32h(ctx, fp0, fd);
10690 }
10691 break;
10692 case OPC_PUL_PS:
10693 check_ps(ctx);
10694 {
10695 TCGv_i32 fp0 = tcg_temp_new_i32();
10696 TCGv_i32 fp1 = tcg_temp_new_i32();
10697
10698 gen_load_fpr32h(ctx, fp0, fs);
10699 gen_load_fpr32(ctx, fp1, ft);
10700 gen_store_fpr32(ctx, fp1, fd);
10701 gen_store_fpr32h(ctx, fp0, fd);
10702 }
10703 break;
10704 case OPC_PUU_PS:
10705 check_ps(ctx);
10706 {
10707 TCGv_i32 fp0 = tcg_temp_new_i32();
10708 TCGv_i32 fp1 = tcg_temp_new_i32();
10709
10710 gen_load_fpr32h(ctx, fp0, fs);
10711 gen_load_fpr32h(ctx, fp1, ft);
10712 gen_store_fpr32(ctx, fp1, fd);
10713 gen_store_fpr32h(ctx, fp0, fd);
10714 }
10715 break;
10716 case OPC_CMP_F_PS:
10717 case OPC_CMP_UN_PS:
10718 case OPC_CMP_EQ_PS:
10719 case OPC_CMP_UEQ_PS:
10720 case OPC_CMP_OLT_PS:
10721 case OPC_CMP_ULT_PS:
10722 case OPC_CMP_OLE_PS:
10723 case OPC_CMP_ULE_PS:
10724 case OPC_CMP_SF_PS:
10725 case OPC_CMP_NGLE_PS:
10726 case OPC_CMP_SEQ_PS:
10727 case OPC_CMP_NGL_PS:
10728 case OPC_CMP_LT_PS:
10729 case OPC_CMP_NGE_PS:
10730 case OPC_CMP_LE_PS:
10731 case OPC_CMP_NGT_PS:
10732 if (ctx->opcode & (1 << 6)) {
10733 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc);
10734 } else {
10735 gen_cmp_ps(ctx, func - 48, ft, fs, cc);
10736 }
10737 break;
10738 default:
10739 MIPS_INVAL("farith");
10740 gen_reserved_instruction(ctx);
10741 return;
10742 }
10743 }
10744
10745 /* Coprocessor 3 (FPU) */
10746 static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
10747 int fd, int fs, int base, int index)
10748 {
10749 TCGv t0 = tcg_temp_new();
10750
10751 if (base == 0) {
10752 gen_load_gpr(t0, index);
10753 } else if (index == 0) {
10754 gen_load_gpr(t0, base);
10755 } else {
10756 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
10757 }
10758 /*
10759 * Don't do NOP if destination is zero: we must perform the actual
10760 * memory access.
10761 */
10762 switch (opc) {
10763 case OPC_LWXC1:
10764 check_cop1x(ctx);
10765 {
10766 TCGv_i32 fp0 = tcg_temp_new_i32();
10767
10768 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
10769 tcg_gen_trunc_tl_i32(fp0, t0);
10770 gen_store_fpr32(ctx, fp0, fd);
10771 }
10772 break;
10773 case OPC_LDXC1:
10774 check_cop1x(ctx);
10775 check_cp1_registers(ctx, fd);
10776 {
10777 TCGv_i64 fp0 = tcg_temp_new_i64();
10778 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
10779 gen_store_fpr64(ctx, fp0, fd);
10780 }
10781 break;
10782 case OPC_LUXC1:
10783 check_cp1_64bitmode(ctx);
10784 tcg_gen_andi_tl(t0, t0, ~0x7);
10785 {
10786 TCGv_i64 fp0 = tcg_temp_new_i64();
10787
10788 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
10789 gen_store_fpr64(ctx, fp0, fd);
10790 }
10791 break;
10792 case OPC_SWXC1:
10793 check_cop1x(ctx);
10794 {
10795 TCGv_i32 fp0 = tcg_temp_new_i32();
10796 gen_load_fpr32(ctx, fp0, fs);
10797 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
10798 }
10799 break;
10800 case OPC_SDXC1:
10801 check_cop1x(ctx);
10802 check_cp1_registers(ctx, fs);
10803 {
10804 TCGv_i64 fp0 = tcg_temp_new_i64();
10805 gen_load_fpr64(ctx, fp0, fs);
10806 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
10807 }
10808 break;
10809 case OPC_SUXC1:
10810 check_cp1_64bitmode(ctx);
10811 tcg_gen_andi_tl(t0, t0, ~0x7);
10812 {
10813 TCGv_i64 fp0 = tcg_temp_new_i64();
10814 gen_load_fpr64(ctx, fp0, fs);
10815 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
10816 }
10817 break;
10818 }
10819 }
10820
10821 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
10822 int fd, int fr, int fs, int ft)
10823 {
10824 switch (opc) {
10825 case OPC_ALNV_PS:
10826 check_ps(ctx);
10827 {
10828 TCGv t0 = tcg_temp_new();
10829 TCGv_i32 fp = tcg_temp_new_i32();
10830 TCGv_i32 fph = tcg_temp_new_i32();
10831 TCGLabel *l1 = gen_new_label();
10832 TCGLabel *l2 = gen_new_label();
10833
10834 gen_load_gpr(t0, fr);
10835 tcg_gen_andi_tl(t0, t0, 0x7);
10836
10837 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1);
10838 gen_load_fpr32(ctx, fp, fs);
10839 gen_load_fpr32h(ctx, fph, fs);
10840 gen_store_fpr32(ctx, fp, fd);
10841 gen_store_fpr32h(ctx, fph, fd);
10842 tcg_gen_br(l2);
10843 gen_set_label(l1);
10844 tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
10845 if (disas_is_bigendian(ctx)) {
10846 gen_load_fpr32(ctx, fp, fs);
10847 gen_load_fpr32h(ctx, fph, ft);
10848 gen_store_fpr32h(ctx, fp, fd);
10849 gen_store_fpr32(ctx, fph, fd);
10850 } else {
10851 gen_load_fpr32h(ctx, fph, fs);
10852 gen_load_fpr32(ctx, fp, ft);
10853 gen_store_fpr32(ctx, fph, fd);
10854 gen_store_fpr32h(ctx, fp, fd);
10855 }
10856 gen_set_label(l2);
10857 }
10858 break;
10859 case OPC_MADD_S:
10860 check_cop1x(ctx);
10861 {
10862 TCGv_i32 fp0 = tcg_temp_new_i32();
10863 TCGv_i32 fp1 = tcg_temp_new_i32();
10864 TCGv_i32 fp2 = tcg_temp_new_i32();
10865
10866 gen_load_fpr32(ctx, fp0, fs);
10867 gen_load_fpr32(ctx, fp1, ft);
10868 gen_load_fpr32(ctx, fp2, fr);
10869 gen_helper_float_madd_s(fp2, tcg_env, fp0, fp1, fp2);
10870 gen_store_fpr32(ctx, fp2, fd);
10871 }
10872 break;
10873 case OPC_MADD_D:
10874 check_cop1x(ctx);
10875 check_cp1_registers(ctx, fd | fs | ft | fr);
10876 {
10877 TCGv_i64 fp0 = tcg_temp_new_i64();
10878 TCGv_i64 fp1 = tcg_temp_new_i64();
10879 TCGv_i64 fp2 = tcg_temp_new_i64();
10880
10881 gen_load_fpr64(ctx, fp0, fs);
10882 gen_load_fpr64(ctx, fp1, ft);
10883 gen_load_fpr64(ctx, fp2, fr);
10884 gen_helper_float_madd_d(fp2, tcg_env, fp0, fp1, fp2);
10885 gen_store_fpr64(ctx, fp2, fd);
10886 }
10887 break;
10888 case OPC_MADD_PS:
10889 check_ps(ctx);
10890 {
10891 TCGv_i64 fp0 = tcg_temp_new_i64();
10892 TCGv_i64 fp1 = tcg_temp_new_i64();
10893 TCGv_i64 fp2 = tcg_temp_new_i64();
10894
10895 gen_load_fpr64(ctx, fp0, fs);
10896 gen_load_fpr64(ctx, fp1, ft);
10897 gen_load_fpr64(ctx, fp2, fr);
10898 gen_helper_float_madd_ps(fp2, tcg_env, fp0, fp1, fp2);
10899 gen_store_fpr64(ctx, fp2, fd);
10900 }
10901 break;
10902 case OPC_MSUB_S:
10903 check_cop1x(ctx);
10904 {
10905 TCGv_i32 fp0 = tcg_temp_new_i32();
10906 TCGv_i32 fp1 = tcg_temp_new_i32();
10907 TCGv_i32 fp2 = tcg_temp_new_i32();
10908
10909 gen_load_fpr32(ctx, fp0, fs);
10910 gen_load_fpr32(ctx, fp1, ft);
10911 gen_load_fpr32(ctx, fp2, fr);
10912 gen_helper_float_msub_s(fp2, tcg_env, fp0, fp1, fp2);
10913 gen_store_fpr32(ctx, fp2, fd);
10914 }
10915 break;
10916 case OPC_MSUB_D:
10917 check_cop1x(ctx);
10918 check_cp1_registers(ctx, fd | fs | ft | fr);
10919 {
10920 TCGv_i64 fp0 = tcg_temp_new_i64();
10921 TCGv_i64 fp1 = tcg_temp_new_i64();
10922 TCGv_i64 fp2 = tcg_temp_new_i64();
10923
10924 gen_load_fpr64(ctx, fp0, fs);
10925 gen_load_fpr64(ctx, fp1, ft);
10926 gen_load_fpr64(ctx, fp2, fr);
10927 gen_helper_float_msub_d(fp2, tcg_env, fp0, fp1, fp2);
10928 gen_store_fpr64(ctx, fp2, fd);
10929 }
10930 break;
10931 case OPC_MSUB_PS:
10932 check_ps(ctx);
10933 {
10934 TCGv_i64 fp0 = tcg_temp_new_i64();
10935 TCGv_i64 fp1 = tcg_temp_new_i64();
10936 TCGv_i64 fp2 = tcg_temp_new_i64();
10937
10938 gen_load_fpr64(ctx, fp0, fs);
10939 gen_load_fpr64(ctx, fp1, ft);
10940 gen_load_fpr64(ctx, fp2, fr);
10941 gen_helper_float_msub_ps(fp2, tcg_env, fp0, fp1, fp2);
10942 gen_store_fpr64(ctx, fp2, fd);
10943 }
10944 break;
10945 case OPC_NMADD_S:
10946 check_cop1x(ctx);
10947 {
10948 TCGv_i32 fp0 = tcg_temp_new_i32();
10949 TCGv_i32 fp1 = tcg_temp_new_i32();
10950 TCGv_i32 fp2 = tcg_temp_new_i32();
10951
10952 gen_load_fpr32(ctx, fp0, fs);
10953 gen_load_fpr32(ctx, fp1, ft);
10954 gen_load_fpr32(ctx, fp2, fr);
10955 gen_helper_float_nmadd_s(fp2, tcg_env, fp0, fp1, fp2);
10956 gen_store_fpr32(ctx, fp2, fd);
10957 }
10958 break;
10959 case OPC_NMADD_D:
10960 check_cop1x(ctx);
10961 check_cp1_registers(ctx, fd | fs | ft | fr);
10962 {
10963 TCGv_i64 fp0 = tcg_temp_new_i64();
10964 TCGv_i64 fp1 = tcg_temp_new_i64();
10965 TCGv_i64 fp2 = tcg_temp_new_i64();
10966
10967 gen_load_fpr64(ctx, fp0, fs);
10968 gen_load_fpr64(ctx, fp1, ft);
10969 gen_load_fpr64(ctx, fp2, fr);
10970 gen_helper_float_nmadd_d(fp2, tcg_env, fp0, fp1, fp2);
10971 gen_store_fpr64(ctx, fp2, fd);
10972 }
10973 break;
10974 case OPC_NMADD_PS:
10975 check_ps(ctx);
10976 {
10977 TCGv_i64 fp0 = tcg_temp_new_i64();
10978 TCGv_i64 fp1 = tcg_temp_new_i64();
10979 TCGv_i64 fp2 = tcg_temp_new_i64();
10980
10981 gen_load_fpr64(ctx, fp0, fs);
10982 gen_load_fpr64(ctx, fp1, ft);
10983 gen_load_fpr64(ctx, fp2, fr);
10984 gen_helper_float_nmadd_ps(fp2, tcg_env, fp0, fp1, fp2);
10985 gen_store_fpr64(ctx, fp2, fd);
10986 }
10987 break;
10988 case OPC_NMSUB_S:
10989 check_cop1x(ctx);
10990 {
10991 TCGv_i32 fp0 = tcg_temp_new_i32();
10992 TCGv_i32 fp1 = tcg_temp_new_i32();
10993 TCGv_i32 fp2 = tcg_temp_new_i32();
10994
10995 gen_load_fpr32(ctx, fp0, fs);
10996 gen_load_fpr32(ctx, fp1, ft);
10997 gen_load_fpr32(ctx, fp2, fr);
10998 gen_helper_float_nmsub_s(fp2, tcg_env, fp0, fp1, fp2);
10999 gen_store_fpr32(ctx, fp2, fd);
11000 }
11001 break;
11002 case OPC_NMSUB_D:
11003 check_cop1x(ctx);
11004 check_cp1_registers(ctx, fd | fs | ft | fr);
11005 {
11006 TCGv_i64 fp0 = tcg_temp_new_i64();
11007 TCGv_i64 fp1 = tcg_temp_new_i64();
11008 TCGv_i64 fp2 = tcg_temp_new_i64();
11009
11010 gen_load_fpr64(ctx, fp0, fs);
11011 gen_load_fpr64(ctx, fp1, ft);
11012 gen_load_fpr64(ctx, fp2, fr);
11013 gen_helper_float_nmsub_d(fp2, tcg_env, fp0, fp1, fp2);
11014 gen_store_fpr64(ctx, fp2, fd);
11015 }
11016 break;
11017 case OPC_NMSUB_PS:
11018 check_ps(ctx);
11019 {
11020 TCGv_i64 fp0 = tcg_temp_new_i64();
11021 TCGv_i64 fp1 = tcg_temp_new_i64();
11022 TCGv_i64 fp2 = tcg_temp_new_i64();
11023
11024 gen_load_fpr64(ctx, fp0, fs);
11025 gen_load_fpr64(ctx, fp1, ft);
11026 gen_load_fpr64(ctx, fp2, fr);
11027 gen_helper_float_nmsub_ps(fp2, tcg_env, fp0, fp1, fp2);
11028 gen_store_fpr64(ctx, fp2, fd);
11029 }
11030 break;
11031 default:
11032 MIPS_INVAL("flt3_arith");
11033 gen_reserved_instruction(ctx);
11034 return;
11035 }
11036 }
11037
11038 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
11039 {
11040 TCGv t0;
11041
11042 #if !defined(CONFIG_USER_ONLY)
11043 /*
11044 * The Linux kernel will emulate rdhwr if it's not supported natively.
11045 * Therefore only check the ISA in system mode.
11046 */
11047 check_insn(ctx, ISA_MIPS_R2);
11048 #endif
11049 t0 = tcg_temp_new();
11050
11051 switch (rd) {
11052 case 0:
11053 gen_helper_rdhwr_cpunum(t0, tcg_env);
11054 gen_store_gpr(t0, rt);
11055 break;
11056 case 1:
11057 gen_helper_rdhwr_synci_step(t0, tcg_env);
11058 gen_store_gpr(t0, rt);
11059 break;
11060 case 2:
11061 translator_io_start(&ctx->base);
11062 gen_helper_rdhwr_cc(t0, tcg_env);
11063 gen_store_gpr(t0, rt);
11064 /*
11065 * Break the TB to be able to take timer interrupts immediately
11066 * after reading count. DISAS_STOP isn't sufficient, we need to ensure
11067 * we break completely out of translated code.
11068 */
11069 gen_save_pc(ctx->base.pc_next + 4);
11070 ctx->base.is_jmp = DISAS_EXIT;
11071 break;
11072 case 3:
11073 gen_helper_rdhwr_ccres(t0, tcg_env);
11074 gen_store_gpr(t0, rt);
11075 break;
11076 case 4:
11077 check_insn(ctx, ISA_MIPS_R6);
11078 if (sel != 0) {
11079 /*
11080 * Performance counter registers are not implemented other than
11081 * control register 0.
11082 */
11083 generate_exception(ctx, EXCP_RI);
11084 }
11085 gen_helper_rdhwr_performance(t0, tcg_env);
11086 gen_store_gpr(t0, rt);
11087 break;
11088 case 5:
11089 check_insn(ctx, ISA_MIPS_R6);
11090 gen_helper_rdhwr_xnp(t0, tcg_env);
11091 gen_store_gpr(t0, rt);
11092 break;
11093 case 29:
11094 #if defined(CONFIG_USER_ONLY)
11095 tcg_gen_ld_tl(t0, tcg_env,
11096 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
11097 gen_store_gpr(t0, rt);
11098 break;
11099 #else
11100 if ((ctx->hflags & MIPS_HFLAG_CP0) ||
11101 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
11102 tcg_gen_ld_tl(t0, tcg_env,
11103 offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
11104 gen_store_gpr(t0, rt);
11105 } else {
11106 gen_reserved_instruction(ctx);
11107 }
11108 break;
11109 #endif
11110 default: /* Invalid */
11111 MIPS_INVAL("rdhwr");
11112 gen_reserved_instruction(ctx);
11113 break;
11114 }
11115 }
11116
11117 static inline void clear_branch_hflags(DisasContext *ctx)
11118 {
11119 ctx->hflags &= ~MIPS_HFLAG_BMASK;
11120 if (ctx->base.is_jmp == DISAS_NEXT) {
11121 save_cpu_state(ctx, 0);
11122 } else {
11123 /*
11124 * It is not safe to save ctx->hflags as hflags may be changed
11125 * in execution time by the instruction in delay / forbidden slot.
11126 */
11127 tcg_gen_andi_i32(hflags, hflags, ~MIPS_HFLAG_BMASK);
11128 }
11129 }
11130
11131 static void gen_branch(DisasContext *ctx, int insn_bytes)
11132 {
11133 if (ctx->hflags & MIPS_HFLAG_BMASK) {
11134 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
11135 /* Branches completion */
11136 clear_branch_hflags(ctx);
11137 ctx->base.is_jmp = DISAS_NORETURN;
11138 switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) {
11139 case MIPS_HFLAG_FBNSLOT:
11140 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes);
11141 break;
11142 case MIPS_HFLAG_B:
11143 /* unconditional branch */
11144 if (proc_hflags & MIPS_HFLAG_BX) {
11145 tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16);
11146 }
11147 gen_goto_tb(ctx, 0, ctx->btarget);
11148 break;
11149 case MIPS_HFLAG_BL:
11150 /* blikely taken case */
11151 gen_goto_tb(ctx, 0, ctx->btarget);
11152 break;
11153 case MIPS_HFLAG_BC:
11154 /* Conditional branch */
11155 {
11156 TCGLabel *l1 = gen_new_label();
11157
11158 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
11159 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes);
11160 gen_set_label(l1);
11161 gen_goto_tb(ctx, 0, ctx->btarget);
11162 }
11163 break;
11164 case MIPS_HFLAG_BR:
11165 /* unconditional branch to register */
11166 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
11167 TCGv t0 = tcg_temp_new();
11168 TCGv_i32 t1 = tcg_temp_new_i32();
11169
11170 tcg_gen_andi_tl(t0, btarget, 0x1);
11171 tcg_gen_trunc_tl_i32(t1, t0);
11172 tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16);
11173 tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT);
11174 tcg_gen_or_i32(hflags, hflags, t1);
11175
11176 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1);
11177 } else {
11178 tcg_gen_mov_tl(cpu_PC, btarget);
11179 }
11180 tcg_gen_lookup_and_goto_ptr();
11181 break;
11182 default:
11183 LOG_DISAS("unknown branch 0x%x\n", proc_hflags);
11184 gen_reserved_instruction(ctx);
11185 }
11186 }
11187 }
11188
11189 /* Compact Branches */
11190 static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
11191 int rs, int rt, int32_t offset)
11192 {
11193 int bcond_compute = 0;
11194 TCGv t0 = tcg_temp_new();
11195 TCGv t1 = tcg_temp_new();
11196 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
11197
11198 if (ctx->hflags & MIPS_HFLAG_BMASK) {
11199 #ifdef MIPS_DEBUG_DISAS
11200 LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
11201 VADDR_PRIx "\n", ctx->base.pc_next);
11202 #endif
11203 gen_reserved_instruction(ctx);
11204 return;
11205 }
11206
11207 /* Load needed operands and calculate btarget */
11208 switch (opc) {
11209 /* compact branch */
11210 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
11211 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
11212 gen_load_gpr(t0, rs);
11213 gen_load_gpr(t1, rt);
11214 bcond_compute = 1;
11215 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11216 if (rs <= rt && rs == 0) {
11217 /* OPC_BEQZALC, OPC_BNEZALC */
11218 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11219 }
11220 break;
11221 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
11222 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
11223 gen_load_gpr(t0, rs);
11224 gen_load_gpr(t1, rt);
11225 bcond_compute = 1;
11226 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11227 break;
11228 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
11229 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
11230 if (rs == 0 || rs == rt) {
11231 /* OPC_BLEZALC, OPC_BGEZALC */
11232 /* OPC_BGTZALC, OPC_BLTZALC */
11233 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11234 }
11235 gen_load_gpr(t0, rs);
11236 gen_load_gpr(t1, rt);
11237 bcond_compute = 1;
11238 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11239 break;
11240 case OPC_BC:
11241 case OPC_BALC:
11242 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11243 break;
11244 case OPC_BEQZC:
11245 case OPC_BNEZC:
11246 if (rs != 0) {
11247 /* OPC_BEQZC, OPC_BNEZC */
11248 gen_load_gpr(t0, rs);
11249 bcond_compute = 1;
11250 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
11251 } else {
11252 /* OPC_JIC, OPC_JIALC */
11253 TCGv tbase = tcg_temp_new();
11254
11255 gen_load_gpr(tbase, rt);
11256 gen_op_addr_addi(ctx, btarget, tbase, offset);
11257 }
11258 break;
11259 default:
11260 MIPS_INVAL("Compact branch/jump");
11261 gen_reserved_instruction(ctx);
11262 return;
11263 }
11264
11265 if (bcond_compute == 0) {
11266 /* Unconditional compact branch */
11267 switch (opc) {
11268 case OPC_JIALC:
11269 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11270 /* Fallthrough */
11271 case OPC_JIC:
11272 ctx->hflags |= MIPS_HFLAG_BR;
11273 break;
11274 case OPC_BALC:
11275 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit);
11276 /* Fallthrough */
11277 case OPC_BC:
11278 ctx->hflags |= MIPS_HFLAG_B;
11279 break;
11280 default:
11281 MIPS_INVAL("Compact branch/jump");
11282 gen_reserved_instruction(ctx);
11283 return;
11284 }
11285
11286 /* Generating branch here as compact branches don't have delay slot */
11287 gen_branch(ctx, 4);
11288 } else {
11289 /* Conditional compact branch */
11290 TCGLabel *fs = gen_new_label();
11291 save_cpu_state(ctx, 0);
11292
11293 switch (opc) {
11294 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC */
11295 if (rs == 0 && rt != 0) {
11296 /* OPC_BLEZALC */
11297 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
11298 } else if (rs != 0 && rt != 0 && rs == rt) {
11299 /* OPC_BGEZALC */
11300 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
11301 } else {
11302 /* OPC_BGEUC */
11303 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
11304 }
11305 break;
11306 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC */
11307 if (rs == 0 && rt != 0) {
11308 /* OPC_BGTZALC */
11309 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
11310 } else if (rs != 0 && rt != 0 && rs == rt) {
11311 /* OPC_BLTZALC */
11312 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
11313 } else {
11314 /* OPC_BLTUC */
11315 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
11316 }
11317 break;
11318 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC */
11319 if (rs == 0 && rt != 0) {
11320 /* OPC_BLEZC */
11321 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LE), t1, 0, fs);
11322 } else if (rs != 0 && rt != 0 && rs == rt) {
11323 /* OPC_BGEZC */
11324 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GE), t1, 0, fs);
11325 } else {
11326 /* OPC_BGEC */
11327 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
11328 }
11329 break;
11330 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC */
11331 if (rs == 0 && rt != 0) {
11332 /* OPC_BGTZC */
11333 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_GT), t1, 0, fs);
11334 } else if (rs != 0 && rt != 0 && rs == rt) {
11335 /* OPC_BLTZC */
11336 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_LT), t1, 0, fs);
11337 } else {
11338 /* OPC_BLTC */
11339 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
11340 }
11341 break;
11342 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC */
11343 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
11344 if (rs >= rt) {
11345 /* OPC_BOVC, OPC_BNVC */
11346 TCGv t2 = tcg_temp_new();
11347 TCGv t3 = tcg_temp_new();
11348 TCGv t4 = tcg_temp_new();
11349 TCGv input_overflow = tcg_temp_new();
11350
11351 gen_load_gpr(t0, rs);
11352 gen_load_gpr(t1, rt);
11353 tcg_gen_ext32s_tl(t2, t0);
11354 tcg_gen_setcond_tl(TCG_COND_NE, input_overflow, t2, t0);
11355 tcg_gen_ext32s_tl(t3, t1);
11356 tcg_gen_setcond_tl(TCG_COND_NE, t4, t3, t1);
11357 tcg_gen_or_tl(input_overflow, input_overflow, t4);
11358
11359 tcg_gen_add_tl(t4, t2, t3);
11360 tcg_gen_ext32s_tl(t4, t4);
11361 tcg_gen_xor_tl(t2, t2, t3);
11362 tcg_gen_xor_tl(t3, t4, t3);
11363 tcg_gen_andc_tl(t2, t3, t2);
11364 tcg_gen_setcondi_tl(TCG_COND_LT, t4, t2, 0);
11365 tcg_gen_or_tl(t4, t4, input_overflow);
11366 if (opc == OPC_BOVC) {
11367 /* OPC_BOVC */
11368 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t4, 0, fs);
11369 } else {
11370 /* OPC_BNVC */
11371 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0, fs);
11372 }
11373 } else if (rs < rt && rs == 0) {
11374 /* OPC_BEQZALC, OPC_BNEZALC */
11375 if (opc == OPC_BEQZALC) {
11376 /* OPC_BEQZALC */
11377 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t1, 0, fs);
11378 } else {
11379 /* OPC_BNEZALC */
11380 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t1, 0, fs);
11381 }
11382 } else {
11383 /* OPC_BEQC, OPC_BNEC */
11384 if (opc == OPC_BEQC) {
11385 /* OPC_BEQC */
11386 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
11387 } else {
11388 /* OPC_BNEC */
11389 tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
11390 }
11391 }
11392 break;
11393 case OPC_BEQZC:
11394 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t0, 0, fs);
11395 break;
11396 case OPC_BNEZC:
11397 tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_NE), t0, 0, fs);
11398 break;
11399 default:
11400 MIPS_INVAL("Compact conditional branch/jump");
11401 gen_reserved_instruction(ctx);
11402 return;
11403 }
11404
11405 /* Generating branch here as compact branches don't have delay slot */
11406 gen_goto_tb(ctx, 1, ctx->btarget);
11407 gen_set_label(fs);
11408
11409 ctx->hflags |= MIPS_HFLAG_FBNSLOT;
11410 }
11411 }
11412
11413 void gen_addiupc(DisasContext *ctx, int rx, int imm,
11414 int is_64_bit, int extended)
11415 {
11416 target_ulong npc;
11417
11418 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
11419 gen_reserved_instruction(ctx);
11420 return;
11421 }
11422
11423 npc = pc_relative_pc(ctx) + imm;
11424 if (!is_64_bit) {
11425 npc = (int32_t)npc;
11426 }
11427 tcg_gen_movi_tl(cpu_gpr[rx], npc);
11428 }
11429
11430 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
11431 int16_t offset)
11432 {
11433 TCGv_i32 t0 = tcg_constant_i32(op);
11434 TCGv t1 = tcg_temp_new();
11435 gen_base_offset_addr(ctx, t1, base, offset);
11436 gen_helper_cache(tcg_env, t1, t0);
11437 }
11438
11439 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code)
11440 {
11441 #ifdef CONFIG_USER_ONLY
11442 return false;
11443 #else
11444 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM;
11445 return semihosting_enabled(is_user) && sdbbp_code == 1;
11446 #endif
11447 }
11448
11449 void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
11450 {
11451 TCGv t0 = tcg_temp_new();
11452 TCGv t1 = tcg_temp_new();
11453
11454 gen_load_gpr(t0, base);
11455
11456 if (index != 0) {
11457 gen_load_gpr(t1, index);
11458 tcg_gen_shli_tl(t1, t1, 2);
11459 gen_op_addr_add(ctx, t0, t1, t0);
11460 }
11461
11462 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
11463 gen_store_gpr(t1, rd);
11464 }
11465
11466 static void gen_sync(int stype)
11467 {
11468 TCGBar tcg_mo = TCG_BAR_SC;
11469
11470 switch (stype) {
11471 case 0x4: /* SYNC_WMB */
11472 tcg_mo |= TCG_MO_ST_ST;
11473 break;
11474 case 0x10: /* SYNC_MB */
11475 tcg_mo |= TCG_MO_ALL;
11476 break;
11477 case 0x11: /* SYNC_ACQUIRE */
11478 tcg_mo |= TCG_MO_LD_LD | TCG_MO_LD_ST;
11479 break;
11480 case 0x12: /* SYNC_RELEASE */
11481 tcg_mo |= TCG_MO_ST_ST | TCG_MO_LD_ST;
11482 break;
11483 case 0x13: /* SYNC_RMB */
11484 tcg_mo |= TCG_MO_LD_LD;
11485 break;
11486 default:
11487 tcg_mo |= TCG_MO_ALL;
11488 break;
11489 }
11490
11491 tcg_gen_mb(tcg_mo);
11492 }
11493
11494 /* ISA extensions (ASEs) */
11495
11496 /* MIPS16 extension to MIPS32 */
11497 #include "mips16e_translate.c.inc"
11498
11499 /* microMIPS extension to MIPS32/MIPS64 */
11500
11501 /*
11502 * Values for microMIPS fmt field. Variable-width, depending on which
11503 * formats the instruction supports.
11504 */
11505 enum {
11506 FMT_SD_S = 0,
11507 FMT_SD_D = 1,
11508
11509 FMT_SDPS_S = 0,
11510 FMT_SDPS_D = 1,
11511 FMT_SDPS_PS = 2,
11512
11513 FMT_SWL_S = 0,
11514 FMT_SWL_W = 1,
11515 FMT_SWL_L = 2,
11516
11517 FMT_DWL_D = 0,
11518 FMT_DWL_W = 1,
11519 FMT_DWL_L = 2
11520 };
11521
11522 #include "micromips_translate.c.inc"
11523
11524 #include "nanomips_translate.c.inc"
11525
11526 /* MIPSDSP functions. */
11527
11528 /* Indexed load is not for DSP only */
11529 static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
11530 int rd, int base, int offset)
11531 {
11532 TCGv t0;
11533
11534 if (!(ctx->insn_flags & INSN_OCTEON)) {
11535 check_dsp(ctx);
11536 }
11537 t0 = tcg_temp_new();
11538
11539 if (base == 0) {
11540 gen_load_gpr(t0, offset);
11541 } else if (offset == 0) {
11542 gen_load_gpr(t0, base);
11543 } else {
11544 gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]);
11545 }
11546
11547 switch (opc) {
11548 case OPC_LBUX:
11549 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
11550 gen_store_gpr(t0, rd);
11551 break;
11552 case OPC_LHX:
11553 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
11554 gen_store_gpr(t0, rd);
11555 break;
11556 case OPC_LWX:
11557 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
11558 gen_store_gpr(t0, rd);
11559 break;
11560 #if defined(TARGET_MIPS64)
11561 case OPC_LDX:
11562 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
11563 gen_store_gpr(t0, rd);
11564 break;
11565 #endif
11566 }
11567 }
11568
11569 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
11570 int ret, int v1, int v2)
11571 {
11572 TCGv v1_t;
11573 TCGv v2_t;
11574
11575 if (ret == 0) {
11576 /* Treat as NOP. */
11577 return;
11578 }
11579
11580 v1_t = tcg_temp_new();
11581 v2_t = tcg_temp_new();
11582
11583 gen_load_gpr(v1_t, v1);
11584 gen_load_gpr(v2_t, v2);
11585
11586 switch (op1) {
11587 /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
11588 case OPC_MULT_G_2E:
11589 check_dsp_r2(ctx);
11590 switch (op2) {
11591 case OPC_ADDUH_QB:
11592 gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
11593 break;
11594 case OPC_ADDUH_R_QB:
11595 gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
11596 break;
11597 case OPC_ADDQH_PH:
11598 gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
11599 break;
11600 case OPC_ADDQH_R_PH:
11601 gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
11602 break;
11603 case OPC_ADDQH_W:
11604 gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
11605 break;
11606 case OPC_ADDQH_R_W:
11607 gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
11608 break;
11609 case OPC_SUBUH_QB:
11610 gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
11611 break;
11612 case OPC_SUBUH_R_QB:
11613 gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
11614 break;
11615 case OPC_SUBQH_PH:
11616 gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
11617 break;
11618 case OPC_SUBQH_R_PH:
11619 gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
11620 break;
11621 case OPC_SUBQH_W:
11622 gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
11623 break;
11624 case OPC_SUBQH_R_W:
11625 gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
11626 break;
11627 }
11628 break;
11629 case OPC_ABSQ_S_PH_DSP:
11630 switch (op2) {
11631 case OPC_ABSQ_S_QB:
11632 check_dsp_r2(ctx);
11633 gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, tcg_env);
11634 break;
11635 case OPC_ABSQ_S_PH:
11636 check_dsp(ctx);
11637 gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, tcg_env);
11638 break;
11639 case OPC_ABSQ_S_W:
11640 check_dsp(ctx);
11641 gen_helper_absq_s_w(cpu_gpr[ret], v2_t, tcg_env);
11642 break;
11643 case OPC_PRECEQ_W_PHL:
11644 check_dsp(ctx);
11645 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000);
11646 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
11647 break;
11648 case OPC_PRECEQ_W_PHR:
11649 check_dsp(ctx);
11650 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF);
11651 tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16);
11652 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
11653 break;
11654 case OPC_PRECEQU_PH_QBL:
11655 check_dsp(ctx);
11656 gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t);
11657 break;
11658 case OPC_PRECEQU_PH_QBR:
11659 check_dsp(ctx);
11660 gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t);
11661 break;
11662 case OPC_PRECEQU_PH_QBLA:
11663 check_dsp(ctx);
11664 gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t);
11665 break;
11666 case OPC_PRECEQU_PH_QBRA:
11667 check_dsp(ctx);
11668 gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t);
11669 break;
11670 case OPC_PRECEU_PH_QBL:
11671 check_dsp(ctx);
11672 gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t);
11673 break;
11674 case OPC_PRECEU_PH_QBR:
11675 check_dsp(ctx);
11676 gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t);
11677 break;
11678 case OPC_PRECEU_PH_QBLA:
11679 check_dsp(ctx);
11680 gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t);
11681 break;
11682 case OPC_PRECEU_PH_QBRA:
11683 check_dsp(ctx);
11684 gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t);
11685 break;
11686 }
11687 break;
11688 case OPC_ADDU_QB_DSP:
11689 switch (op2) {
11690 case OPC_ADDQ_PH:
11691 check_dsp(ctx);
11692 gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11693 break;
11694 case OPC_ADDQ_S_PH:
11695 check_dsp(ctx);
11696 gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11697 break;
11698 case OPC_ADDQ_S_W:
11699 check_dsp(ctx);
11700 gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11701 break;
11702 case OPC_ADDU_QB:
11703 check_dsp(ctx);
11704 gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11705 break;
11706 case OPC_ADDU_S_QB:
11707 check_dsp(ctx);
11708 gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11709 break;
11710 case OPC_ADDU_PH:
11711 check_dsp_r2(ctx);
11712 gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11713 break;
11714 case OPC_ADDU_S_PH:
11715 check_dsp_r2(ctx);
11716 gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11717 break;
11718 case OPC_SUBQ_PH:
11719 check_dsp(ctx);
11720 gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11721 break;
11722 case OPC_SUBQ_S_PH:
11723 check_dsp(ctx);
11724 gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11725 break;
11726 case OPC_SUBQ_S_W:
11727 check_dsp(ctx);
11728 gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11729 break;
11730 case OPC_SUBU_QB:
11731 check_dsp(ctx);
11732 gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11733 break;
11734 case OPC_SUBU_S_QB:
11735 check_dsp(ctx);
11736 gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11737 break;
11738 case OPC_SUBU_PH:
11739 check_dsp_r2(ctx);
11740 gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11741 break;
11742 case OPC_SUBU_S_PH:
11743 check_dsp_r2(ctx);
11744 gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11745 break;
11746 case OPC_ADDSC:
11747 check_dsp(ctx);
11748 gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11749 break;
11750 case OPC_ADDWC:
11751 check_dsp(ctx);
11752 gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11753 break;
11754 case OPC_MODSUB:
11755 check_dsp(ctx);
11756 gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
11757 break;
11758 case OPC_RADDU_W_QB:
11759 check_dsp(ctx);
11760 gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
11761 break;
11762 }
11763 break;
11764 case OPC_CMPU_EQ_QB_DSP:
11765 switch (op2) {
11766 case OPC_PRECR_QB_PH:
11767 check_dsp_r2(ctx);
11768 gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
11769 break;
11770 case OPC_PRECRQ_QB_PH:
11771 check_dsp(ctx);
11772 gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
11773 break;
11774 case OPC_PRECR_SRA_PH_W:
11775 check_dsp_r2(ctx);
11776 {
11777 TCGv_i32 sa_t = tcg_constant_i32(v2);
11778 gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
11779 cpu_gpr[ret]);
11780 break;
11781 }
11782 case OPC_PRECR_SRA_R_PH_W:
11783 check_dsp_r2(ctx);
11784 {
11785 TCGv_i32 sa_t = tcg_constant_i32(v2);
11786 gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
11787 cpu_gpr[ret]);
11788 break;
11789 }
11790 case OPC_PRECRQ_PH_W:
11791 check_dsp(ctx);
11792 gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
11793 break;
11794 case OPC_PRECRQ_RS_PH_W:
11795 check_dsp(ctx);
11796 gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11797 break;
11798 case OPC_PRECRQU_S_QB_PH:
11799 check_dsp(ctx);
11800 gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11801 break;
11802 }
11803 break;
11804 #ifdef TARGET_MIPS64
11805 case OPC_ABSQ_S_QH_DSP:
11806 switch (op2) {
11807 case OPC_PRECEQ_L_PWL:
11808 check_dsp(ctx);
11809 tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull);
11810 break;
11811 case OPC_PRECEQ_L_PWR:
11812 check_dsp(ctx);
11813 tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32);
11814 break;
11815 case OPC_PRECEQ_PW_QHL:
11816 check_dsp(ctx);
11817 gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t);
11818 break;
11819 case OPC_PRECEQ_PW_QHR:
11820 check_dsp(ctx);
11821 gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t);
11822 break;
11823 case OPC_PRECEQ_PW_QHLA:
11824 check_dsp(ctx);
11825 gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t);
11826 break;
11827 case OPC_PRECEQ_PW_QHRA:
11828 check_dsp(ctx);
11829 gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t);
11830 break;
11831 case OPC_PRECEQU_QH_OBL:
11832 check_dsp(ctx);
11833 gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t);
11834 break;
11835 case OPC_PRECEQU_QH_OBR:
11836 check_dsp(ctx);
11837 gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t);
11838 break;
11839 case OPC_PRECEQU_QH_OBLA:
11840 check_dsp(ctx);
11841 gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t);
11842 break;
11843 case OPC_PRECEQU_QH_OBRA:
11844 check_dsp(ctx);
11845 gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t);
11846 break;
11847 case OPC_PRECEU_QH_OBL:
11848 check_dsp(ctx);
11849 gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t);
11850 break;
11851 case OPC_PRECEU_QH_OBR:
11852 check_dsp(ctx);
11853 gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t);
11854 break;
11855 case OPC_PRECEU_QH_OBLA:
11856 check_dsp(ctx);
11857 gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t);
11858 break;
11859 case OPC_PRECEU_QH_OBRA:
11860 check_dsp(ctx);
11861 gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
11862 break;
11863 case OPC_ABSQ_S_OB:
11864 check_dsp_r2(ctx);
11865 gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, tcg_env);
11866 break;
11867 case OPC_ABSQ_S_PW:
11868 check_dsp(ctx);
11869 gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, tcg_env);
11870 break;
11871 case OPC_ABSQ_S_QH:
11872 check_dsp(ctx);
11873 gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, tcg_env);
11874 break;
11875 }
11876 break;
11877 case OPC_ADDU_OB_DSP:
11878 switch (op2) {
11879 case OPC_RADDU_L_OB:
11880 check_dsp(ctx);
11881 gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t);
11882 break;
11883 case OPC_SUBQ_PW:
11884 check_dsp(ctx);
11885 gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11886 break;
11887 case OPC_SUBQ_S_PW:
11888 check_dsp(ctx);
11889 gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11890 break;
11891 case OPC_SUBQ_QH:
11892 check_dsp(ctx);
11893 gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11894 break;
11895 case OPC_SUBQ_S_QH:
11896 check_dsp(ctx);
11897 gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11898 break;
11899 case OPC_SUBU_OB:
11900 check_dsp(ctx);
11901 gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11902 break;
11903 case OPC_SUBU_S_OB:
11904 check_dsp(ctx);
11905 gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11906 break;
11907 case OPC_SUBU_QH:
11908 check_dsp_r2(ctx);
11909 gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11910 break;
11911 case OPC_SUBU_S_QH:
11912 check_dsp_r2(ctx);
11913 gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11914 break;
11915 case OPC_SUBUH_OB:
11916 check_dsp_r2(ctx);
11917 gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
11918 break;
11919 case OPC_SUBUH_R_OB:
11920 check_dsp_r2(ctx);
11921 gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
11922 break;
11923 case OPC_ADDQ_PW:
11924 check_dsp(ctx);
11925 gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11926 break;
11927 case OPC_ADDQ_S_PW:
11928 check_dsp(ctx);
11929 gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11930 break;
11931 case OPC_ADDQ_QH:
11932 check_dsp(ctx);
11933 gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11934 break;
11935 case OPC_ADDQ_S_QH:
11936 check_dsp(ctx);
11937 gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11938 break;
11939 case OPC_ADDU_OB:
11940 check_dsp(ctx);
11941 gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11942 break;
11943 case OPC_ADDU_S_OB:
11944 check_dsp(ctx);
11945 gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11946 break;
11947 case OPC_ADDU_QH:
11948 check_dsp_r2(ctx);
11949 gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11950 break;
11951 case OPC_ADDU_S_QH:
11952 check_dsp_r2(ctx);
11953 gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
11954 break;
11955 case OPC_ADDUH_OB:
11956 check_dsp_r2(ctx);
11957 gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
11958 break;
11959 case OPC_ADDUH_R_OB:
11960 check_dsp_r2(ctx);
11961 gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
11962 break;
11963 }
11964 break;
11965 case OPC_CMPU_EQ_OB_DSP:
11966 switch (op2) {
11967 case OPC_PRECR_OB_QH:
11968 check_dsp_r2(ctx);
11969 gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
11970 break;
11971 case OPC_PRECR_SRA_QH_PW:
11972 check_dsp_r2(ctx);
11973 {
11974 TCGv_i32 ret_t = tcg_constant_i32(ret);
11975 gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
11976 break;
11977 }
11978 case OPC_PRECR_SRA_R_QH_PW:
11979 check_dsp_r2(ctx);
11980 {
11981 TCGv_i32 sa_v = tcg_constant_i32(ret);
11982 gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
11983 break;
11984 }
11985 case OPC_PRECRQ_OB_QH:
11986 check_dsp(ctx);
11987 gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t);
11988 break;
11989 case OPC_PRECRQ_PW_L:
11990 check_dsp(ctx);
11991 gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t);
11992 break;
11993 case OPC_PRECRQ_QH_PW:
11994 check_dsp(ctx);
11995 gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t);
11996 break;
11997 case OPC_PRECRQ_RS_QH_PW:
11998 check_dsp(ctx);
11999 gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12000 break;
12001 case OPC_PRECRQU_S_OB_QH:
12002 check_dsp(ctx);
12003 gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12004 break;
12005 }
12006 break;
12007 #endif
12008 }
12009 }
12010
12011 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
12012 int ret, int v1, int v2)
12013 {
12014 uint32_t op2;
12015 TCGv t0;
12016 TCGv v1_t;
12017 TCGv v2_t;
12018
12019 if (ret == 0) {
12020 /* Treat as NOP. */
12021 return;
12022 }
12023
12024 t0 = tcg_temp_new();
12025 v1_t = tcg_temp_new();
12026 v2_t = tcg_temp_new();
12027
12028 tcg_gen_movi_tl(t0, v1);
12029 gen_load_gpr(v1_t, v1);
12030 gen_load_gpr(v2_t, v2);
12031
12032 switch (opc) {
12033 case OPC_SHLL_QB_DSP:
12034 {
12035 op2 = MASK_SHLL_QB(ctx->opcode);
12036 switch (op2) {
12037 case OPC_SHLL_QB:
12038 check_dsp(ctx);
12039 gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, tcg_env);
12040 break;
12041 case OPC_SHLLV_QB:
12042 check_dsp(ctx);
12043 gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12044 break;
12045 case OPC_SHLL_PH:
12046 check_dsp(ctx);
12047 gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, tcg_env);
12048 break;
12049 case OPC_SHLLV_PH:
12050 check_dsp(ctx);
12051 gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12052 break;
12053 case OPC_SHLL_S_PH:
12054 check_dsp(ctx);
12055 gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, tcg_env);
12056 break;
12057 case OPC_SHLLV_S_PH:
12058 check_dsp(ctx);
12059 gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12060 break;
12061 case OPC_SHLL_S_W:
12062 check_dsp(ctx);
12063 gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, tcg_env);
12064 break;
12065 case OPC_SHLLV_S_W:
12066 check_dsp(ctx);
12067 gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12068 break;
12069 case OPC_SHRL_QB:
12070 check_dsp(ctx);
12071 gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t);
12072 break;
12073 case OPC_SHRLV_QB:
12074 check_dsp(ctx);
12075 gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
12076 break;
12077 case OPC_SHRL_PH:
12078 check_dsp_r2(ctx);
12079 gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
12080 break;
12081 case OPC_SHRLV_PH:
12082 check_dsp_r2(ctx);
12083 gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
12084 break;
12085 case OPC_SHRA_QB:
12086 check_dsp_r2(ctx);
12087 gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
12088 break;
12089 case OPC_SHRA_R_QB:
12090 check_dsp_r2(ctx);
12091 gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
12092 break;
12093 case OPC_SHRAV_QB:
12094 check_dsp_r2(ctx);
12095 gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
12096 break;
12097 case OPC_SHRAV_R_QB:
12098 check_dsp_r2(ctx);
12099 gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
12100 break;
12101 case OPC_SHRA_PH:
12102 check_dsp(ctx);
12103 gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t);
12104 break;
12105 case OPC_SHRA_R_PH:
12106 check_dsp(ctx);
12107 gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t);
12108 break;
12109 case OPC_SHRAV_PH:
12110 check_dsp(ctx);
12111 gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t);
12112 break;
12113 case OPC_SHRAV_R_PH:
12114 check_dsp(ctx);
12115 gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t);
12116 break;
12117 case OPC_SHRA_R_W:
12118 check_dsp(ctx);
12119 gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t);
12120 break;
12121 case OPC_SHRAV_R_W:
12122 check_dsp(ctx);
12123 gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t);
12124 break;
12125 default: /* Invalid */
12126 MIPS_INVAL("MASK SHLL.QB");
12127 gen_reserved_instruction(ctx);
12128 break;
12129 }
12130 break;
12131 }
12132 #ifdef TARGET_MIPS64
12133 case OPC_SHLL_OB_DSP:
12134 op2 = MASK_SHLL_OB(ctx->opcode);
12135 switch (op2) {
12136 case OPC_SHLL_PW:
12137 check_dsp(ctx);
12138 gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, tcg_env);
12139 break;
12140 case OPC_SHLLV_PW:
12141 check_dsp(ctx);
12142 gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env);
12143 break;
12144 case OPC_SHLL_S_PW:
12145 check_dsp(ctx);
12146 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, tcg_env);
12147 break;
12148 case OPC_SHLLV_S_PW:
12149 check_dsp(ctx);
12150 gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env);
12151 break;
12152 case OPC_SHLL_OB:
12153 check_dsp(ctx);
12154 gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, tcg_env);
12155 break;
12156 case OPC_SHLLV_OB:
12157 check_dsp(ctx);
12158 gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, tcg_env);
12159 break;
12160 case OPC_SHLL_QH:
12161 check_dsp(ctx);
12162 gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, tcg_env);
12163 break;
12164 case OPC_SHLLV_QH:
12165 check_dsp(ctx);
12166 gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env);
12167 break;
12168 case OPC_SHLL_S_QH:
12169 check_dsp(ctx);
12170 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, tcg_env);
12171 break;
12172 case OPC_SHLLV_S_QH:
12173 check_dsp(ctx);
12174 gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env);
12175 break;
12176 case OPC_SHRA_OB:
12177 check_dsp_r2(ctx);
12178 gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
12179 break;
12180 case OPC_SHRAV_OB:
12181 check_dsp_r2(ctx);
12182 gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
12183 break;
12184 case OPC_SHRA_R_OB:
12185 check_dsp_r2(ctx);
12186 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
12187 break;
12188 case OPC_SHRAV_R_OB:
12189 check_dsp_r2(ctx);
12190 gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
12191 break;
12192 case OPC_SHRA_PW:
12193 check_dsp(ctx);
12194 gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0);
12195 break;
12196 case OPC_SHRAV_PW:
12197 check_dsp(ctx);
12198 gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t);
12199 break;
12200 case OPC_SHRA_R_PW:
12201 check_dsp(ctx);
12202 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0);
12203 break;
12204 case OPC_SHRAV_R_PW:
12205 check_dsp(ctx);
12206 gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t);
12207 break;
12208 case OPC_SHRA_QH:
12209 check_dsp(ctx);
12210 gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0);
12211 break;
12212 case OPC_SHRAV_QH:
12213 check_dsp(ctx);
12214 gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t);
12215 break;
12216 case OPC_SHRA_R_QH:
12217 check_dsp(ctx);
12218 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0);
12219 break;
12220 case OPC_SHRAV_R_QH:
12221 check_dsp(ctx);
12222 gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t);
12223 break;
12224 case OPC_SHRL_OB:
12225 check_dsp(ctx);
12226 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0);
12227 break;
12228 case OPC_SHRLV_OB:
12229 check_dsp(ctx);
12230 gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
12231 break;
12232 case OPC_SHRL_QH:
12233 check_dsp_r2(ctx);
12234 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
12235 break;
12236 case OPC_SHRLV_QH:
12237 check_dsp_r2(ctx);
12238 gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
12239 break;
12240 default: /* Invalid */
12241 MIPS_INVAL("MASK SHLL.OB");
12242 gen_reserved_instruction(ctx);
12243 break;
12244 }
12245 break;
12246 #endif
12247 }
12248 }
12249
12250 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
12251 int ret, int v1, int v2, int check_ret)
12252 {
12253 TCGv_i32 t0;
12254 TCGv v1_t;
12255 TCGv v2_t;
12256
12257 if ((ret == 0) && (check_ret == 1)) {
12258 /* Treat as NOP. */
12259 return;
12260 }
12261
12262 t0 = tcg_temp_new_i32();
12263 v1_t = tcg_temp_new();
12264 v2_t = tcg_temp_new();
12265
12266 tcg_gen_movi_i32(t0, ret);
12267 gen_load_gpr(v1_t, v1);
12268 gen_load_gpr(v2_t, v2);
12269
12270 switch (op1) {
12271 /*
12272 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
12273 * the same mask and op1.
12274 */
12275 case OPC_MULT_G_2E:
12276 check_dsp_r2(ctx);
12277 switch (op2) {
12278 case OPC_MUL_PH:
12279 gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12280 break;
12281 case OPC_MUL_S_PH:
12282 gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12283 break;
12284 case OPC_MULQ_S_W:
12285 gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12286 break;
12287 case OPC_MULQ_RS_W:
12288 gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12289 break;
12290 }
12291 break;
12292 case OPC_DPA_W_PH_DSP:
12293 switch (op2) {
12294 case OPC_DPAU_H_QBL:
12295 check_dsp(ctx);
12296 gen_helper_dpau_h_qbl(t0, v1_t, v2_t, tcg_env);
12297 break;
12298 case OPC_DPAU_H_QBR:
12299 check_dsp(ctx);
12300 gen_helper_dpau_h_qbr(t0, v1_t, v2_t, tcg_env);
12301 break;
12302 case OPC_DPSU_H_QBL:
12303 check_dsp(ctx);
12304 gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, tcg_env);
12305 break;
12306 case OPC_DPSU_H_QBR:
12307 check_dsp(ctx);
12308 gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, tcg_env);
12309 break;
12310 case OPC_DPA_W_PH:
12311 check_dsp_r2(ctx);
12312 gen_helper_dpa_w_ph(t0, v1_t, v2_t, tcg_env);
12313 break;
12314 case OPC_DPAX_W_PH:
12315 check_dsp_r2(ctx);
12316 gen_helper_dpax_w_ph(t0, v1_t, v2_t, tcg_env);
12317 break;
12318 case OPC_DPAQ_S_W_PH:
12319 check_dsp(ctx);
12320 gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, tcg_env);
12321 break;
12322 case OPC_DPAQX_S_W_PH:
12323 check_dsp_r2(ctx);
12324 gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, tcg_env);
12325 break;
12326 case OPC_DPAQX_SA_W_PH:
12327 check_dsp_r2(ctx);
12328 gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, tcg_env);
12329 break;
12330 case OPC_DPS_W_PH:
12331 check_dsp_r2(ctx);
12332 gen_helper_dps_w_ph(t0, v1_t, v2_t, tcg_env);
12333 break;
12334 case OPC_DPSX_W_PH:
12335 check_dsp_r2(ctx);
12336 gen_helper_dpsx_w_ph(t0, v1_t, v2_t, tcg_env);
12337 break;
12338 case OPC_DPSQ_S_W_PH:
12339 check_dsp(ctx);
12340 gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, tcg_env);
12341 break;
12342 case OPC_DPSQX_S_W_PH:
12343 check_dsp_r2(ctx);
12344 gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, tcg_env);
12345 break;
12346 case OPC_DPSQX_SA_W_PH:
12347 check_dsp_r2(ctx);
12348 gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, tcg_env);
12349 break;
12350 case OPC_MULSAQ_S_W_PH:
12351 check_dsp(ctx);
12352 gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, tcg_env);
12353 break;
12354 case OPC_DPAQ_SA_L_W:
12355 check_dsp(ctx);
12356 gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, tcg_env);
12357 break;
12358 case OPC_DPSQ_SA_L_W:
12359 check_dsp(ctx);
12360 gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, tcg_env);
12361 break;
12362 case OPC_MAQ_S_W_PHL:
12363 check_dsp(ctx);
12364 gen_helper_maq_s_w_phl(t0, v1_t, v2_t, tcg_env);
12365 break;
12366 case OPC_MAQ_S_W_PHR:
12367 check_dsp(ctx);
12368 gen_helper_maq_s_w_phr(t0, v1_t, v2_t, tcg_env);
12369 break;
12370 case OPC_MAQ_SA_W_PHL:
12371 check_dsp(ctx);
12372 gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, tcg_env);
12373 break;
12374 case OPC_MAQ_SA_W_PHR:
12375 check_dsp(ctx);
12376 gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, tcg_env);
12377 break;
12378 case OPC_MULSA_W_PH:
12379 check_dsp_r2(ctx);
12380 gen_helper_mulsa_w_ph(t0, v1_t, v2_t, tcg_env);
12381 break;
12382 }
12383 break;
12384 #ifdef TARGET_MIPS64
12385 case OPC_DPAQ_W_QH_DSP:
12386 {
12387 int ac = ret & 0x03;
12388 tcg_gen_movi_i32(t0, ac);
12389
12390 switch (op2) {
12391 case OPC_DMADD:
12392 check_dsp(ctx);
12393 gen_helper_dmadd(v1_t, v2_t, t0, tcg_env);
12394 break;
12395 case OPC_DMADDU:
12396 check_dsp(ctx);
12397 gen_helper_dmaddu(v1_t, v2_t, t0, tcg_env);
12398 break;
12399 case OPC_DMSUB:
12400 check_dsp(ctx);
12401 gen_helper_dmsub(v1_t, v2_t, t0, tcg_env);
12402 break;
12403 case OPC_DMSUBU:
12404 check_dsp(ctx);
12405 gen_helper_dmsubu(v1_t, v2_t, t0, tcg_env);
12406 break;
12407 case OPC_DPA_W_QH:
12408 check_dsp_r2(ctx);
12409 gen_helper_dpa_w_qh(v1_t, v2_t, t0, tcg_env);
12410 break;
12411 case OPC_DPAQ_S_W_QH:
12412 check_dsp(ctx);
12413 gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, tcg_env);
12414 break;
12415 case OPC_DPAQ_SA_L_PW:
12416 check_dsp(ctx);
12417 gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, tcg_env);
12418 break;
12419 case OPC_DPAU_H_OBL:
12420 check_dsp(ctx);
12421 gen_helper_dpau_h_obl(v1_t, v2_t, t0, tcg_env);
12422 break;
12423 case OPC_DPAU_H_OBR:
12424 check_dsp(ctx);
12425 gen_helper_dpau_h_obr(v1_t, v2_t, t0, tcg_env);
12426 break;
12427 case OPC_DPS_W_QH:
12428 check_dsp_r2(ctx);
12429 gen_helper_dps_w_qh(v1_t, v2_t, t0, tcg_env);
12430 break;
12431 case OPC_DPSQ_S_W_QH:
12432 check_dsp(ctx);
12433 gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, tcg_env);
12434 break;
12435 case OPC_DPSQ_SA_L_PW:
12436 check_dsp(ctx);
12437 gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, tcg_env);
12438 break;
12439 case OPC_DPSU_H_OBL:
12440 check_dsp(ctx);
12441 gen_helper_dpsu_h_obl(v1_t, v2_t, t0, tcg_env);
12442 break;
12443 case OPC_DPSU_H_OBR:
12444 check_dsp(ctx);
12445 gen_helper_dpsu_h_obr(v1_t, v2_t, t0, tcg_env);
12446 break;
12447 case OPC_MAQ_S_L_PWL:
12448 check_dsp(ctx);
12449 gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, tcg_env);
12450 break;
12451 case OPC_MAQ_S_L_PWR:
12452 check_dsp(ctx);
12453 gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, tcg_env);
12454 break;
12455 case OPC_MAQ_S_W_QHLL:
12456 check_dsp(ctx);
12457 gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, tcg_env);
12458 break;
12459 case OPC_MAQ_SA_W_QHLL:
12460 check_dsp(ctx);
12461 gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, tcg_env);
12462 break;
12463 case OPC_MAQ_S_W_QHLR:
12464 check_dsp(ctx);
12465 gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, tcg_env);
12466 break;
12467 case OPC_MAQ_SA_W_QHLR:
12468 check_dsp(ctx);
12469 gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, tcg_env);
12470 break;
12471 case OPC_MAQ_S_W_QHRL:
12472 check_dsp(ctx);
12473 gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, tcg_env);
12474 break;
12475 case OPC_MAQ_SA_W_QHRL:
12476 check_dsp(ctx);
12477 gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, tcg_env);
12478 break;
12479 case OPC_MAQ_S_W_QHRR:
12480 check_dsp(ctx);
12481 gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, tcg_env);
12482 break;
12483 case OPC_MAQ_SA_W_QHRR:
12484 check_dsp(ctx);
12485 gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, tcg_env);
12486 break;
12487 case OPC_MULSAQ_S_L_PW:
12488 check_dsp(ctx);
12489 gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, tcg_env);
12490 break;
12491 case OPC_MULSAQ_S_W_QH:
12492 check_dsp(ctx);
12493 gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, tcg_env);
12494 break;
12495 }
12496 }
12497 break;
12498 #endif
12499 case OPC_ADDU_QB_DSP:
12500 switch (op2) {
12501 case OPC_MULEU_S_PH_QBL:
12502 check_dsp(ctx);
12503 gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12504 break;
12505 case OPC_MULEU_S_PH_QBR:
12506 check_dsp(ctx);
12507 gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12508 break;
12509 case OPC_MULQ_RS_PH:
12510 check_dsp(ctx);
12511 gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12512 break;
12513 case OPC_MULEQ_S_W_PHL:
12514 check_dsp(ctx);
12515 gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12516 break;
12517 case OPC_MULEQ_S_W_PHR:
12518 check_dsp(ctx);
12519 gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12520 break;
12521 case OPC_MULQ_S_PH:
12522 check_dsp_r2(ctx);
12523 gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12524 break;
12525 }
12526 break;
12527 #ifdef TARGET_MIPS64
12528 case OPC_ADDU_OB_DSP:
12529 switch (op2) {
12530 case OPC_MULEQ_S_PW_QHL:
12531 check_dsp(ctx);
12532 gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12533 break;
12534 case OPC_MULEQ_S_PW_QHR:
12535 check_dsp(ctx);
12536 gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12537 break;
12538 case OPC_MULEU_S_QH_OBL:
12539 check_dsp(ctx);
12540 gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12541 break;
12542 case OPC_MULEU_S_QH_OBR:
12543 check_dsp(ctx);
12544 gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12545 break;
12546 case OPC_MULQ_RS_QH:
12547 check_dsp(ctx);
12548 gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12549 break;
12550 }
12551 break;
12552 #endif
12553 }
12554 }
12555
12556 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
12557 int ret, int val)
12558 {
12559 int16_t imm;
12560 TCGv t0;
12561 TCGv val_t;
12562
12563 if (ret == 0) {
12564 /* Treat as NOP. */
12565 return;
12566 }
12567
12568 t0 = tcg_temp_new();
12569 val_t = tcg_temp_new();
12570 gen_load_gpr(val_t, val);
12571
12572 switch (op1) {
12573 case OPC_ABSQ_S_PH_DSP:
12574 switch (op2) {
12575 case OPC_BITREV:
12576 check_dsp(ctx);
12577 gen_helper_bitrev(cpu_gpr[ret], val_t);
12578 break;
12579 case OPC_REPL_QB:
12580 check_dsp(ctx);
12581 {
12582 target_long result;
12583 imm = (ctx->opcode >> 16) & 0xFF;
12584 result = (uint32_t)imm << 24 |
12585 (uint32_t)imm << 16 |
12586 (uint32_t)imm << 8 |
12587 (uint32_t)imm;
12588 result = (int32_t)result;
12589 tcg_gen_movi_tl(cpu_gpr[ret], result);
12590 }
12591 break;
12592 case OPC_REPLV_QB:
12593 check_dsp(ctx);
12594 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
12595 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
12596 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12597 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
12598 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12599 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
12600 break;
12601 case OPC_REPL_PH:
12602 check_dsp(ctx);
12603 {
12604 imm = (ctx->opcode >> 16) & 0x03FF;
12605 imm = (int16_t)(imm << 6) >> 6;
12606 tcg_gen_movi_tl(cpu_gpr[ret], \
12607 (target_long)((int32_t)imm << 16 | \
12608 (uint16_t)imm));
12609 }
12610 break;
12611 case OPC_REPLV_PH:
12612 check_dsp(ctx);
12613 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
12614 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
12615 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12616 tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]);
12617 break;
12618 }
12619 break;
12620 #ifdef TARGET_MIPS64
12621 case OPC_ABSQ_S_QH_DSP:
12622 switch (op2) {
12623 case OPC_REPL_OB:
12624 check_dsp(ctx);
12625 {
12626 target_long temp;
12627
12628 imm = (ctx->opcode >> 16) & 0xFF;
12629 temp = ((uint64_t)imm << 8) | (uint64_t)imm;
12630 temp = (temp << 16) | temp;
12631 temp = (temp << 32) | temp;
12632 tcg_gen_movi_tl(cpu_gpr[ret], temp);
12633 break;
12634 }
12635 case OPC_REPL_PW:
12636 check_dsp(ctx);
12637 {
12638 target_long temp;
12639
12640 imm = (ctx->opcode >> 16) & 0x03FF;
12641 imm = (int16_t)(imm << 6) >> 6;
12642 temp = ((target_long)imm << 32) \
12643 | ((target_long)imm & 0xFFFFFFFF);
12644 tcg_gen_movi_tl(cpu_gpr[ret], temp);
12645 break;
12646 }
12647 case OPC_REPL_QH:
12648 check_dsp(ctx);
12649 {
12650 target_long temp;
12651
12652 imm = (ctx->opcode >> 16) & 0x03FF;
12653 imm = (int16_t)(imm << 6) >> 6;
12654
12655 temp = ((uint64_t)(uint16_t)imm << 48) |
12656 ((uint64_t)(uint16_t)imm << 32) |
12657 ((uint64_t)(uint16_t)imm << 16) |
12658 (uint64_t)(uint16_t)imm;
12659 tcg_gen_movi_tl(cpu_gpr[ret], temp);
12660 break;
12661 }
12662 case OPC_REPLV_OB:
12663 check_dsp(ctx);
12664 tcg_gen_ext8u_tl(cpu_gpr[ret], val_t);
12665 tcg_gen_shli_tl(t0, cpu_gpr[ret], 8);
12666 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12667 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
12668 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12669 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
12670 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12671 break;
12672 case OPC_REPLV_PW:
12673 check_dsp(ctx);
12674 tcg_gen_ext32u_i64(cpu_gpr[ret], val_t);
12675 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
12676 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12677 break;
12678 case OPC_REPLV_QH:
12679 check_dsp(ctx);
12680 tcg_gen_ext16u_tl(cpu_gpr[ret], val_t);
12681 tcg_gen_shli_tl(t0, cpu_gpr[ret], 16);
12682 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12683 tcg_gen_shli_tl(t0, cpu_gpr[ret], 32);
12684 tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0);
12685 break;
12686 }
12687 break;
12688 #endif
12689 }
12690 }
12691
12692 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
12693 uint32_t op1, uint32_t op2,
12694 int ret, int v1, int v2, int check_ret)
12695 {
12696 TCGv t1;
12697 TCGv v1_t;
12698 TCGv v2_t;
12699
12700 if ((ret == 0) && (check_ret == 1)) {
12701 /* Treat as NOP. */
12702 return;
12703 }
12704
12705 t1 = tcg_temp_new();
12706 v1_t = tcg_temp_new();
12707 v2_t = tcg_temp_new();
12708
12709 gen_load_gpr(v1_t, v1);
12710 gen_load_gpr(v2_t, v2);
12711
12712 switch (op1) {
12713 case OPC_CMPU_EQ_QB_DSP:
12714 switch (op2) {
12715 case OPC_CMPU_EQ_QB:
12716 check_dsp(ctx);
12717 gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env);
12718 break;
12719 case OPC_CMPU_LT_QB:
12720 check_dsp(ctx);
12721 gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env);
12722 break;
12723 case OPC_CMPU_LE_QB:
12724 check_dsp(ctx);
12725 gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env);
12726 break;
12727 case OPC_CMPGU_EQ_QB:
12728 check_dsp(ctx);
12729 gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t);
12730 break;
12731 case OPC_CMPGU_LT_QB:
12732 check_dsp(ctx);
12733 gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t);
12734 break;
12735 case OPC_CMPGU_LE_QB:
12736 check_dsp(ctx);
12737 gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
12738 break;
12739 case OPC_CMPGDU_EQ_QB:
12740 check_dsp_r2(ctx);
12741 gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
12742 tcg_gen_mov_tl(cpu_gpr[ret], t1);
12743 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
12744 tcg_gen_shli_tl(t1, t1, 24);
12745 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
12746 break;
12747 case OPC_CMPGDU_LT_QB:
12748 check_dsp_r2(ctx);
12749 gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
12750 tcg_gen_mov_tl(cpu_gpr[ret], t1);
12751 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
12752 tcg_gen_shli_tl(t1, t1, 24);
12753 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
12754 break;
12755 case OPC_CMPGDU_LE_QB:
12756 check_dsp_r2(ctx);
12757 gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
12758 tcg_gen_mov_tl(cpu_gpr[ret], t1);
12759 tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
12760 tcg_gen_shli_tl(t1, t1, 24);
12761 tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
12762 break;
12763 case OPC_CMP_EQ_PH:
12764 check_dsp(ctx);
12765 gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env);
12766 break;
12767 case OPC_CMP_LT_PH:
12768 check_dsp(ctx);
12769 gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env);
12770 break;
12771 case OPC_CMP_LE_PH:
12772 check_dsp(ctx);
12773 gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env);
12774 break;
12775 case OPC_PICK_QB:
12776 check_dsp(ctx);
12777 gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12778 break;
12779 case OPC_PICK_PH:
12780 check_dsp(ctx);
12781 gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12782 break;
12783 case OPC_PACKRL_PH:
12784 check_dsp(ctx);
12785 gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t);
12786 break;
12787 }
12788 break;
12789 #ifdef TARGET_MIPS64
12790 case OPC_CMPU_EQ_OB_DSP:
12791 switch (op2) {
12792 case OPC_CMP_EQ_PW:
12793 check_dsp(ctx);
12794 gen_helper_cmp_eq_pw(v1_t, v2_t, tcg_env);
12795 break;
12796 case OPC_CMP_LT_PW:
12797 check_dsp(ctx);
12798 gen_helper_cmp_lt_pw(v1_t, v2_t, tcg_env);
12799 break;
12800 case OPC_CMP_LE_PW:
12801 check_dsp(ctx);
12802 gen_helper_cmp_le_pw(v1_t, v2_t, tcg_env);
12803 break;
12804 case OPC_CMP_EQ_QH:
12805 check_dsp(ctx);
12806 gen_helper_cmp_eq_qh(v1_t, v2_t, tcg_env);
12807 break;
12808 case OPC_CMP_LT_QH:
12809 check_dsp(ctx);
12810 gen_helper_cmp_lt_qh(v1_t, v2_t, tcg_env);
12811 break;
12812 case OPC_CMP_LE_QH:
12813 check_dsp(ctx);
12814 gen_helper_cmp_le_qh(v1_t, v2_t, tcg_env);
12815 break;
12816 case OPC_CMPGDU_EQ_OB:
12817 check_dsp_r2(ctx);
12818 gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12819 break;
12820 case OPC_CMPGDU_LT_OB:
12821 check_dsp_r2(ctx);
12822 gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12823 break;
12824 case OPC_CMPGDU_LE_OB:
12825 check_dsp_r2(ctx);
12826 gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12827 break;
12828 case OPC_CMPGU_EQ_OB:
12829 check_dsp(ctx);
12830 gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t);
12831 break;
12832 case OPC_CMPGU_LT_OB:
12833 check_dsp(ctx);
12834 gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t);
12835 break;
12836 case OPC_CMPGU_LE_OB:
12837 check_dsp(ctx);
12838 gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t);
12839 break;
12840 case OPC_CMPU_EQ_OB:
12841 check_dsp(ctx);
12842 gen_helper_cmpu_eq_ob(v1_t, v2_t, tcg_env);
12843 break;
12844 case OPC_CMPU_LT_OB:
12845 check_dsp(ctx);
12846 gen_helper_cmpu_lt_ob(v1_t, v2_t, tcg_env);
12847 break;
12848 case OPC_CMPU_LE_OB:
12849 check_dsp(ctx);
12850 gen_helper_cmpu_le_ob(v1_t, v2_t, tcg_env);
12851 break;
12852 case OPC_PACKRL_PW:
12853 check_dsp(ctx);
12854 gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t);
12855 break;
12856 case OPC_PICK_OB:
12857 check_dsp(ctx);
12858 gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12859 break;
12860 case OPC_PICK_PW:
12861 check_dsp(ctx);
12862 gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12863 break;
12864 case OPC_PICK_QH:
12865 check_dsp(ctx);
12866 gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env);
12867 break;
12868 }
12869 break;
12870 #endif
12871 }
12872 }
12873
12874 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
12875 uint32_t op1, int rt, int rs, int sa)
12876 {
12877 TCGv t0;
12878
12879 check_dsp_r2(ctx);
12880
12881 if (rt == 0) {
12882 /* Treat as NOP. */
12883 return;
12884 }
12885
12886 t0 = tcg_temp_new();
12887 gen_load_gpr(t0, rs);
12888
12889 switch (op1) {
12890 case OPC_APPEND_DSP:
12891 switch (MASK_APPEND(ctx->opcode)) {
12892 case OPC_APPEND:
12893 if (sa != 0) {
12894 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa);
12895 }
12896 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
12897 break;
12898 case OPC_PREPEND:
12899 if (sa != 0) {
12900 tcg_gen_ext32u_tl(cpu_gpr[rt], cpu_gpr[rt]);
12901 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
12902 tcg_gen_shli_tl(t0, t0, 32 - sa);
12903 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
12904 }
12905 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
12906 break;
12907 case OPC_BALIGN:
12908 sa &= 3;
12909 if (sa != 0 && sa != 2) {
12910 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
12911 tcg_gen_ext32u_tl(t0, t0);
12912 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa));
12913 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
12914 }
12915 tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
12916 break;
12917 default: /* Invalid */
12918 MIPS_INVAL("MASK APPEND");
12919 gen_reserved_instruction(ctx);
12920 break;
12921 }
12922 break;
12923 #ifdef TARGET_MIPS64
12924 case OPC_DAPPEND_DSP:
12925 switch (MASK_DAPPEND(ctx->opcode)) {
12926 case OPC_DAPPEND:
12927 if (sa != 0) {
12928 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa);
12929 }
12930 break;
12931 case OPC_PREPENDD:
12932 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], 0x20 | sa);
12933 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa));
12934 tcg_gen_or_tl(cpu_gpr[rt], t0, t0);
12935 break;
12936 case OPC_PREPENDW:
12937 if (sa != 0) {
12938 tcg_gen_shri_tl(cpu_gpr[rt], cpu_gpr[rt], sa);
12939 tcg_gen_shli_tl(t0, t0, 64 - sa);
12940 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
12941 }
12942 break;
12943 case OPC_DBALIGN:
12944 sa &= 7;
12945 if (sa != 0 && sa != 2 && sa != 4) {
12946 tcg_gen_shli_tl(cpu_gpr[rt], cpu_gpr[rt], 8 * sa);
12947 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa));
12948 tcg_gen_or_tl(cpu_gpr[rt], cpu_gpr[rt], t0);
12949 }
12950 break;
12951 default: /* Invalid */
12952 MIPS_INVAL("MASK DAPPEND");
12953 gen_reserved_instruction(ctx);
12954 break;
12955 }
12956 break;
12957 #endif
12958 }
12959 }
12960
12961 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
12962 int ret, int v1, int v2, int check_ret)
12963
12964 {
12965 TCGv t0;
12966 TCGv t1;
12967 TCGv v1_t;
12968 int16_t imm;
12969
12970 if ((ret == 0) && (check_ret == 1)) {
12971 /* Treat as NOP. */
12972 return;
12973 }
12974
12975 t0 = tcg_temp_new();
12976 t1 = tcg_temp_new();
12977 v1_t = tcg_temp_new();
12978
12979 gen_load_gpr(v1_t, v1);
12980
12981 switch (op1) {
12982 case OPC_EXTR_W_DSP:
12983 check_dsp(ctx);
12984 switch (op2) {
12985 case OPC_EXTR_W:
12986 tcg_gen_movi_tl(t0, v2);
12987 tcg_gen_movi_tl(t1, v1);
12988 gen_helper_extr_w(cpu_gpr[ret], t0, t1, tcg_env);
12989 break;
12990 case OPC_EXTR_R_W:
12991 tcg_gen_movi_tl(t0, v2);
12992 tcg_gen_movi_tl(t1, v1);
12993 gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, tcg_env);
12994 break;
12995 case OPC_EXTR_RS_W:
12996 tcg_gen_movi_tl(t0, v2);
12997 tcg_gen_movi_tl(t1, v1);
12998 gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, tcg_env);
12999 break;
13000 case OPC_EXTR_S_H:
13001 tcg_gen_movi_tl(t0, v2);
13002 tcg_gen_movi_tl(t1, v1);
13003 gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, tcg_env);
13004 break;
13005 case OPC_EXTRV_S_H:
13006 tcg_gen_movi_tl(t0, v2);
13007 gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env);
13008 break;
13009 case OPC_EXTRV_W:
13010 tcg_gen_movi_tl(t0, v2);
13011 gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, tcg_env);
13012 break;
13013 case OPC_EXTRV_R_W:
13014 tcg_gen_movi_tl(t0, v2);
13015 gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env);
13016 break;
13017 case OPC_EXTRV_RS_W:
13018 tcg_gen_movi_tl(t0, v2);
13019 gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env);
13020 break;
13021 case OPC_EXTP:
13022 tcg_gen_movi_tl(t0, v2);
13023 tcg_gen_movi_tl(t1, v1);
13024 gen_helper_extp(cpu_gpr[ret], t0, t1, tcg_env);
13025 break;
13026 case OPC_EXTPV:
13027 tcg_gen_movi_tl(t0, v2);
13028 gen_helper_extp(cpu_gpr[ret], t0, v1_t, tcg_env);
13029 break;
13030 case OPC_EXTPDP:
13031 tcg_gen_movi_tl(t0, v2);
13032 tcg_gen_movi_tl(t1, v1);
13033 gen_helper_extpdp(cpu_gpr[ret], t0, t1, tcg_env);
13034 break;
13035 case OPC_EXTPDPV:
13036 tcg_gen_movi_tl(t0, v2);
13037 gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, tcg_env);
13038 break;
13039 case OPC_SHILO:
13040 imm = (ctx->opcode >> 20) & 0x3F;
13041 tcg_gen_movi_tl(t0, ret);
13042 tcg_gen_movi_tl(t1, imm);
13043 gen_helper_shilo(t0, t1, tcg_env);
13044 break;
13045 case OPC_SHILOV:
13046 tcg_gen_movi_tl(t0, ret);
13047 gen_helper_shilo(t0, v1_t, tcg_env);
13048 break;
13049 case OPC_MTHLIP:
13050 tcg_gen_movi_tl(t0, ret);
13051 gen_helper_mthlip(t0, v1_t, tcg_env);
13052 break;
13053 case OPC_WRDSP:
13054 imm = (ctx->opcode >> 11) & 0x3FF;
13055 tcg_gen_movi_tl(t0, imm);
13056 gen_helper_wrdsp(v1_t, t0, tcg_env);
13057 break;
13058 case OPC_RDDSP:
13059 imm = (ctx->opcode >> 16) & 0x03FF;
13060 tcg_gen_movi_tl(t0, imm);
13061 gen_helper_rddsp(cpu_gpr[ret], t0, tcg_env);
13062 break;
13063 }
13064 break;
13065 #ifdef TARGET_MIPS64
13066 case OPC_DEXTR_W_DSP:
13067 check_dsp(ctx);
13068 switch (op2) {
13069 case OPC_DMTHLIP:
13070 tcg_gen_movi_tl(t0, ret);
13071 gen_helper_dmthlip(v1_t, t0, tcg_env);
13072 break;
13073 case OPC_DSHILO:
13074 {
13075 int shift = (ctx->opcode >> 19) & 0x7F;
13076 int ac = (ctx->opcode >> 11) & 0x03;
13077 tcg_gen_movi_tl(t0, shift);
13078 tcg_gen_movi_tl(t1, ac);
13079 gen_helper_dshilo(t0, t1, tcg_env);
13080 break;
13081 }
13082 case OPC_DSHILOV:
13083 {
13084 int ac = (ctx->opcode >> 11) & 0x03;
13085 tcg_gen_movi_tl(t0, ac);
13086 gen_helper_dshilo(v1_t, t0, tcg_env);
13087 break;
13088 }
13089 case OPC_DEXTP:
13090 tcg_gen_movi_tl(t0, v2);
13091 tcg_gen_movi_tl(t1, v1);
13092
13093 gen_helper_dextp(cpu_gpr[ret], t0, t1, tcg_env);
13094 break;
13095 case OPC_DEXTPV:
13096 tcg_gen_movi_tl(t0, v2);
13097 gen_helper_dextp(cpu_gpr[ret], t0, v1_t, tcg_env);
13098 break;
13099 case OPC_DEXTPDP:
13100 tcg_gen_movi_tl(t0, v2);
13101 tcg_gen_movi_tl(t1, v1);
13102 gen_helper_dextpdp(cpu_gpr[ret], t0, t1, tcg_env);
13103 break;
13104 case OPC_DEXTPDPV:
13105 tcg_gen_movi_tl(t0, v2);
13106 gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, tcg_env);
13107 break;
13108 case OPC_DEXTR_L:
13109 tcg_gen_movi_tl(t0, v2);
13110 tcg_gen_movi_tl(t1, v1);
13111 gen_helper_dextr_l(cpu_gpr[ret], t0, t1, tcg_env);
13112 break;
13113 case OPC_DEXTR_R_L:
13114 tcg_gen_movi_tl(t0, v2);
13115 tcg_gen_movi_tl(t1, v1);
13116 gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, tcg_env);
13117 break;
13118 case OPC_DEXTR_RS_L:
13119 tcg_gen_movi_tl(t0, v2);
13120 tcg_gen_movi_tl(t1, v1);
13121 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, tcg_env);
13122 break;
13123 case OPC_DEXTR_W:
13124 tcg_gen_movi_tl(t0, v2);
13125 tcg_gen_movi_tl(t1, v1);
13126 gen_helper_dextr_w(cpu_gpr[ret], t0, t1, tcg_env);
13127 break;
13128 case OPC_DEXTR_R_W:
13129 tcg_gen_movi_tl(t0, v2);
13130 tcg_gen_movi_tl(t1, v1);
13131 gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, tcg_env);
13132 break;
13133 case OPC_DEXTR_RS_W:
13134 tcg_gen_movi_tl(t0, v2);
13135 tcg_gen_movi_tl(t1, v1);
13136 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, tcg_env);
13137 break;
13138 case OPC_DEXTR_S_H:
13139 tcg_gen_movi_tl(t0, v2);
13140 tcg_gen_movi_tl(t1, v1);
13141 gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, tcg_env);
13142 break;
13143 case OPC_DEXTRV_S_H:
13144 tcg_gen_movi_tl(t0, v2);
13145 gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env);
13146 break;
13147 case OPC_DEXTRV_L:
13148 tcg_gen_movi_tl(t0, v2);
13149 gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, tcg_env);
13150 break;
13151 case OPC_DEXTRV_R_L:
13152 tcg_gen_movi_tl(t0, v2);
13153 gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, tcg_env);
13154 break;
13155 case OPC_DEXTRV_RS_L:
13156 tcg_gen_movi_tl(t0, v2);
13157 gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, tcg_env);
13158 break;
13159 case OPC_DEXTRV_W:
13160 tcg_gen_movi_tl(t0, v2);
13161 gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, tcg_env);
13162 break;
13163 case OPC_DEXTRV_R_W:
13164 tcg_gen_movi_tl(t0, v2);
13165 gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env);
13166 break;
13167 case OPC_DEXTRV_RS_W:
13168 tcg_gen_movi_tl(t0, v2);
13169 gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env);
13170 break;
13171 }
13172 break;
13173 #endif
13174 }
13175 }
13176
13177 /* End MIPSDSP functions. */
13178
13179 static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
13180 {
13181 int rs, rt, rd, sa;
13182 uint32_t op1, op2;
13183
13184 rs = (ctx->opcode >> 21) & 0x1f;
13185 rt = (ctx->opcode >> 16) & 0x1f;
13186 rd = (ctx->opcode >> 11) & 0x1f;
13187 sa = (ctx->opcode >> 6) & 0x1f;
13188
13189 op1 = MASK_SPECIAL(ctx->opcode);
13190 switch (op1) {
13191 case OPC_MULT:
13192 case OPC_MULTU:
13193 case OPC_DIV:
13194 case OPC_DIVU:
13195 op2 = MASK_R6_MULDIV(ctx->opcode);
13196 switch (op2) {
13197 case R6_OPC_MUL:
13198 case R6_OPC_MUH:
13199 case R6_OPC_MULU:
13200 case R6_OPC_MUHU:
13201 case R6_OPC_DIV:
13202 case R6_OPC_MOD:
13203 case R6_OPC_DIVU:
13204 case R6_OPC_MODU:
13205 gen_r6_muldiv(ctx, op2, rd, rs, rt);
13206 break;
13207 default:
13208 MIPS_INVAL("special_r6 muldiv");
13209 gen_reserved_instruction(ctx);
13210 break;
13211 }
13212 break;
13213 case OPC_SELEQZ:
13214 case OPC_SELNEZ:
13215 gen_cond_move(ctx, op1, rd, rs, rt);
13216 break;
13217 case R6_OPC_CLO:
13218 case R6_OPC_CLZ:
13219 if (rt == 0 && sa == 1) {
13220 /*
13221 * Major opcode and function field is shared with preR6 MFHI/MTHI.
13222 * We need additionally to check other fields.
13223 */
13224 gen_cl(ctx, op1, rd, rs);
13225 } else {
13226 gen_reserved_instruction(ctx);
13227 }
13228 break;
13229 case R6_OPC_SDBBP:
13230 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) {
13231 ctx->base.is_jmp = DISAS_SEMIHOST;
13232 } else {
13233 if (ctx->hflags & MIPS_HFLAG_SBRI) {
13234 gen_reserved_instruction(ctx);
13235 } else {
13236 generate_exception_end(ctx, EXCP_DBp);
13237 }
13238 }
13239 break;
13240 #if defined(TARGET_MIPS64)
13241 case R6_OPC_DCLO:
13242 case R6_OPC_DCLZ:
13243 if (rt == 0 && sa == 1) {
13244 /*
13245 * Major opcode and function field is shared with preR6 MFHI/MTHI.
13246 * We need additionally to check other fields.
13247 */
13248 check_mips_64(ctx);
13249 gen_cl(ctx, op1, rd, rs);
13250 } else {
13251 gen_reserved_instruction(ctx);
13252 }
13253 break;
13254 case OPC_DMULT:
13255 case OPC_DMULTU:
13256 case OPC_DDIV:
13257 case OPC_DDIVU:
13258
13259 op2 = MASK_R6_MULDIV(ctx->opcode);
13260 switch (op2) {
13261 case R6_OPC_DMUL:
13262 case R6_OPC_DMUH:
13263 case R6_OPC_DMULU:
13264 case R6_OPC_DMUHU:
13265 case R6_OPC_DDIV:
13266 case R6_OPC_DMOD:
13267 case R6_OPC_DDIVU:
13268 case R6_OPC_DMODU:
13269 check_mips_64(ctx);
13270 gen_r6_muldiv(ctx, op2, rd, rs, rt);
13271 break;
13272 default:
13273 MIPS_INVAL("special_r6 muldiv");
13274 gen_reserved_instruction(ctx);
13275 break;
13276 }
13277 break;
13278 #endif
13279 default: /* Invalid */
13280 MIPS_INVAL("special_r6");
13281 gen_reserved_instruction(ctx);
13282 break;
13283 }
13284 }
13285
13286 static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
13287 {
13288 int rs = extract32(ctx->opcode, 21, 5);
13289 int rt = extract32(ctx->opcode, 16, 5);
13290 int rd = extract32(ctx->opcode, 11, 5);
13291 uint32_t op1 = MASK_SPECIAL(ctx->opcode);
13292
13293 switch (op1) {
13294 case OPC_MOVN: /* Conditional move */
13295 case OPC_MOVZ:
13296 gen_cond_move(ctx, op1, rd, rs, rt);
13297 break;
13298 case OPC_MFHI: /* Move from HI/LO */
13299 case OPC_MFLO:
13300 gen_HILO(ctx, op1, 0, rd);
13301 break;
13302 case OPC_MTHI:
13303 case OPC_MTLO: /* Move to HI/LO */
13304 gen_HILO(ctx, op1, 0, rs);
13305 break;
13306 case OPC_MULT:
13307 case OPC_MULTU:
13308 gen_mul_txx9(ctx, op1, rd, rs, rt);
13309 break;
13310 case OPC_DIV:
13311 case OPC_DIVU:
13312 gen_muldiv(ctx, op1, 0, rs, rt);
13313 break;
13314 #if defined(TARGET_MIPS64)
13315 case OPC_DMULT:
13316 case OPC_DMULTU:
13317 case OPC_DDIV:
13318 case OPC_DDIVU:
13319 check_insn_opc_user_only(ctx, INSN_R5900);
13320 gen_muldiv(ctx, op1, 0, rs, rt);
13321 break;
13322 #endif
13323 case OPC_JR:
13324 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
13325 break;
13326 default: /* Invalid */
13327 MIPS_INVAL("special_tx79");
13328 gen_reserved_instruction(ctx);
13329 break;
13330 }
13331 }
13332
13333 static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
13334 {
13335 int rs, rt, rd;
13336 uint32_t op1;
13337
13338 rs = (ctx->opcode >> 21) & 0x1f;
13339 rt = (ctx->opcode >> 16) & 0x1f;
13340 rd = (ctx->opcode >> 11) & 0x1f;
13341
13342 op1 = MASK_SPECIAL(ctx->opcode);
13343 switch (op1) {
13344 case OPC_MOVN: /* Conditional move */
13345 case OPC_MOVZ:
13346 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
13347 INSN_LOONGSON2E | INSN_LOONGSON2F);
13348 gen_cond_move(ctx, op1, rd, rs, rt);
13349 break;
13350 case OPC_MFHI: /* Move from HI/LO */
13351 case OPC_MFLO:
13352 gen_HILO(ctx, op1, rs & 3, rd);
13353 break;
13354 case OPC_MTHI:
13355 case OPC_MTLO: /* Move to HI/LO */
13356 gen_HILO(ctx, op1, rd & 3, rs);
13357 break;
13358 case OPC_MOVCI:
13359 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
13360 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
13361 check_cp1_enabled(ctx);
13362 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
13363 (ctx->opcode >> 16) & 1);
13364 } else {
13365 generate_exception_err(ctx, EXCP_CpU, 1);
13366 }
13367 break;
13368 case OPC_MULT:
13369 case OPC_MULTU:
13370 gen_muldiv(ctx, op1, rd & 3, rs, rt);
13371 break;
13372 case OPC_DIV:
13373 case OPC_DIVU:
13374 gen_muldiv(ctx, op1, 0, rs, rt);
13375 break;
13376 #if defined(TARGET_MIPS64)
13377 case OPC_DMULT:
13378 case OPC_DMULTU:
13379 case OPC_DDIV:
13380 case OPC_DDIVU:
13381 check_insn(ctx, ISA_MIPS3);
13382 check_mips_64(ctx);
13383 gen_muldiv(ctx, op1, 0, rs, rt);
13384 break;
13385 #endif
13386 case OPC_JR:
13387 gen_compute_branch(ctx, op1, 4, rs, 0, 0, 4);
13388 break;
13389 case OPC_SPIM:
13390 #ifdef MIPS_STRICT_STANDARD
13391 MIPS_INVAL("SPIM");
13392 gen_reserved_instruction(ctx);
13393 #else
13394 /* Implemented as RI exception for now. */
13395 MIPS_INVAL("spim (unofficial)");
13396 gen_reserved_instruction(ctx);
13397 #endif
13398 break;
13399 default: /* Invalid */
13400 MIPS_INVAL("special_legacy");
13401 gen_reserved_instruction(ctx);
13402 break;
13403 }
13404 }
13405
13406 static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
13407 {
13408 int rs, rt, rd, sa;
13409 uint32_t op1;
13410
13411 rs = (ctx->opcode >> 21) & 0x1f;
13412 rt = (ctx->opcode >> 16) & 0x1f;
13413 rd = (ctx->opcode >> 11) & 0x1f;
13414 sa = (ctx->opcode >> 6) & 0x1f;
13415
13416 op1 = MASK_SPECIAL(ctx->opcode);
13417 switch (op1) {
13418 case OPC_SLL: /* Shift with immediate */
13419 if (sa == 5 && rd == 0 &&
13420 rs == 0 && rt == 0) { /* PAUSE */
13421 if ((ctx->insn_flags & ISA_MIPS_R6) &&
13422 (ctx->hflags & MIPS_HFLAG_BMASK)) {
13423 gen_reserved_instruction(ctx);
13424 break;
13425 }
13426 }
13427 /* Fallthrough */
13428 case OPC_SRA:
13429 gen_shift_imm(ctx, op1, rd, rt, sa);
13430 break;
13431 case OPC_SRL:
13432 switch ((ctx->opcode >> 21) & 0x1f) {
13433 case 1:
13434 /* rotr is decoded as srl on non-R2 CPUs */
13435 if (ctx->insn_flags & ISA_MIPS_R2) {
13436 op1 = OPC_ROTR;
13437 }
13438 /* Fallthrough */
13439 case 0:
13440 gen_shift_imm(ctx, op1, rd, rt, sa);
13441 break;
13442 default:
13443 gen_reserved_instruction(ctx);
13444 break;
13445 }
13446 break;
13447 case OPC_ADD:
13448 case OPC_ADDU:
13449 case OPC_SUB:
13450 case OPC_SUBU:
13451 gen_arith(ctx, op1, rd, rs, rt);
13452 break;
13453 case OPC_SLLV: /* Shifts */
13454 case OPC_SRAV:
13455 gen_shift(ctx, op1, rd, rs, rt);
13456 break;
13457 case OPC_SRLV:
13458 switch ((ctx->opcode >> 6) & 0x1f) {
13459 case 1:
13460 /* rotrv is decoded as srlv on non-R2 CPUs */
13461 if (ctx->insn_flags & ISA_MIPS_R2) {
13462 op1 = OPC_ROTRV;
13463 }
13464 /* Fallthrough */
13465 case 0:
13466 gen_shift(ctx, op1, rd, rs, rt);
13467 break;
13468 default:
13469 gen_reserved_instruction(ctx);
13470 break;
13471 }
13472 break;
13473 case OPC_SLT: /* Set on less than */
13474 case OPC_SLTU:
13475 gen_slt(ctx, op1, rd, rs, rt);
13476 break;
13477 case OPC_AND: /* Logic*/
13478 case OPC_OR:
13479 case OPC_NOR:
13480 case OPC_XOR:
13481 gen_logic(ctx, op1, rd, rs, rt);
13482 break;
13483 case OPC_JALR:
13484 gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
13485 break;
13486 case OPC_TGE: /* Traps */
13487 case OPC_TGEU:
13488 case OPC_TLT:
13489 case OPC_TLTU:
13490 case OPC_TEQ:
13491 case OPC_TNE:
13492 check_insn(ctx, ISA_MIPS2);
13493 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10));
13494 break;
13495 case OPC_PMON:
13496 /* Pmon entry point, also R4010 selsl */
13497 #ifdef MIPS_STRICT_STANDARD
13498 MIPS_INVAL("PMON / selsl");
13499 gen_reserved_instruction(ctx);
13500 #else
13501 gen_helper_pmon(tcg_env, tcg_constant_i32(sa));
13502 #endif
13503 break;
13504 case OPC_SYSCALL:
13505 generate_exception_end(ctx, EXCP_SYSCALL);
13506 break;
13507 case OPC_BREAK:
13508 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20));
13509 break;
13510 case OPC_SYNC:
13511 check_insn(ctx, ISA_MIPS2);
13512 gen_sync(extract32(ctx->opcode, 6, 5));
13513 break;
13514
13515 #if defined(TARGET_MIPS64)
13516 /* MIPS64 specific opcodes */
13517 case OPC_DSLL:
13518 case OPC_DSRA:
13519 case OPC_DSLL32:
13520 case OPC_DSRA32:
13521 check_insn(ctx, ISA_MIPS3);
13522 check_mips_64(ctx);
13523 gen_shift_imm(ctx, op1, rd, rt, sa);
13524 break;
13525 case OPC_DSRL:
13526 switch ((ctx->opcode >> 21) & 0x1f) {
13527 case 1:
13528 /* drotr is decoded as dsrl on non-R2 CPUs */
13529 if (ctx->insn_flags & ISA_MIPS_R2) {
13530 op1 = OPC_DROTR;
13531 }
13532 /* Fallthrough */
13533 case 0:
13534 check_insn(ctx, ISA_MIPS3);
13535 check_mips_64(ctx);
13536 gen_shift_imm(ctx, op1, rd, rt, sa);
13537 break;
13538 default:
13539 gen_reserved_instruction(ctx);
13540 break;
13541 }
13542 break;
13543 case OPC_DSRL32:
13544 switch ((ctx->opcode >> 21) & 0x1f) {
13545 case 1:
13546 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
13547 if (ctx->insn_flags & ISA_MIPS_R2) {
13548 op1 = OPC_DROTR32;
13549 }
13550 /* Fallthrough */
13551 case 0:
13552 check_insn(ctx, ISA_MIPS3);
13553 check_mips_64(ctx);
13554 gen_shift_imm(ctx, op1, rd, rt, sa);
13555 break;
13556 default:
13557 gen_reserved_instruction(ctx);
13558 break;
13559 }
13560 break;
13561 case OPC_DADD:
13562 case OPC_DADDU:
13563 case OPC_DSUB:
13564 case OPC_DSUBU:
13565 check_insn(ctx, ISA_MIPS3);
13566 check_mips_64(ctx);
13567 gen_arith(ctx, op1, rd, rs, rt);
13568 break;
13569 case OPC_DSLLV:
13570 case OPC_DSRAV:
13571 check_insn(ctx, ISA_MIPS3);
13572 check_mips_64(ctx);
13573 gen_shift(ctx, op1, rd, rs, rt);
13574 break;
13575 case OPC_DSRLV:
13576 switch ((ctx->opcode >> 6) & 0x1f) {
13577 case 1:
13578 /* drotrv is decoded as dsrlv on non-R2 CPUs */
13579 if (ctx->insn_flags & ISA_MIPS_R2) {
13580 op1 = OPC_DROTRV;
13581 }
13582 /* Fallthrough */
13583 case 0:
13584 check_insn(ctx, ISA_MIPS3);
13585 check_mips_64(ctx);
13586 gen_shift(ctx, op1, rd, rs, rt);
13587 break;
13588 default:
13589 gen_reserved_instruction(ctx);
13590 break;
13591 }
13592 break;
13593 #endif
13594 default:
13595 if (ctx->insn_flags & ISA_MIPS_R6) {
13596 decode_opc_special_r6(env, ctx);
13597 } else if (ctx->insn_flags & INSN_R5900) {
13598 decode_opc_special_tx79(env, ctx);
13599 } else {
13600 decode_opc_special_legacy(env, ctx);
13601 }
13602 }
13603 }
13604
13605
13606 static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
13607 {
13608 int rs, rt, rd;
13609 uint32_t op1;
13610
13611 rs = (ctx->opcode >> 21) & 0x1f;
13612 rt = (ctx->opcode >> 16) & 0x1f;
13613 rd = (ctx->opcode >> 11) & 0x1f;
13614
13615 op1 = MASK_SPECIAL2(ctx->opcode);
13616 switch (op1) {
13617 case OPC_MADD: /* Multiply and add/sub */
13618 case OPC_MADDU:
13619 case OPC_MSUB:
13620 case OPC_MSUBU:
13621 check_insn(ctx, ISA_MIPS_R1);
13622 gen_muldiv(ctx, op1, rd & 3, rs, rt);
13623 break;
13624 case OPC_MUL:
13625 gen_arith(ctx, op1, rd, rs, rt);
13626 break;
13627 case OPC_DIV_G_2F:
13628 case OPC_DIVU_G_2F:
13629 case OPC_MULT_G_2F:
13630 case OPC_MULTU_G_2F:
13631 case OPC_MOD_G_2F:
13632 case OPC_MODU_G_2F:
13633 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
13634 gen_loongson_integer(ctx, op1, rd, rs, rt);
13635 break;
13636 case OPC_CLO:
13637 case OPC_CLZ:
13638 check_insn(ctx, ISA_MIPS_R1);
13639 gen_cl(ctx, op1, rd, rs);
13640 break;
13641 case OPC_SDBBP:
13642 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) {
13643 ctx->base.is_jmp = DISAS_SEMIHOST;
13644 } else {
13645 /*
13646 * XXX: not clear which exception should be raised
13647 * when in debug mode...
13648 */
13649 check_insn(ctx, ISA_MIPS_R1);
13650 generate_exception_end(ctx, EXCP_DBp);
13651 }
13652 break;
13653 #if defined(TARGET_MIPS64)
13654 case OPC_DCLO:
13655 case OPC_DCLZ:
13656 check_insn(ctx, ISA_MIPS_R1);
13657 check_mips_64(ctx);
13658 gen_cl(ctx, op1, rd, rs);
13659 break;
13660 case OPC_DMULT_G_2F:
13661 case OPC_DMULTU_G_2F:
13662 case OPC_DDIV_G_2F:
13663 case OPC_DDIVU_G_2F:
13664 case OPC_DMOD_G_2F:
13665 case OPC_DMODU_G_2F:
13666 check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
13667 gen_loongson_integer(ctx, op1, rd, rs, rt);
13668 break;
13669 #endif
13670 default: /* Invalid */
13671 MIPS_INVAL("special2_legacy");
13672 gen_reserved_instruction(ctx);
13673 break;
13674 }
13675 }
13676
13677 static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
13678 {
13679 int rs, rt, rd, sa;
13680 uint32_t op1, op2;
13681 int16_t imm;
13682
13683 rs = (ctx->opcode >> 21) & 0x1f;
13684 rt = (ctx->opcode >> 16) & 0x1f;
13685 rd = (ctx->opcode >> 11) & 0x1f;
13686 sa = (ctx->opcode >> 6) & 0x1f;
13687 imm = (int16_t)ctx->opcode >> 7;
13688
13689 op1 = MASK_SPECIAL3(ctx->opcode);
13690 switch (op1) {
13691 case R6_OPC_PREF:
13692 if (rt >= 24) {
13693 /* hint codes 24-31 are reserved and signal RI */
13694 gen_reserved_instruction(ctx);
13695 }
13696 /* Treat as NOP. */
13697 break;
13698 case R6_OPC_CACHE:
13699 check_cp0_enabled(ctx);
13700 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
13701 gen_cache_operation(ctx, rt, rs, imm);
13702 }
13703 break;
13704 case R6_OPC_SC:
13705 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
13706 break;
13707 case R6_OPC_LL:
13708 gen_ld(ctx, op1, rt, rs, imm);
13709 break;
13710 case OPC_BSHFL:
13711 {
13712 if (rd == 0) {
13713 /* Treat as NOP. */
13714 break;
13715 }
13716 op2 = MASK_BSHFL(ctx->opcode);
13717 switch (op2) {
13718 case OPC_ALIGN:
13719 case OPC_ALIGN_1:
13720 case OPC_ALIGN_2:
13721 case OPC_ALIGN_3:
13722 gen_align(ctx, 32, rd, rs, rt, sa & 3);
13723 break;
13724 case OPC_BITSWAP:
13725 gen_bitswap(ctx, op2, rd, rt);
13726 break;
13727 }
13728 }
13729 break;
13730 #ifndef CONFIG_USER_ONLY
13731 case OPC_GINV:
13732 if (unlikely(ctx->gi <= 1)) {
13733 gen_reserved_instruction(ctx);
13734 }
13735 check_cp0_enabled(ctx);
13736 switch ((ctx->opcode >> 6) & 3) {
13737 case 0: /* GINVI */
13738 /* Treat as NOP. */
13739 break;
13740 case 2: /* GINVT */
13741 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2));
13742 break;
13743 default:
13744 gen_reserved_instruction(ctx);
13745 break;
13746 }
13747 break;
13748 #endif
13749 #if defined(TARGET_MIPS64)
13750 case R6_OPC_SCD:
13751 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
13752 break;
13753 case R6_OPC_LLD:
13754 gen_ld(ctx, op1, rt, rs, imm);
13755 break;
13756 case OPC_DBSHFL:
13757 check_mips_64(ctx);
13758 {
13759 if (rd == 0) {
13760 /* Treat as NOP. */
13761 break;
13762 }
13763 op2 = MASK_DBSHFL(ctx->opcode);
13764 switch (op2) {
13765 case OPC_DALIGN:
13766 case OPC_DALIGN_1:
13767 case OPC_DALIGN_2:
13768 case OPC_DALIGN_3:
13769 case OPC_DALIGN_4:
13770 case OPC_DALIGN_5:
13771 case OPC_DALIGN_6:
13772 case OPC_DALIGN_7:
13773 gen_align(ctx, 64, rd, rs, rt, sa & 7);
13774 break;
13775 case OPC_DBITSWAP:
13776 gen_bitswap(ctx, op2, rd, rt);
13777 break;
13778 }
13779
13780 }
13781 break;
13782 #endif
13783 default: /* Invalid */
13784 MIPS_INVAL("special3_r6");
13785 gen_reserved_instruction(ctx);
13786 break;
13787 }
13788 }
13789
13790 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
13791 {
13792 int rs, rt, rd;
13793 uint32_t op1, op2;
13794
13795 rs = (ctx->opcode >> 21) & 0x1f;
13796 rt = (ctx->opcode >> 16) & 0x1f;
13797 rd = (ctx->opcode >> 11) & 0x1f;
13798
13799 op1 = MASK_SPECIAL3(ctx->opcode);
13800 switch (op1) {
13801 case OPC_DIV_G_2E:
13802 case OPC_DIVU_G_2E:
13803 case OPC_MOD_G_2E:
13804 case OPC_MODU_G_2E:
13805 case OPC_MULT_G_2E:
13806 case OPC_MULTU_G_2E:
13807 /*
13808 * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
13809 * the same mask and op1.
13810 */
13811 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
13812 op2 = MASK_ADDUH_QB(ctx->opcode);
13813 switch (op2) {
13814 case OPC_ADDUH_QB:
13815 case OPC_ADDUH_R_QB:
13816 case OPC_ADDQH_PH:
13817 case OPC_ADDQH_R_PH:
13818 case OPC_ADDQH_W:
13819 case OPC_ADDQH_R_W:
13820 case OPC_SUBUH_QB:
13821 case OPC_SUBUH_R_QB:
13822 case OPC_SUBQH_PH:
13823 case OPC_SUBQH_R_PH:
13824 case OPC_SUBQH_W:
13825 case OPC_SUBQH_R_W:
13826 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
13827 break;
13828 case OPC_MUL_PH:
13829 case OPC_MUL_S_PH:
13830 case OPC_MULQ_S_W:
13831 case OPC_MULQ_RS_W:
13832 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
13833 break;
13834 default:
13835 MIPS_INVAL("MASK ADDUH.QB");
13836 gen_reserved_instruction(ctx);
13837 break;
13838 }
13839 } else if (ctx->insn_flags & INSN_LOONGSON2E) {
13840 gen_loongson_integer(ctx, op1, rd, rs, rt);
13841 } else {
13842 gen_reserved_instruction(ctx);
13843 }
13844 break;
13845 case OPC_LX_DSP:
13846 op2 = MASK_LX(ctx->opcode);
13847 switch (op2) {
13848 #if defined(TARGET_MIPS64)
13849 case OPC_LDX:
13850 #endif
13851 case OPC_LBUX:
13852 case OPC_LHX:
13853 case OPC_LWX:
13854 gen_mips_lx(ctx, op2, rd, rs, rt);
13855 break;
13856 default: /* Invalid */
13857 MIPS_INVAL("MASK LX");
13858 gen_reserved_instruction(ctx);
13859 break;
13860 }
13861 break;
13862 case OPC_ABSQ_S_PH_DSP:
13863 op2 = MASK_ABSQ_S_PH(ctx->opcode);
13864 switch (op2) {
13865 case OPC_ABSQ_S_QB:
13866 case OPC_ABSQ_S_PH:
13867 case OPC_ABSQ_S_W:
13868 case OPC_PRECEQ_W_PHL:
13869 case OPC_PRECEQ_W_PHR:
13870 case OPC_PRECEQU_PH_QBL:
13871 case OPC_PRECEQU_PH_QBR:
13872 case OPC_PRECEQU_PH_QBLA:
13873 case OPC_PRECEQU_PH_QBRA:
13874 case OPC_PRECEU_PH_QBL:
13875 case OPC_PRECEU_PH_QBR:
13876 case OPC_PRECEU_PH_QBLA:
13877 case OPC_PRECEU_PH_QBRA:
13878 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
13879 break;
13880 case OPC_BITREV:
13881 case OPC_REPL_QB:
13882 case OPC_REPLV_QB:
13883 case OPC_REPL_PH:
13884 case OPC_REPLV_PH:
13885 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
13886 break;
13887 default:
13888 MIPS_INVAL("MASK ABSQ_S.PH");
13889 gen_reserved_instruction(ctx);
13890 break;
13891 }
13892 break;
13893 case OPC_ADDU_QB_DSP:
13894 op2 = MASK_ADDU_QB(ctx->opcode);
13895 switch (op2) {
13896 case OPC_ADDQ_PH:
13897 case OPC_ADDQ_S_PH:
13898 case OPC_ADDQ_S_W:
13899 case OPC_ADDU_QB:
13900 case OPC_ADDU_S_QB:
13901 case OPC_ADDU_PH:
13902 case OPC_ADDU_S_PH:
13903 case OPC_SUBQ_PH:
13904 case OPC_SUBQ_S_PH:
13905 case OPC_SUBQ_S_W:
13906 case OPC_SUBU_QB:
13907 case OPC_SUBU_S_QB:
13908 case OPC_SUBU_PH:
13909 case OPC_SUBU_S_PH:
13910 case OPC_ADDSC:
13911 case OPC_ADDWC:
13912 case OPC_MODSUB:
13913 case OPC_RADDU_W_QB:
13914 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
13915 break;
13916 case OPC_MULEU_S_PH_QBL:
13917 case OPC_MULEU_S_PH_QBR:
13918 case OPC_MULQ_RS_PH:
13919 case OPC_MULEQ_S_W_PHL:
13920 case OPC_MULEQ_S_W_PHR:
13921 case OPC_MULQ_S_PH:
13922 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
13923 break;
13924 default: /* Invalid */
13925 MIPS_INVAL("MASK ADDU.QB");
13926 gen_reserved_instruction(ctx);
13927 break;
13928
13929 }
13930 break;
13931 case OPC_CMPU_EQ_QB_DSP:
13932 op2 = MASK_CMPU_EQ_QB(ctx->opcode);
13933 switch (op2) {
13934 case OPC_PRECR_SRA_PH_W:
13935 case OPC_PRECR_SRA_R_PH_W:
13936 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
13937 break;
13938 case OPC_PRECR_QB_PH:
13939 case OPC_PRECRQ_QB_PH:
13940 case OPC_PRECRQ_PH_W:
13941 case OPC_PRECRQ_RS_PH_W:
13942 case OPC_PRECRQU_S_QB_PH:
13943 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
13944 break;
13945 case OPC_CMPU_EQ_QB:
13946 case OPC_CMPU_LT_QB:
13947 case OPC_CMPU_LE_QB:
13948 case OPC_CMP_EQ_PH:
13949 case OPC_CMP_LT_PH:
13950 case OPC_CMP_LE_PH:
13951 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
13952 break;
13953 case OPC_CMPGU_EQ_QB:
13954 case OPC_CMPGU_LT_QB:
13955 case OPC_CMPGU_LE_QB:
13956 case OPC_CMPGDU_EQ_QB:
13957 case OPC_CMPGDU_LT_QB:
13958 case OPC_CMPGDU_LE_QB:
13959 case OPC_PICK_QB:
13960 case OPC_PICK_PH:
13961 case OPC_PACKRL_PH:
13962 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
13963 break;
13964 default: /* Invalid */
13965 MIPS_INVAL("MASK CMPU.EQ.QB");
13966 gen_reserved_instruction(ctx);
13967 break;
13968 }
13969 break;
13970 case OPC_SHLL_QB_DSP:
13971 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
13972 break;
13973 case OPC_DPA_W_PH_DSP:
13974 op2 = MASK_DPA_W_PH(ctx->opcode);
13975 switch (op2) {
13976 case OPC_DPAU_H_QBL:
13977 case OPC_DPAU_H_QBR:
13978 case OPC_DPSU_H_QBL:
13979 case OPC_DPSU_H_QBR:
13980 case OPC_DPA_W_PH:
13981 case OPC_DPAX_W_PH:
13982 case OPC_DPAQ_S_W_PH:
13983 case OPC_DPAQX_S_W_PH:
13984 case OPC_DPAQX_SA_W_PH:
13985 case OPC_DPS_W_PH:
13986 case OPC_DPSX_W_PH:
13987 case OPC_DPSQ_S_W_PH:
13988 case OPC_DPSQX_S_W_PH:
13989 case OPC_DPSQX_SA_W_PH:
13990 case OPC_MULSAQ_S_W_PH:
13991 case OPC_DPAQ_SA_L_W:
13992 case OPC_DPSQ_SA_L_W:
13993 case OPC_MAQ_S_W_PHL:
13994 case OPC_MAQ_S_W_PHR:
13995 case OPC_MAQ_SA_W_PHL:
13996 case OPC_MAQ_SA_W_PHR:
13997 case OPC_MULSA_W_PH:
13998 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
13999 break;
14000 default: /* Invalid */
14001 MIPS_INVAL("MASK DPAW.PH");
14002 gen_reserved_instruction(ctx);
14003 break;
14004 }
14005 break;
14006 case OPC_INSV_DSP:
14007 op2 = MASK_INSV(ctx->opcode);
14008 switch (op2) {
14009 case OPC_INSV:
14010 check_dsp(ctx);
14011 {
14012 TCGv t0, t1;
14013
14014 if (rt == 0) {
14015 break;
14016 }
14017
14018 t0 = tcg_temp_new();
14019 t1 = tcg_temp_new();
14020
14021 gen_load_gpr(t0, rt);
14022 gen_load_gpr(t1, rs);
14023
14024 gen_helper_insv(cpu_gpr[rt], tcg_env, t1, t0);
14025 break;
14026 }
14027 default: /* Invalid */
14028 MIPS_INVAL("MASK INSV");
14029 gen_reserved_instruction(ctx);
14030 break;
14031 }
14032 break;
14033 case OPC_APPEND_DSP:
14034 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
14035 break;
14036 case OPC_EXTR_W_DSP:
14037 op2 = MASK_EXTR_W(ctx->opcode);
14038 switch (op2) {
14039 case OPC_EXTR_W:
14040 case OPC_EXTR_R_W:
14041 case OPC_EXTR_RS_W:
14042 case OPC_EXTR_S_H:
14043 case OPC_EXTRV_S_H:
14044 case OPC_EXTRV_W:
14045 case OPC_EXTRV_R_W:
14046 case OPC_EXTRV_RS_W:
14047 case OPC_EXTP:
14048 case OPC_EXTPV:
14049 case OPC_EXTPDP:
14050 case OPC_EXTPDPV:
14051 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
14052 break;
14053 case OPC_RDDSP:
14054 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1);
14055 break;
14056 case OPC_SHILO:
14057 case OPC_SHILOV:
14058 case OPC_MTHLIP:
14059 case OPC_WRDSP:
14060 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
14061 break;
14062 default: /* Invalid */
14063 MIPS_INVAL("MASK EXTR.W");
14064 gen_reserved_instruction(ctx);
14065 break;
14066 }
14067 break;
14068 #if defined(TARGET_MIPS64)
14069 case OPC_DDIV_G_2E:
14070 case OPC_DDIVU_G_2E:
14071 case OPC_DMULT_G_2E:
14072 case OPC_DMULTU_G_2E:
14073 case OPC_DMOD_G_2E:
14074 case OPC_DMODU_G_2E:
14075 check_insn(ctx, INSN_LOONGSON2E);
14076 gen_loongson_integer(ctx, op1, rd, rs, rt);
14077 break;
14078 case OPC_ABSQ_S_QH_DSP:
14079 op2 = MASK_ABSQ_S_QH(ctx->opcode);
14080 switch (op2) {
14081 case OPC_PRECEQ_L_PWL:
14082 case OPC_PRECEQ_L_PWR:
14083 case OPC_PRECEQ_PW_QHL:
14084 case OPC_PRECEQ_PW_QHR:
14085 case OPC_PRECEQ_PW_QHLA:
14086 case OPC_PRECEQ_PW_QHRA:
14087 case OPC_PRECEQU_QH_OBL:
14088 case OPC_PRECEQU_QH_OBR:
14089 case OPC_PRECEQU_QH_OBLA:
14090 case OPC_PRECEQU_QH_OBRA:
14091 case OPC_PRECEU_QH_OBL:
14092 case OPC_PRECEU_QH_OBR:
14093 case OPC_PRECEU_QH_OBLA:
14094 case OPC_PRECEU_QH_OBRA:
14095 case OPC_ABSQ_S_OB:
14096 case OPC_ABSQ_S_PW:
14097 case OPC_ABSQ_S_QH:
14098 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14099 break;
14100 case OPC_REPL_OB:
14101 case OPC_REPL_PW:
14102 case OPC_REPL_QH:
14103 case OPC_REPLV_OB:
14104 case OPC_REPLV_PW:
14105 case OPC_REPLV_QH:
14106 gen_mipsdsp_bitinsn(ctx, op1, op2, rd, rt);
14107 break;
14108 default: /* Invalid */
14109 MIPS_INVAL("MASK ABSQ_S.QH");
14110 gen_reserved_instruction(ctx);
14111 break;
14112 }
14113 break;
14114 case OPC_ADDU_OB_DSP:
14115 op2 = MASK_ADDU_OB(ctx->opcode);
14116 switch (op2) {
14117 case OPC_RADDU_L_OB:
14118 case OPC_SUBQ_PW:
14119 case OPC_SUBQ_S_PW:
14120 case OPC_SUBQ_QH:
14121 case OPC_SUBQ_S_QH:
14122 case OPC_SUBU_OB:
14123 case OPC_SUBU_S_OB:
14124 case OPC_SUBU_QH:
14125 case OPC_SUBU_S_QH:
14126 case OPC_SUBUH_OB:
14127 case OPC_SUBUH_R_OB:
14128 case OPC_ADDQ_PW:
14129 case OPC_ADDQ_S_PW:
14130 case OPC_ADDQ_QH:
14131 case OPC_ADDQ_S_QH:
14132 case OPC_ADDU_OB:
14133 case OPC_ADDU_S_OB:
14134 case OPC_ADDU_QH:
14135 case OPC_ADDU_S_QH:
14136 case OPC_ADDUH_OB:
14137 case OPC_ADDUH_R_OB:
14138 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14139 break;
14140 case OPC_MULEQ_S_PW_QHL:
14141 case OPC_MULEQ_S_PW_QHR:
14142 case OPC_MULEU_S_QH_OBL:
14143 case OPC_MULEU_S_QH_OBR:
14144 case OPC_MULQ_RS_QH:
14145 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1);
14146 break;
14147 default: /* Invalid */
14148 MIPS_INVAL("MASK ADDU.OB");
14149 gen_reserved_instruction(ctx);
14150 break;
14151 }
14152 break;
14153 case OPC_CMPU_EQ_OB_DSP:
14154 op2 = MASK_CMPU_EQ_OB(ctx->opcode);
14155 switch (op2) {
14156 case OPC_PRECR_SRA_QH_PW:
14157 case OPC_PRECR_SRA_R_QH_PW:
14158 /* Return value is rt. */
14159 gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
14160 break;
14161 case OPC_PRECR_OB_QH:
14162 case OPC_PRECRQ_OB_QH:
14163 case OPC_PRECRQ_PW_L:
14164 case OPC_PRECRQ_QH_PW:
14165 case OPC_PRECRQ_RS_QH_PW:
14166 case OPC_PRECRQU_S_OB_QH:
14167 gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
14168 break;
14169 case OPC_CMPU_EQ_OB:
14170 case OPC_CMPU_LT_OB:
14171 case OPC_CMPU_LE_OB:
14172 case OPC_CMP_EQ_QH:
14173 case OPC_CMP_LT_QH:
14174 case OPC_CMP_LE_QH:
14175 case OPC_CMP_EQ_PW:
14176 case OPC_CMP_LT_PW:
14177 case OPC_CMP_LE_PW:
14178 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0);
14179 break;
14180 case OPC_CMPGDU_EQ_OB:
14181 case OPC_CMPGDU_LT_OB:
14182 case OPC_CMPGDU_LE_OB:
14183 case OPC_CMPGU_EQ_OB:
14184 case OPC_CMPGU_LT_OB:
14185 case OPC_CMPGU_LE_OB:
14186 case OPC_PACKRL_PW:
14187 case OPC_PICK_OB:
14188 case OPC_PICK_PW:
14189 case OPC_PICK_QH:
14190 gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1);
14191 break;
14192 default: /* Invalid */
14193 MIPS_INVAL("MASK CMPU_EQ.OB");
14194 gen_reserved_instruction(ctx);
14195 break;
14196 }
14197 break;
14198 case OPC_DAPPEND_DSP:
14199 gen_mipsdsp_append(env, ctx, op1, rt, rs, rd);
14200 break;
14201 case OPC_DEXTR_W_DSP:
14202 op2 = MASK_DEXTR_W(ctx->opcode);
14203 switch (op2) {
14204 case OPC_DEXTP:
14205 case OPC_DEXTPDP:
14206 case OPC_DEXTPDPV:
14207 case OPC_DEXTPV:
14208 case OPC_DEXTR_L:
14209 case OPC_DEXTR_R_L:
14210 case OPC_DEXTR_RS_L:
14211 case OPC_DEXTR_W:
14212 case OPC_DEXTR_R_W:
14213 case OPC_DEXTR_RS_W:
14214 case OPC_DEXTR_S_H:
14215 case OPC_DEXTRV_L:
14216 case OPC_DEXTRV_R_L:
14217 case OPC_DEXTRV_RS_L:
14218 case OPC_DEXTRV_S_H:
14219 case OPC_DEXTRV_W:
14220 case OPC_DEXTRV_R_W:
14221 case OPC_DEXTRV_RS_W:
14222 gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1);
14223 break;
14224 case OPC_DMTHLIP:
14225 case OPC_DSHILO:
14226 case OPC_DSHILOV:
14227 gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0);
14228 break;
14229 default: /* Invalid */
14230 MIPS_INVAL("MASK EXTR.W");
14231 gen_reserved_instruction(ctx);
14232 break;
14233 }
14234 break;
14235 case OPC_DPAQ_W_QH_DSP:
14236 op2 = MASK_DPAQ_W_QH(ctx->opcode);
14237 switch (op2) {
14238 case OPC_DPAU_H_OBL:
14239 case OPC_DPAU_H_OBR:
14240 case OPC_DPSU_H_OBL:
14241 case OPC_DPSU_H_OBR:
14242 case OPC_DPA_W_QH:
14243 case OPC_DPAQ_S_W_QH:
14244 case OPC_DPS_W_QH:
14245 case OPC_DPSQ_S_W_QH:
14246 case OPC_MULSAQ_S_W_QH:
14247 case OPC_DPAQ_SA_L_PW:
14248 case OPC_DPSQ_SA_L_PW:
14249 case OPC_MULSAQ_S_L_PW:
14250 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
14251 break;
14252 case OPC_MAQ_S_W_QHLL:
14253 case OPC_MAQ_S_W_QHLR:
14254 case OPC_MAQ_S_W_QHRL:
14255 case OPC_MAQ_S_W_QHRR:
14256 case OPC_MAQ_SA_W_QHLL:
14257 case OPC_MAQ_SA_W_QHLR:
14258 case OPC_MAQ_SA_W_QHRL:
14259 case OPC_MAQ_SA_W_QHRR:
14260 case OPC_MAQ_S_L_PWL:
14261 case OPC_MAQ_S_L_PWR:
14262 case OPC_DMADD:
14263 case OPC_DMADDU:
14264 case OPC_DMSUB:
14265 case OPC_DMSUBU:
14266 gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0);
14267 break;
14268 default: /* Invalid */
14269 MIPS_INVAL("MASK DPAQ.W.QH");
14270 gen_reserved_instruction(ctx);
14271 break;
14272 }
14273 break;
14274 case OPC_DINSV_DSP:
14275 op2 = MASK_INSV(ctx->opcode);
14276 switch (op2) {
14277 case OPC_DINSV:
14278 {
14279 TCGv t0, t1;
14280
14281 check_dsp(ctx);
14282
14283 if (rt == 0) {
14284 break;
14285 }
14286
14287 t0 = tcg_temp_new();
14288 t1 = tcg_temp_new();
14289
14290 gen_load_gpr(t0, rt);
14291 gen_load_gpr(t1, rs);
14292
14293 gen_helper_dinsv(cpu_gpr[rt], tcg_env, t1, t0);
14294 break;
14295 }
14296 default: /* Invalid */
14297 MIPS_INVAL("MASK DINSV");
14298 gen_reserved_instruction(ctx);
14299 break;
14300 }
14301 break;
14302 case OPC_SHLL_OB_DSP:
14303 gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
14304 break;
14305 #endif
14306 default: /* Invalid */
14307 MIPS_INVAL("special3_legacy");
14308 gen_reserved_instruction(ctx);
14309 break;
14310 }
14311 }
14312
14313
14314 #if defined(TARGET_MIPS64)
14315
14316 static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
14317 {
14318 uint32_t opc = MASK_MMI(ctx->opcode);
14319 int rs = extract32(ctx->opcode, 21, 5);
14320 int rt = extract32(ctx->opcode, 16, 5);
14321 int rd = extract32(ctx->opcode, 11, 5);
14322
14323 switch (opc) {
14324 case MMI_OPC_MULT1:
14325 case MMI_OPC_MULTU1:
14326 case MMI_OPC_MADD:
14327 case MMI_OPC_MADDU:
14328 case MMI_OPC_MADD1:
14329 case MMI_OPC_MADDU1:
14330 gen_mul_txx9(ctx, opc, rd, rs, rt);
14331 break;
14332 case MMI_OPC_DIV1:
14333 case MMI_OPC_DIVU1:
14334 gen_div1_tx79(ctx, opc, rs, rt);
14335 break;
14336 default:
14337 MIPS_INVAL("TX79 MMI class");
14338 gen_reserved_instruction(ctx);
14339 break;
14340 }
14341 }
14342
14343 static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
14344 {
14345 gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
14346 }
14347
14348 /*
14349 * The TX79-specific instruction Store Quadword
14350 *
14351 * +--------+-------+-------+------------------------+
14352 * | 011111 | base | rt | offset | SQ
14353 * +--------+-------+-------+------------------------+
14354 * 6 5 5 16
14355 *
14356 * has the same opcode as the Read Hardware Register instruction
14357 *
14358 * +--------+-------+-------+-------+-------+--------+
14359 * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
14360 * +--------+-------+-------+-------+-------+--------+
14361 * 6 5 5 5 5 6
14362 *
14363 * that is required, trapped and emulated by the Linux kernel. However, all
14364 * RDHWR encodings yield address error exceptions on the TX79 since the SQ
14365 * offset is odd. Therefore all valid SQ instructions can execute normally.
14366 * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
14367 * between SQ and RDHWR, as the Linux kernel does.
14368 */
14369 static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
14370 {
14371 int base = extract32(ctx->opcode, 21, 5);
14372 int rt = extract32(ctx->opcode, 16, 5);
14373 int offset = extract32(ctx->opcode, 0, 16);
14374
14375 #ifdef CONFIG_USER_ONLY
14376 uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
14377 uint32_t op2 = extract32(ctx->opcode, 6, 5);
14378
14379 if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
14380 int rd = extract32(ctx->opcode, 11, 5);
14381
14382 gen_rdhwr(ctx, rt, rd, 0);
14383 return;
14384 }
14385 #endif
14386
14387 gen_mmi_sq(ctx, base, rt, offset);
14388 }
14389
14390 #endif
14391
14392 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
14393 {
14394 int rs, rt, rd, sa;
14395 uint32_t op1, op2;
14396 int16_t imm;
14397
14398 rs = (ctx->opcode >> 21) & 0x1f;
14399 rt = (ctx->opcode >> 16) & 0x1f;
14400 rd = (ctx->opcode >> 11) & 0x1f;
14401 sa = (ctx->opcode >> 6) & 0x1f;
14402 imm = sextract32(ctx->opcode, 7, 9);
14403
14404 op1 = MASK_SPECIAL3(ctx->opcode);
14405
14406 /*
14407 * EVA loads and stores overlap Loongson 2E instructions decoded by
14408 * decode_opc_special3_legacy(), so be careful to allow their decoding when
14409 * EVA is absent.
14410 */
14411 if (ctx->eva) {
14412 switch (op1) {
14413 case OPC_LWLE:
14414 case OPC_LWRE:
14415 case OPC_LBUE:
14416 case OPC_LHUE:
14417 case OPC_LBE:
14418 case OPC_LHE:
14419 case OPC_LLE:
14420 case OPC_LWE:
14421 check_cp0_enabled(ctx);
14422 gen_ld(ctx, op1, rt, rs, imm);
14423 return;
14424 case OPC_SWLE:
14425 case OPC_SWRE:
14426 case OPC_SBE:
14427 case OPC_SHE:
14428 case OPC_SWE:
14429 check_cp0_enabled(ctx);
14430 gen_st(ctx, op1, rt, rs, imm);
14431 return;
14432 case OPC_SCE:
14433 check_cp0_enabled(ctx);
14434 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true);
14435 return;
14436 case OPC_CACHEE:
14437 check_eva(ctx);
14438 check_cp0_enabled(ctx);
14439 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
14440 gen_cache_operation(ctx, rt, rs, imm);
14441 }
14442 return;
14443 case OPC_PREFE:
14444 check_cp0_enabled(ctx);
14445 /* Treat as NOP. */
14446 return;
14447 }
14448 }
14449
14450 switch (op1) {
14451 case OPC_EXT:
14452 case OPC_INS:
14453 check_insn(ctx, ISA_MIPS_R2);
14454 gen_bitops(ctx, op1, rt, rs, sa, rd);
14455 break;
14456 case OPC_BSHFL:
14457 op2 = MASK_BSHFL(ctx->opcode);
14458 switch (op2) {
14459 case OPC_ALIGN:
14460 case OPC_ALIGN_1:
14461 case OPC_ALIGN_2:
14462 case OPC_ALIGN_3:
14463 case OPC_BITSWAP:
14464 check_insn(ctx, ISA_MIPS_R6);
14465 decode_opc_special3_r6(env, ctx);
14466 break;
14467 default:
14468 check_insn(ctx, ISA_MIPS_R2);
14469 gen_bshfl(ctx, op2, rt, rd);
14470 break;
14471 }
14472 break;
14473 #if defined(TARGET_MIPS64)
14474 case OPC_DEXTM:
14475 case OPC_DEXTU:
14476 case OPC_DEXT:
14477 case OPC_DINSM:
14478 case OPC_DINSU:
14479 case OPC_DINS:
14480 check_insn(ctx, ISA_MIPS_R2);
14481 check_mips_64(ctx);
14482 gen_bitops(ctx, op1, rt, rs, sa, rd);
14483 break;
14484 case OPC_DBSHFL:
14485 op2 = MASK_DBSHFL(ctx->opcode);
14486 switch (op2) {
14487 case OPC_DALIGN:
14488 case OPC_DALIGN_1:
14489 case OPC_DALIGN_2:
14490 case OPC_DALIGN_3:
14491 case OPC_DALIGN_4:
14492 case OPC_DALIGN_5:
14493 case OPC_DALIGN_6:
14494 case OPC_DALIGN_7:
14495 case OPC_DBITSWAP:
14496 check_insn(ctx, ISA_MIPS_R6);
14497 decode_opc_special3_r6(env, ctx);
14498 break;
14499 default:
14500 check_insn(ctx, ISA_MIPS_R2);
14501 check_mips_64(ctx);
14502 op2 = MASK_DBSHFL(ctx->opcode);
14503 gen_bshfl(ctx, op2, rt, rd);
14504 break;
14505 }
14506 break;
14507 #endif
14508 case OPC_RDHWR:
14509 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3));
14510 break;
14511 case OPC_FORK:
14512 check_mt(ctx);
14513 {
14514 TCGv t0 = tcg_temp_new();
14515 TCGv t1 = tcg_temp_new();
14516
14517 gen_load_gpr(t0, rt);
14518 gen_load_gpr(t1, rs);
14519 gen_helper_fork(t0, t1);
14520 }
14521 break;
14522 case OPC_YIELD:
14523 check_mt(ctx);
14524 {
14525 TCGv t0 = tcg_temp_new();
14526
14527 gen_load_gpr(t0, rs);
14528 gen_helper_yield(t0, tcg_env, t0);
14529 gen_store_gpr(t0, rd);
14530 }
14531 break;
14532 default:
14533 if (ctx->insn_flags & ISA_MIPS_R6) {
14534 decode_opc_special3_r6(env, ctx);
14535 } else {
14536 decode_opc_special3_legacy(env, ctx);
14537 }
14538 }
14539 }
14540
14541 static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
14542 {
14543 int32_t offset;
14544 int rs, rt, rd, sa;
14545 uint32_t op, op1;
14546 int16_t imm;
14547
14548 op = MASK_OP_MAJOR(ctx->opcode);
14549 rs = (ctx->opcode >> 21) & 0x1f;
14550 rt = (ctx->opcode >> 16) & 0x1f;
14551 rd = (ctx->opcode >> 11) & 0x1f;
14552 sa = (ctx->opcode >> 6) & 0x1f;
14553 imm = (int16_t)ctx->opcode;
14554 switch (op) {
14555 case OPC_SPECIAL:
14556 decode_opc_special(env, ctx);
14557 break;
14558 case OPC_SPECIAL2:
14559 #if defined(TARGET_MIPS64)
14560 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
14561 decode_mmi(env, ctx);
14562 break;
14563 }
14564 #endif
14565 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) {
14566 if (decode_ase_mxu(ctx, ctx->opcode)) {
14567 break;
14568 }
14569 }
14570 decode_opc_special2_legacy(env, ctx);
14571 break;
14572 case OPC_SPECIAL3:
14573 #if defined(TARGET_MIPS64)
14574 if (ctx->insn_flags & INSN_R5900) {
14575 decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
14576 } else {
14577 decode_opc_special3(env, ctx);
14578 }
14579 #else
14580 decode_opc_special3(env, ctx);
14581 #endif
14582 break;
14583 case OPC_REGIMM:
14584 op1 = MASK_REGIMM(ctx->opcode);
14585 switch (op1) {
14586 case OPC_BLTZL: /* REGIMM branches */
14587 case OPC_BGEZL:
14588 case OPC_BLTZALL:
14589 case OPC_BGEZALL:
14590 check_insn(ctx, ISA_MIPS2);
14591 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14592 /* Fallthrough */
14593 case OPC_BLTZ:
14594 case OPC_BGEZ:
14595 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
14596 break;
14597 case OPC_BLTZAL:
14598 case OPC_BGEZAL:
14599 if (ctx->insn_flags & ISA_MIPS_R6) {
14600 if (rs == 0) {
14601 /* OPC_NAL, OPC_BAL */
14602 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
14603 } else {
14604 gen_reserved_instruction(ctx);
14605 }
14606 } else {
14607 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
14608 }
14609 break;
14610 case OPC_TGEI: /* REGIMM traps */
14611 case OPC_TGEIU:
14612 case OPC_TLTI:
14613 case OPC_TLTIU:
14614 case OPC_TEQI:
14615 case OPC_TNEI:
14616 check_insn(ctx, ISA_MIPS2);
14617 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14618 gen_trap(ctx, op1, rs, -1, imm, 0);
14619 break;
14620 case OPC_SIGRIE:
14621 check_insn(ctx, ISA_MIPS_R6);
14622 gen_reserved_instruction(ctx);
14623 break;
14624 case OPC_SYNCI:
14625 check_insn(ctx, ISA_MIPS_R2);
14626 /*
14627 * Break the TB to be able to sync copied instructions
14628 * immediately.
14629 */
14630 ctx->base.is_jmp = DISAS_STOP;
14631 break;
14632 case OPC_BPOSGE32: /* MIPS DSP branch */
14633 #if defined(TARGET_MIPS64)
14634 case OPC_BPOSGE64:
14635 #endif
14636 check_dsp(ctx);
14637 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4);
14638 break;
14639 #if defined(TARGET_MIPS64)
14640 case OPC_DAHI:
14641 check_insn(ctx, ISA_MIPS_R6);
14642 check_mips_64(ctx);
14643 if (rs != 0) {
14644 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32);
14645 }
14646 break;
14647 case OPC_DATI:
14648 check_insn(ctx, ISA_MIPS_R6);
14649 check_mips_64(ctx);
14650 if (rs != 0) {
14651 tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48);
14652 }
14653 break;
14654 #endif
14655 default: /* Invalid */
14656 MIPS_INVAL("regimm");
14657 gen_reserved_instruction(ctx);
14658 break;
14659 }
14660 break;
14661 case OPC_CP0:
14662 check_cp0_enabled(ctx);
14663 op1 = MASK_CP0(ctx->opcode);
14664 switch (op1) {
14665 case OPC_MFC0:
14666 case OPC_MTC0:
14667 case OPC_MFTR:
14668 case OPC_MTTR:
14669 case OPC_MFHC0:
14670 case OPC_MTHC0:
14671 #if defined(TARGET_MIPS64)
14672 case OPC_DMFC0:
14673 case OPC_DMTC0:
14674 #endif
14675 #ifndef CONFIG_USER_ONLY
14676 gen_cp0(env, ctx, op1, rt, rd);
14677 #endif /* !CONFIG_USER_ONLY */
14678 break;
14679 case OPC_C0:
14680 case OPC_C0_1:
14681 case OPC_C0_2:
14682 case OPC_C0_3:
14683 case OPC_C0_4:
14684 case OPC_C0_5:
14685 case OPC_C0_6:
14686 case OPC_C0_7:
14687 case OPC_C0_8:
14688 case OPC_C0_9:
14689 case OPC_C0_A:
14690 case OPC_C0_B:
14691 case OPC_C0_C:
14692 case OPC_C0_D:
14693 case OPC_C0_E:
14694 case OPC_C0_F:
14695 #ifndef CONFIG_USER_ONLY
14696 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
14697 #endif /* !CONFIG_USER_ONLY */
14698 break;
14699 case OPC_MFMC0:
14700 #ifndef CONFIG_USER_ONLY
14701 {
14702 uint32_t op2;
14703 TCGv t0 = tcg_temp_new();
14704
14705 op2 = MASK_MFMC0(ctx->opcode);
14706 switch (op2) {
14707 case OPC_DMT:
14708 check_cp0_mt(ctx);
14709 gen_helper_dmt(t0);
14710 gen_store_gpr(t0, rt);
14711 break;
14712 case OPC_EMT:
14713 check_cp0_mt(ctx);
14714 gen_helper_emt(t0);
14715 gen_store_gpr(t0, rt);
14716 break;
14717 case OPC_DVPE:
14718 check_cp0_mt(ctx);
14719 gen_helper_dvpe(t0, tcg_env);
14720 gen_store_gpr(t0, rt);
14721 break;
14722 case OPC_EVPE:
14723 check_cp0_mt(ctx);
14724 gen_helper_evpe(t0, tcg_env);
14725 gen_store_gpr(t0, rt);
14726 break;
14727 case OPC_DVP:
14728 check_insn(ctx, ISA_MIPS_R6);
14729 if (ctx->vp) {
14730 gen_helper_dvp(t0, tcg_env);
14731 gen_store_gpr(t0, rt);
14732 }
14733 break;
14734 case OPC_EVP:
14735 check_insn(ctx, ISA_MIPS_R6);
14736 if (ctx->vp) {
14737 gen_helper_evp(t0, tcg_env);
14738 gen_store_gpr(t0, rt);
14739 }
14740 break;
14741 case OPC_DI:
14742 check_insn(ctx, ISA_MIPS_R2);
14743 save_cpu_state(ctx, 1);
14744 gen_helper_di(t0, tcg_env);
14745 gen_store_gpr(t0, rt);
14746 /*
14747 * Stop translation as we may have switched
14748 * the execution mode.
14749 */
14750 ctx->base.is_jmp = DISAS_STOP;
14751 break;
14752 case OPC_EI:
14753 check_insn(ctx, ISA_MIPS_R2);
14754 save_cpu_state(ctx, 1);
14755 gen_helper_ei(t0, tcg_env);
14756 gen_store_gpr(t0, rt);
14757 /*
14758 * DISAS_STOP isn't sufficient, we need to ensure we break
14759 * out of translated code to check for pending interrupts.
14760 */
14761 gen_save_pc(ctx->base.pc_next + 4);
14762 ctx->base.is_jmp = DISAS_EXIT;
14763 break;
14764 default: /* Invalid */
14765 MIPS_INVAL("mfmc0");
14766 gen_reserved_instruction(ctx);
14767 break;
14768 }
14769 }
14770 #endif /* !CONFIG_USER_ONLY */
14771 break;
14772 case OPC_RDPGPR:
14773 check_insn(ctx, ISA_MIPS_R2);
14774 gen_load_srsgpr(rt, rd);
14775 break;
14776 case OPC_WRPGPR:
14777 check_insn(ctx, ISA_MIPS_R2);
14778 gen_store_srsgpr(rt, rd);
14779 break;
14780 default:
14781 MIPS_INVAL("cp0");
14782 gen_reserved_instruction(ctx);
14783 break;
14784 }
14785 break;
14786 case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
14787 if (ctx->insn_flags & ISA_MIPS_R6) {
14788 /* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
14789 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
14790 } else {
14791 /* OPC_ADDI */
14792 /* Arithmetic with immediate opcode */
14793 gen_arith_imm(ctx, op, rt, rs, imm);
14794 }
14795 break;
14796 case OPC_ADDIU:
14797 gen_arith_imm(ctx, op, rt, rs, imm);
14798 break;
14799 case OPC_SLTI: /* Set on less than with immediate opcode */
14800 case OPC_SLTIU:
14801 gen_slt_imm(ctx, op, rt, rs, imm);
14802 break;
14803 case OPC_ANDI: /* Arithmetic with immediate opcode */
14804 case OPC_LUI: /* OPC_AUI */
14805 case OPC_ORI:
14806 case OPC_XORI:
14807 gen_logic_imm(ctx, op, rt, rs, imm);
14808 break;
14809 case OPC_J: /* Jump */
14810 case OPC_JAL:
14811 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
14812 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
14813 break;
14814 /* Branch */
14815 case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
14816 if (ctx->insn_flags & ISA_MIPS_R6) {
14817 if (rt == 0) {
14818 gen_reserved_instruction(ctx);
14819 break;
14820 }
14821 /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
14822 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
14823 } else {
14824 /* OPC_BLEZL */
14825 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
14826 }
14827 break;
14828 case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
14829 if (ctx->insn_flags & ISA_MIPS_R6) {
14830 if (rt == 0) {
14831 gen_reserved_instruction(ctx);
14832 break;
14833 }
14834 /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
14835 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
14836 } else {
14837 /* OPC_BGTZL */
14838 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
14839 }
14840 break;
14841 case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
14842 if (rt == 0) {
14843 /* OPC_BLEZ */
14844 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
14845 } else {
14846 check_insn(ctx, ISA_MIPS_R6);
14847 /* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
14848 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
14849 }
14850 break;
14851 case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
14852 if (rt == 0) {
14853 /* OPC_BGTZ */
14854 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
14855 } else {
14856 check_insn(ctx, ISA_MIPS_R6);
14857 /* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
14858 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
14859 }
14860 break;
14861 case OPC_BEQL:
14862 case OPC_BNEL:
14863 check_insn(ctx, ISA_MIPS2);
14864 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14865 /* Fallthrough */
14866 case OPC_BEQ:
14867 case OPC_BNE:
14868 gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
14869 break;
14870 case OPC_LL: /* Load and stores */
14871 check_insn(ctx, ISA_MIPS2);
14872 if (ctx->insn_flags & INSN_R5900) {
14873 check_insn_opc_user_only(ctx, INSN_R5900);
14874 }
14875 /* Fallthrough */
14876 case OPC_LWL:
14877 case OPC_LWR:
14878 case OPC_LB:
14879 case OPC_LH:
14880 case OPC_LW:
14881 case OPC_LWPC:
14882 case OPC_LBU:
14883 case OPC_LHU:
14884 gen_ld(ctx, op, rt, rs, imm);
14885 break;
14886 case OPC_SWL:
14887 case OPC_SWR:
14888 case OPC_SB:
14889 case OPC_SH:
14890 case OPC_SW:
14891 gen_st(ctx, op, rt, rs, imm);
14892 break;
14893 case OPC_SC:
14894 check_insn(ctx, ISA_MIPS2);
14895 if (ctx->insn_flags & INSN_R5900) {
14896 check_insn_opc_user_only(ctx, INSN_R5900);
14897 }
14898 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
14899 break;
14900 case OPC_CACHE:
14901 check_cp0_enabled(ctx);
14902 check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
14903 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
14904 gen_cache_operation(ctx, rt, rs, imm);
14905 }
14906 /* Treat as NOP. */
14907 break;
14908 case OPC_PREF:
14909 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900);
14910 /* Treat as NOP. */
14911 break;
14912
14913 /* Floating point (COP1). */
14914 case OPC_LWC1:
14915 case OPC_LDC1:
14916 case OPC_SWC1:
14917 case OPC_SDC1:
14918 gen_cop1_ldst(ctx, op, rt, rs, imm);
14919 break;
14920
14921 case OPC_CP1:
14922 op1 = MASK_CP1(ctx->opcode);
14923
14924 switch (op1) {
14925 case OPC_MFHC1:
14926 case OPC_MTHC1:
14927 check_cp1_enabled(ctx);
14928 check_insn(ctx, ISA_MIPS_R2);
14929 /* fall through */
14930 case OPC_MFC1:
14931 case OPC_CFC1:
14932 case OPC_MTC1:
14933 case OPC_CTC1:
14934 check_cp1_enabled(ctx);
14935 gen_cp1(ctx, op1, rt, rd);
14936 break;
14937 #if defined(TARGET_MIPS64)
14938 case OPC_DMFC1:
14939 case OPC_DMTC1:
14940 check_cp1_enabled(ctx);
14941 check_insn(ctx, ISA_MIPS3);
14942 check_mips_64(ctx);
14943 gen_cp1(ctx, op1, rt, rd);
14944 break;
14945 #endif
14946 case OPC_BC1EQZ: /* OPC_BC1ANY2 */
14947 check_cp1_enabled(ctx);
14948 if (ctx->insn_flags & ISA_MIPS_R6) {
14949 /* OPC_BC1EQZ */
14950 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
14951 rt, imm << 2, 4);
14952 } else {
14953 /* OPC_BC1ANY2 */
14954 check_cop1x(ctx);
14955 check_insn(ctx, ASE_MIPS3D);
14956 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
14957 (rt >> 2) & 0x7, imm << 2);
14958 }
14959 break;
14960 case OPC_BC1NEZ:
14961 check_cp1_enabled(ctx);
14962 check_insn(ctx, ISA_MIPS_R6);
14963 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode),
14964 rt, imm << 2, 4);
14965 break;
14966 case OPC_BC1ANY4:
14967 check_cp1_enabled(ctx);
14968 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14969 check_cop1x(ctx);
14970 check_insn(ctx, ASE_MIPS3D);
14971 /* fall through */
14972 case OPC_BC1:
14973 check_cp1_enabled(ctx);
14974 check_insn_opc_removed(ctx, ISA_MIPS_R6);
14975 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
14976 (rt >> 2) & 0x7, imm << 2);
14977 break;
14978 case OPC_PS_FMT:
14979 check_ps(ctx);
14980 /* fall through */
14981 case OPC_S_FMT:
14982 case OPC_D_FMT:
14983 check_cp1_enabled(ctx);
14984 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
14985 (imm >> 8) & 0x7);
14986 break;
14987 case OPC_W_FMT:
14988 case OPC_L_FMT:
14989 {
14990 int r6_op = ctx->opcode & FOP(0x3f, 0x1f);
14991 check_cp1_enabled(ctx);
14992 if (ctx->insn_flags & ISA_MIPS_R6) {
14993 switch (r6_op) {
14994 case R6_OPC_CMP_AF_S:
14995 case R6_OPC_CMP_UN_S:
14996 case R6_OPC_CMP_EQ_S:
14997 case R6_OPC_CMP_UEQ_S:
14998 case R6_OPC_CMP_LT_S:
14999 case R6_OPC_CMP_ULT_S:
15000 case R6_OPC_CMP_LE_S:
15001 case R6_OPC_CMP_ULE_S:
15002 case R6_OPC_CMP_SAF_S:
15003 case R6_OPC_CMP_SUN_S:
15004 case R6_OPC_CMP_SEQ_S:
15005 case R6_OPC_CMP_SEUQ_S:
15006 case R6_OPC_CMP_SLT_S:
15007 case R6_OPC_CMP_SULT_S:
15008 case R6_OPC_CMP_SLE_S:
15009 case R6_OPC_CMP_SULE_S:
15010 case R6_OPC_CMP_OR_S:
15011 case R6_OPC_CMP_UNE_S:
15012 case R6_OPC_CMP_NE_S:
15013 case R6_OPC_CMP_SOR_S:
15014 case R6_OPC_CMP_SUNE_S:
15015 case R6_OPC_CMP_SNE_S:
15016 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa);
15017 break;
15018 case R6_OPC_CMP_AF_D:
15019 case R6_OPC_CMP_UN_D:
15020 case R6_OPC_CMP_EQ_D:
15021 case R6_OPC_CMP_UEQ_D:
15022 case R6_OPC_CMP_LT_D:
15023 case R6_OPC_CMP_ULT_D:
15024 case R6_OPC_CMP_LE_D:
15025 case R6_OPC_CMP_ULE_D:
15026 case R6_OPC_CMP_SAF_D:
15027 case R6_OPC_CMP_SUN_D:
15028 case R6_OPC_CMP_SEQ_D:
15029 case R6_OPC_CMP_SEUQ_D:
15030 case R6_OPC_CMP_SLT_D:
15031 case R6_OPC_CMP_SULT_D:
15032 case R6_OPC_CMP_SLE_D:
15033 case R6_OPC_CMP_SULE_D:
15034 case R6_OPC_CMP_OR_D:
15035 case R6_OPC_CMP_UNE_D:
15036 case R6_OPC_CMP_NE_D:
15037 case R6_OPC_CMP_SOR_D:
15038 case R6_OPC_CMP_SUNE_D:
15039 case R6_OPC_CMP_SNE_D:
15040 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa);
15041 break;
15042 default:
15043 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
15044 rt, rd, sa, (imm >> 8) & 0x7);
15045
15046 break;
15047 }
15048 } else {
15049 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
15050 (imm >> 8) & 0x7);
15051 }
15052 break;
15053 }
15054 default:
15055 MIPS_INVAL("cp1");
15056 gen_reserved_instruction(ctx);
15057 break;
15058 }
15059 break;
15060
15061 /* Compact branches [R6] and COP2 [non-R6] */
15062 case OPC_BC: /* OPC_LWC2 */
15063 case OPC_BALC: /* OPC_SWC2 */
15064 if (ctx->insn_flags & ISA_MIPS_R6) {
15065 /* OPC_BC, OPC_BALC */
15066 gen_compute_compact_branch(ctx, op, 0, 0,
15067 sextract32(ctx->opcode << 2, 0, 28));
15068 } else if (ctx->insn_flags & ASE_LEXT) {
15069 gen_loongson_lswc2(ctx, rt, rs, rd);
15070 } else {
15071 /* OPC_LWC2, OPC_SWC2 */
15072 /* COP2: Not implemented. */
15073 generate_exception_err(ctx, EXCP_CpU, 2);
15074 }
15075 break;
15076 case OPC_BEQZC: /* OPC_JIC, OPC_LDC2 */
15077 case OPC_BNEZC: /* OPC_JIALC, OPC_SDC2 */
15078 if (ctx->insn_flags & ISA_MIPS_R6) {
15079 if (rs != 0) {
15080 /* OPC_BEQZC, OPC_BNEZC */
15081 gen_compute_compact_branch(ctx, op, rs, 0,
15082 sextract32(ctx->opcode << 2, 0, 23));
15083 } else {
15084 /* OPC_JIC, OPC_JIALC */
15085 gen_compute_compact_branch(ctx, op, 0, rt, imm);
15086 }
15087 } else if (ctx->insn_flags & ASE_LEXT) {
15088 gen_loongson_lsdc2(ctx, rt, rs, rd);
15089 } else {
15090 /* OPC_LWC2, OPC_SWC2 */
15091 /* COP2: Not implemented. */
15092 generate_exception_err(ctx, EXCP_CpU, 2);
15093 }
15094 break;
15095 case OPC_CP2:
15096 check_insn(ctx, ASE_LMMI);
15097 /* Note that these instructions use different fields. */
15098 gen_loongson_multimedia(ctx, sa, rd, rt);
15099 break;
15100
15101 case OPC_CP3:
15102 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
15103 check_cp1_enabled(ctx);
15104 op1 = MASK_CP3(ctx->opcode);
15105 switch (op1) {
15106 case OPC_LUXC1:
15107 case OPC_SUXC1:
15108 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
15109 /* Fallthrough */
15110 case OPC_LWXC1:
15111 case OPC_LDXC1:
15112 case OPC_SWXC1:
15113 case OPC_SDXC1:
15114 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
15115 gen_flt3_ldst(ctx, op1, sa, rd, rs, rt);
15116 break;
15117 case OPC_PREFX:
15118 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
15119 /* Treat as NOP. */
15120 break;
15121 case OPC_ALNV_PS:
15122 check_insn(ctx, ISA_MIPS5 | ISA_MIPS_R2);
15123 /* Fallthrough */
15124 case OPC_MADD_S:
15125 case OPC_MADD_D:
15126 case OPC_MADD_PS:
15127 case OPC_MSUB_S:
15128 case OPC_MSUB_D:
15129 case OPC_MSUB_PS:
15130 case OPC_NMADD_S:
15131 case OPC_NMADD_D:
15132 case OPC_NMADD_PS:
15133 case OPC_NMSUB_S:
15134 case OPC_NMSUB_D:
15135 case OPC_NMSUB_PS:
15136 check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R2);
15137 gen_flt3_arith(ctx, op1, sa, rs, rd, rt);
15138 break;
15139 default:
15140 MIPS_INVAL("cp3");
15141 gen_reserved_instruction(ctx);
15142 break;
15143 }
15144 } else {
15145 generate_exception_err(ctx, EXCP_CpU, 1);
15146 }
15147 break;
15148
15149 #if defined(TARGET_MIPS64)
15150 /* MIPS64 opcodes */
15151 case OPC_LLD:
15152 if (ctx->insn_flags & INSN_R5900) {
15153 check_insn_opc_user_only(ctx, INSN_R5900);
15154 }
15155 /* fall through */
15156 case OPC_LDL:
15157 case OPC_LDR:
15158 case OPC_LWU:
15159 case OPC_LD:
15160 check_insn(ctx, ISA_MIPS3);
15161 check_mips_64(ctx);
15162 gen_ld(ctx, op, rt, rs, imm);
15163 break;
15164 case OPC_SDL:
15165 case OPC_SDR:
15166 case OPC_SD:
15167 check_insn(ctx, ISA_MIPS3);
15168 check_mips_64(ctx);
15169 gen_st(ctx, op, rt, rs, imm);
15170 break;
15171 case OPC_SCD:
15172 check_insn(ctx, ISA_MIPS3);
15173 if (ctx->insn_flags & INSN_R5900) {
15174 check_insn_opc_user_only(ctx, INSN_R5900);
15175 }
15176 check_mips_64(ctx);
15177 gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
15178 break;
15179 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
15180 if (ctx->insn_flags & ISA_MIPS_R6) {
15181 /* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
15182 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15183 } else {
15184 /* OPC_DADDI */
15185 check_insn(ctx, ISA_MIPS3);
15186 check_mips_64(ctx);
15187 gen_arith_imm(ctx, op, rt, rs, imm);
15188 }
15189 break;
15190 case OPC_DADDIU:
15191 check_insn(ctx, ISA_MIPS3);
15192 check_mips_64(ctx);
15193 gen_arith_imm(ctx, op, rt, rs, imm);
15194 break;
15195 #else
15196 case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
15197 if (ctx->insn_flags & ISA_MIPS_R6) {
15198 gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
15199 } else {
15200 MIPS_INVAL("major opcode");
15201 gen_reserved_instruction(ctx);
15202 }
15203 break;
15204 #endif
15205 case OPC_DAUI: /* OPC_JALX */
15206 if (ctx->insn_flags & ISA_MIPS_R6) {
15207 #if defined(TARGET_MIPS64)
15208 /* OPC_DAUI */
15209 check_mips_64(ctx);
15210 if (rs == 0) {
15211 generate_exception(ctx, EXCP_RI);
15212 } else if (rt != 0) {
15213 TCGv t0 = tcg_temp_new();
15214 gen_load_gpr(t0, rs);
15215 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
15216 }
15217 #else
15218 gen_reserved_instruction(ctx);
15219 MIPS_INVAL("major opcode");
15220 #endif
15221 } else {
15222 /* OPC_JALX */
15223 check_insn(ctx, ASE_MIPS16 | ASE_MICROMIPS);
15224 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
15225 gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
15226 }
15227 break;
15228 case OPC_MDMX:
15229 /* MDMX: Not implemented. */
15230 break;
15231 case OPC_PCREL:
15232 check_insn(ctx, ISA_MIPS_R6);
15233 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs);
15234 break;
15235 default: /* Invalid */
15236 MIPS_INVAL("major opcode");
15237 return false;
15238 }
15239 return true;
15240 }
15241
15242 static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
15243 {
15244 /* make sure instructions are on a word boundary */
15245 if (ctx->base.pc_next & 0x3) {
15246 env->CP0_BadVAddr = ctx->base.pc_next;
15247 generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
15248 return;
15249 }
15250
15251 /* Handle blikely not taken case */
15252 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
15253 TCGLabel *l1 = gen_new_label();
15254
15255 tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
15256 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
15257 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
15258 gen_set_label(l1);
15259 }
15260
15261 /* Transition to the auto-generated decoder. */
15262
15263 /* Vendor specific extensions */
15264 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) {
15265 return;
15266 }
15267 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
15268 return;
15269 }
15270 #if defined(TARGET_MIPS64)
15271 if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) {
15272 return;
15273 }
15274 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
15275 return;
15276 }
15277 #endif
15278
15279 /* ISA extensions */
15280 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
15281 return;
15282 }
15283
15284 /* ISA (from latest to oldest) */
15285 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
15286 return;
15287 }
15288
15289 if (decode_opc_legacy(env, ctx)) {
15290 return;
15291 }
15292
15293 gen_reserved_instruction(ctx);
15294 }
15295
15296 static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
15297 {
15298 DisasContext *ctx = container_of(dcbase, DisasContext, base);
15299 CPUMIPSState *env = cpu_env(cs);
15300
15301 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
15302 ctx->saved_pc = -1;
15303 ctx->insn_flags = env->insn_flags;
15304 ctx->CP0_Config0 = env->CP0_Config0;
15305 ctx->CP0_Config1 = env->CP0_Config1;
15306 ctx->CP0_Config2 = env->CP0_Config2;
15307 ctx->CP0_Config3 = env->CP0_Config3;
15308 ctx->CP0_Config5 = env->CP0_Config5;
15309 ctx->btarget = 0;
15310 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff;
15311 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1;
15312 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3;
15313 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1;
15314 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1;
15315 ctx->PAMask = env->PAMask;
15316 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1;
15317 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1;
15318 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1;
15319 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;
15320 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;
15321 /* Restore delay slot state from the tb context. */
15322 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */
15323 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;
15324 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||
15325 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));
15326 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1;
15327 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
15328 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
15329 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
15330 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1;
15331 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3;
15332 restore_cpu_state(env, ctx);
15333 #ifdef CONFIG_USER_ONLY
15334 ctx->mem_idx = MIPS_HFLAG_UM;
15335 #else
15336 ctx->mem_idx = hflags_mmu_index(ctx->hflags);
15337 #endif
15338 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
15339 (ctx->insn_flags & (ISA_MIPS_R6 |
15340 INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
15341
15342 /*
15343 * Execute a branch and its delay slot as a single instruction.
15344 * This is what GDB expects and is consistent with what the
15345 * hardware does (e.g. if a delay slot instruction faults, the
15346 * reported PC is the PC of the branch).
15347 */
15348 if ((tb_cflags(ctx->base.tb) & CF_SINGLE_STEP) &&
15349 (ctx->hflags & MIPS_HFLAG_BMASK)) {
15350 ctx->base.max_insns = 2;
15351 }
15352
15353 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
15354 ctx->hflags);
15355 }
15356
15357 static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
15358 {
15359 }
15360
15361 static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
15362 {
15363 DisasContext *ctx = container_of(dcbase, DisasContext, base);
15364
15365 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
15366 ctx->btarget);
15367 }
15368
15369 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
15370 {
15371 CPUMIPSState *env = cpu_env(cs);
15372 DisasContext *ctx = container_of(dcbase, DisasContext, base);
15373 int insn_bytes;
15374 int is_slot;
15375
15376 is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
15377 if (ctx->insn_flags & ISA_NANOMIPS32) {
15378 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
15379 insn_bytes = decode_isa_nanomips(env, ctx);
15380 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
15381 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
15382 insn_bytes = 4;
15383 decode_opc(env, ctx);
15384 } else if (ctx->insn_flags & ASE_MICROMIPS) {
15385 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
15386 insn_bytes = decode_isa_micromips(env, ctx);
15387 } else if (ctx->insn_flags & ASE_MIPS16) {
15388 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
15389 insn_bytes = decode_ase_mips16e(env, ctx);
15390 } else {
15391 gen_reserved_instruction(ctx);
15392 g_assert(ctx->base.is_jmp == DISAS_NORETURN);
15393 return;
15394 }
15395
15396 if (ctx->hflags & MIPS_HFLAG_BMASK) {
15397 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
15398 MIPS_HFLAG_FBNSLOT))) {
15399 /*
15400 * Force to generate branch as there is neither delay nor
15401 * forbidden slot.
15402 */
15403 is_slot = 1;
15404 }
15405 if ((ctx->hflags & MIPS_HFLAG_M16) &&
15406 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
15407 /*
15408 * Force to generate branch as microMIPS R6 doesn't restrict
15409 * branches in the forbidden slot.
15410 */
15411 is_slot = 1;
15412 }
15413 }
15414 if (is_slot) {
15415 gen_branch(ctx, insn_bytes);
15416 }
15417 if (ctx->base.is_jmp == DISAS_SEMIHOST) {
15418 generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes);
15419 }
15420 ctx->base.pc_next += insn_bytes;
15421
15422 if (ctx->base.is_jmp != DISAS_NEXT) {
15423 return;
15424 }
15425
15426 /*
15427 * End the TB on (most) page crossings.
15428 * See mips_tr_init_disas_context about single-stepping a branch
15429 * together with its delay slot.
15430 */
15431 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
15432 && !(tb_cflags(ctx->base.tb) & CF_SINGLE_STEP)) {
15433 ctx->base.is_jmp = DISAS_TOO_MANY;
15434 }
15435 }
15436
15437 static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
15438 {
15439 DisasContext *ctx = container_of(dcbase, DisasContext, base);
15440
15441 switch (ctx->base.is_jmp) {
15442 case DISAS_STOP:
15443 gen_save_pc(ctx->base.pc_next);
15444 tcg_gen_lookup_and_goto_ptr();
15445 break;
15446 case DISAS_NEXT:
15447 case DISAS_TOO_MANY:
15448 save_cpu_state(ctx, 0);
15449 gen_goto_tb(ctx, 0, ctx->base.pc_next);
15450 break;
15451 case DISAS_EXIT:
15452 tcg_gen_exit_tb(NULL, 0);
15453 break;
15454 case DISAS_NORETURN:
15455 break;
15456 default:
15457 g_assert_not_reached();
15458 }
15459 }
15460
15461 static const TranslatorOps mips_tr_ops = {
15462 .init_disas_context = mips_tr_init_disas_context,
15463 .tb_start = mips_tr_tb_start,
15464 .insn_start = mips_tr_insn_start,
15465 .translate_insn = mips_tr_translate_insn,
15466 .tb_stop = mips_tr_tb_stop,
15467 };
15468
15469 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
15470 vaddr pc, void *host_pc)
15471 {
15472 DisasContext ctx;
15473
15474 translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base);
15475 }
15476
15477 void mips_tcg_init(void)
15478 {
15479 cpu_gpr[0] = NULL;
15480 for (unsigned i = 1; i < 32; i++)
15481 cpu_gpr[i] = tcg_global_mem_new(tcg_env,
15482 offsetof(CPUMIPSState,
15483 active_tc.gpr[i]),
15484 regnames[i]);
15485 #if defined(TARGET_MIPS64)
15486 cpu_gpr_hi[0] = NULL;
15487
15488 for (unsigned i = 1; i < 32; i++) {
15489 g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]);
15490
15491 cpu_gpr_hi[i] = tcg_global_mem_new_i64(tcg_env,
15492 offsetof(CPUMIPSState,
15493 active_tc.gpr_hi[i]),
15494 rname);
15495 }
15496 #endif /* !TARGET_MIPS64 */
15497 for (unsigned i = 0; i < 32; i++) {
15498 int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
15499
15500 fpu_f64[i] = tcg_global_mem_new_i64(tcg_env, off, fregnames[i]);
15501 }
15502 msa_translate_init();
15503 cpu_PC = tcg_global_mem_new(tcg_env,
15504 offsetof(CPUMIPSState, active_tc.PC), "PC");
15505 for (unsigned i = 0; i < MIPS_DSP_ACC; i++) {
15506 cpu_HI[i] = tcg_global_mem_new(tcg_env,
15507 offsetof(CPUMIPSState, active_tc.HI[i]),
15508 regnames_HI[i]);
15509 cpu_LO[i] = tcg_global_mem_new(tcg_env,
15510 offsetof(CPUMIPSState, active_tc.LO[i]),
15511 regnames_LO[i]);
15512 }
15513 cpu_dspctrl = tcg_global_mem_new(tcg_env,
15514 offsetof(CPUMIPSState,
15515 active_tc.DSPControl),
15516 "DSPControl");
15517 bcond = tcg_global_mem_new(tcg_env,
15518 offsetof(CPUMIPSState, bcond), "bcond");
15519 btarget = tcg_global_mem_new(tcg_env,
15520 offsetof(CPUMIPSState, btarget), "btarget");
15521 hflags = tcg_global_mem_new_i32(tcg_env,
15522 offsetof(CPUMIPSState, hflags), "hflags");
15523
15524 fpu_fcr0 = tcg_global_mem_new_i32(tcg_env,
15525 offsetof(CPUMIPSState, active_fpu.fcr0),
15526 "fcr0");
15527 fpu_fcr31 = tcg_global_mem_new_i32(tcg_env,
15528 offsetof(CPUMIPSState, active_fpu.fcr31),
15529 "fcr31");
15530 cpu_lladdr = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, lladdr),
15531 "lladdr");
15532 cpu_llval = tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llval),
15533 "llval");
15534
15535 if (TARGET_LONG_BITS == 32) {
15536 mxu_translate_init();
15537 }
15538 }
15539
15540 void mips_restore_state_to_opc(CPUState *cs,
15541 const TranslationBlock *tb,
15542 const uint64_t *data)
15543 {
15544 CPUMIPSState *env = cpu_env(cs);
15545
15546 env->active_tc.PC = data[0];
15547 env->hflags &= ~MIPS_HFLAG_BMASK;
15548 env->hflags |= data[1];
15549 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) {
15550 case MIPS_HFLAG_BR:
15551 break;
15552 case MIPS_HFLAG_BC:
15553 case MIPS_HFLAG_BL:
15554 case MIPS_HFLAG_B:
15555 env->btarget = data[2];
15556 break;
15557 }
15558 }
armbru's QEMU hackery