target/ppc/gdbstub.c

   1 /*
   2  * PowerPC gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23 #include "gdbstub/helpers.h"
  24 #include "internal.h"
  25
  26 static int ppc_gdb_register_len_apple(int n)
  27 {
  28     switch (n) {
  29     case 0 ... 31:
  30         /* gprs */
  31         return 8;
  32     case 32 ... 63:
  33         /* fprs */
  34         return 8;
  35     case 64 ... 95:
  36         return 16;
  37     case 64 + 32: /* nip */
  38     case 65 + 32: /* msr */
  39     case 67 + 32: /* lr */
  40     case 68 + 32: /* ctr */
  41     case 70 + 32: /* fpscr */
  42         return 8;
  43     case 66 + 32: /* cr */
  44     case 69 + 32: /* xer */
  45         return 4;
  46     default:
  47         return 0;
  48     }
  49 }
  50
  51 static int ppc_gdb_register_len(int n)
  52 {
  53     switch (n) {
  54     case 0 ... 31:
  55         /* gprs */
  56         return sizeof(target_ulong);
  57     case 66:
  58         /* cr */
  59     case 69:
  60         /* xer */
  61         return 4;
  62     case 64:
  63         /* nip */
  64     case 65:
  65         /* msr */
  66     case 67:
  67         /* lr */
  68     case 68:
  69         /* ctr */
  70         return sizeof(target_ulong);
  71     default:
  72         return 0;
  73     }
  74 }
  75
  76 /*
  77  * We need to present the registers to gdb in the "current" memory
  78  * ordering.  For user-only mode we get this for free;
  79  * TARGET_BIG_ENDIAN is set to the proper ordering for the
  80  * binary, and cannot be changed.  For system mode,
  81  * TARGET_BIG_ENDIAN is always set, and we must check the current
  82  * mode of the chip to see if we're running in little-endian.
  83  */
  84 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
  85 {
  86 #ifndef CONFIG_USER_ONLY
  87     if (!FIELD_EX64(env->msr, MSR, LE)) {
  88         /* do nothing */
  89     } else if (len == 4) {
  90         bswap32s((uint32_t *)mem_buf);
  91     } else if (len == 8) {
  92         bswap64s((uint64_t *)mem_buf);
  93     } else if (len == 16) {
  94         bswap128s((Int128 *)mem_buf);
  95     } else {
  96         g_assert_not_reached();
  97     }
  98 #endif
  99 }
 100
 101 /*
 102  * Old gdb always expects FP registers.  Newer (xml-aware) gdb only
 103  * expects whatever the target description contains.  Due to a
 104  * historical mishap the FP registers appear in between core integer
 105  * regs and PC, MSR, CR, and so forth.  We hack round this by giving
 106  * the FP regs zero size when talking to a newer gdb.
 107  */
 108
 109 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
 110 {
 111     CPUPPCState *env = cpu_env(cs);
 112     uint8_t *mem_buf;
 113     int r = ppc_gdb_register_len(n);
 114
 115     if (!r) {
 116         return r;
 117     }
 118
 119     if (n < 32) {
 120         /* gprs */
 121         gdb_get_regl(buf, env->gpr[n]);
 122     } else {
 123         switch (n) {
 124         case 64:
 125             gdb_get_regl(buf, env->nip);
 126             break;
 127         case 65:
 128             gdb_get_regl(buf, env->msr);
 129             break;
 130         case 66:
 131             {
 132                 uint32_t cr = ppc_get_cr(env);
 133                 gdb_get_reg32(buf, cr);
 134                 break;
 135             }
 136         case 67:
 137             gdb_get_regl(buf, env->lr);
 138             break;
 139         case 68:
 140             gdb_get_regl(buf, env->ctr);
 141             break;
 142         case 69:
 143             gdb_get_reg32(buf, cpu_read_xer(env));
 144             break;
 145         }
 146     }
 147     mem_buf = buf->data + buf->len - r;
 148     ppc_maybe_bswap_register(env, mem_buf, r);
 149     return r;
 150 }
 151
 152 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
 153 {
 154     CPUPPCState *env = cpu_env(cs);
 155     uint8_t *mem_buf;
 156     int r = ppc_gdb_register_len_apple(n);
 157
 158     if (!r) {
 159         return r;
 160     }
 161
 162     if (n < 32) {
 163         /* gprs */
 164         gdb_get_reg64(buf, env->gpr[n]);
 165     } else if (n < 64) {
 166         /* fprs */
 167         gdb_get_reg64(buf, *cpu_fpr_ptr(env, n - 32));
 168     } else if (n < 96) {
 169         /* Altivec */
 170         gdb_get_reg64(buf, n - 64);
 171         gdb_get_reg64(buf, 0);
 172     } else {
 173         switch (n) {
 174         case 64 + 32:
 175             gdb_get_reg64(buf, env->nip);
 176             break;
 177         case 65 + 32:
 178             gdb_get_reg64(buf, env->msr);
 179             break;
 180         case 66 + 32:
 181             {
 182                 uint32_t cr = ppc_get_cr(env);
 183                 gdb_get_reg32(buf, cr);
 184                 break;
 185             }
 186         case 67 + 32:
 187             gdb_get_reg64(buf, env->lr);
 188             break;
 189         case 68 + 32:
 190             gdb_get_reg64(buf, env->ctr);
 191             break;
 192         case 69 + 32:
 193             gdb_get_reg32(buf, cpu_read_xer(env));
 194             break;
 195         case 70 + 32:
 196             gdb_get_reg64(buf, env->fpscr);
 197             break;
 198         }
 199     }
 200     mem_buf = buf->data + buf->len - r;
 201     ppc_maybe_bswap_register(env, mem_buf, r);
 202     return r;
 203 }
 204
 205 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 206 {
 207     CPUPPCState *env = cpu_env(cs);
 208     int r = ppc_gdb_register_len(n);
 209
 210     if (!r) {
 211         return r;
 212     }
 213     ppc_maybe_bswap_register(env, mem_buf, r);
 214     if (n < 32) {
 215         /* gprs */
 216         env->gpr[n] = ldtul_p(mem_buf);
 217     } else if (n < 64) {
 218         /* fprs */
 219         *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
 220     } else {
 221         switch (n) {
 222         case 64:
 223             env->nip = ldtul_p(mem_buf);
 224             break;
 225         case 65:
 226             ppc_store_msr(env, ldtul_p(mem_buf));
 227             break;
 228         case 66:
 229             {
 230                 uint32_t cr = ldl_p(mem_buf);
 231                 ppc_set_cr(env, cr);
 232                 break;
 233             }
 234         case 67:
 235             env->lr = ldtul_p(mem_buf);
 236             break;
 237         case 68:
 238             env->ctr = ldtul_p(mem_buf);
 239             break;
 240         case 69:
 241             cpu_write_xer(env, ldl_p(mem_buf));
 242             break;
 243         case 70:
 244             /* fpscr */
 245             ppc_store_fpscr(env, ldtul_p(mem_buf));
 246             break;
 247         }
 248     }
 249     return r;
 250 }
 251 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
 252 {
 253     CPUPPCState *env = cpu_env(cs);
 254     int r = ppc_gdb_register_len_apple(n);
 255
 256     if (!r) {
 257         return r;
 258     }
 259     ppc_maybe_bswap_register(env, mem_buf, r);
 260     if (n < 32) {
 261         /* gprs */
 262         env->gpr[n] = ldq_p(mem_buf);
 263     } else if (n < 64) {
 264         /* fprs */
 265         *cpu_fpr_ptr(env, n - 32) = ldq_p(mem_buf);
 266     } else {
 267         switch (n) {
 268         case 64 + 32:
 269             env->nip = ldq_p(mem_buf);
 270             break;
 271         case 65 + 32:
 272             ppc_store_msr(env, ldq_p(mem_buf));
 273             break;
 274         case 66 + 32:
 275             {
 276                 uint32_t cr = ldl_p(mem_buf);
 277                 ppc_set_cr(env, cr);
 278                 break;
 279             }
 280         case 67 + 32:
 281             env->lr = ldq_p(mem_buf);
 282             break;
 283         case 68 + 32:
 284             env->ctr = ldq_p(mem_buf);
 285             break;
 286         case 69 + 32:
 287             cpu_write_xer(env, ldl_p(mem_buf));
 288             break;
 289         case 70 + 32:
 290             /* fpscr */
 291             ppc_store_fpscr(env, ldq_p(mem_buf));
 292             break;
 293         }
 294     }
 295     return r;
 296 }
 297
 298 #ifndef CONFIG_USER_ONLY
 299 static void gdb_gen_spr_feature(CPUState *cs)
 300 {
 301     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
 302     PowerPCCPU *cpu = POWERPC_CPU(cs);
 303     CPUPPCState *env = &cpu->env;
 304     GDBFeatureBuilder builder;
 305     unsigned int num_regs = 0;
 306     int i;
 307
 308     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
 309         ppc_spr_t *spr = &env->spr_cb[i];
 310
 311         if (!spr->name) {
 312             continue;
 313         }
 314
 315         /*
 316          * GDB identifies registers based on the order they are
 317          * presented in the XML. These ids will not match QEMU's
 318          * representation (which follows the PowerISA).
 319          *
 320          * Store the position of the current register description so
 321          * we can make the correspondence later.
 322          */
 323         spr->gdb_id = num_regs;
 324         num_regs++;
 325     }
 326
 327     if (pcc->gdb_spr.xml) {
 328         return;
 329     }
 330
 331     gdb_feature_builder_init(&builder, &pcc->gdb_spr,
 332                              "org.qemu.power.spr", "power-spr.xml",
 333                              cs->gdb_num_regs);
 334
 335     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
 336         ppc_spr_t *spr = &env->spr_cb[i];
 337
 338         if (!spr->name) {
 339             continue;
 340         }
 341
 342         gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1),
 343                                        TARGET_LONG_BITS, spr->gdb_id,
 344                                        "int", "spr");
 345     }
 346
 347     gdb_feature_builder_end(&builder);
 348 }
 349 #endif
 350
 351 #if !defined(CONFIG_USER_ONLY)
 352 static int gdb_find_spr_idx(CPUPPCState *env, int n)
 353 {
 354     int i;
 355
 356     for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
 357         ppc_spr_t *spr = &env->spr_cb[i];
 358
 359         if (spr->name && spr->gdb_id == n) {
 360             return i;
 361         }
 362     }
 363     return -1;
 364 }
 365
 366 static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n)
 367 {
 368     PowerPCCPU *cpu = POWERPC_CPU(cs);
 369     CPUPPCState *env = &cpu->env;
 370     int reg;
 371     int len;
 372
 373     reg = gdb_find_spr_idx(env, n);
 374     if (reg < 0) {
 375         return 0;
 376     }
 377
 378     len = TARGET_LONG_SIZE;
 379
 380     /* Handle those SPRs that are not part of the env->spr[] array */
 381     target_ulong val;
 382     switch (reg) {
 383 #if defined(TARGET_PPC64)
 384     case SPR_CFAR:
 385         val = env->cfar;
 386         break;
 387 #endif
 388     case SPR_HDEC:
 389         val = cpu_ppc_load_hdecr(env);
 390         break;
 391     case SPR_TBL:
 392         val = cpu_ppc_load_tbl(env);
 393         break;
 394     case SPR_TBU:
 395         val = cpu_ppc_load_tbu(env);
 396         break;
 397     case SPR_DECR:
 398         val = cpu_ppc_load_decr(env);
 399         break;
 400     default:
 401         val = env->spr[reg];
 402     }
 403     gdb_get_regl(buf, val);
 404
 405     ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len);
 406     return len;
 407 }
 408
 409 static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n)
 410 {
 411     PowerPCCPU *cpu = POWERPC_CPU(cs);
 412     CPUPPCState *env = &cpu->env;
 413     int reg;
 414     int len;
 415
 416     reg = gdb_find_spr_idx(env, n);
 417     if (reg < 0) {
 418         return 0;
 419     }
 420
 421     len = TARGET_LONG_SIZE;
 422     ppc_maybe_bswap_register(env, mem_buf, len);
 423
 424     /* Handle those SPRs that are not part of the env->spr[] array */
 425     target_ulong val = ldn_p(mem_buf, len);
 426     switch (reg) {
 427 #if defined(TARGET_PPC64)
 428     case SPR_CFAR:
 429         env->cfar = val;
 430         break;
 431 #endif
 432     default:
 433         env->spr[reg] = val;
 434     }
 435
 436     return len;
 437 }
 438 #endif
 439
 440 static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n)
 441 {
 442     PowerPCCPU *cpu = POWERPC_CPU(cs);
 443     CPUPPCState *env = &cpu->env;
 444     uint8_t *mem_buf;
 445     if (n < 32) {
 446         gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));
 447         mem_buf = gdb_get_reg_ptr(buf, 8);
 448         ppc_maybe_bswap_register(env, mem_buf, 8);
 449         return 8;
 450     }
 451     if (n == 32) {
 452         gdb_get_reg32(buf, env->fpscr);
 453         mem_buf = gdb_get_reg_ptr(buf, 4);
 454         ppc_maybe_bswap_register(env, mem_buf, 4);
 455         return 4;
 456     }
 457     return 0;
 458 }
 459
 460 static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n)
 461 {
 462     PowerPCCPU *cpu = POWERPC_CPU(cs);
 463     CPUPPCState *env = &cpu->env;
 464
 465     if (n < 32) {
 466         ppc_maybe_bswap_register(env, mem_buf, 8);
 467         *cpu_fpr_ptr(env, n) = ldq_p(mem_buf);
 468         return 8;
 469     }
 470     if (n == 32) {
 471         ppc_maybe_bswap_register(env, mem_buf, 4);
 472         ppc_store_fpscr(env, ldl_p(mem_buf));
 473         return 4;
 474     }
 475     return 0;
 476 }
 477
 478 static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n)
 479 {
 480     PowerPCCPU *cpu = POWERPC_CPU(cs);
 481     CPUPPCState *env = &cpu->env;
 482     uint8_t *mem_buf;
 483
 484     if (n < 32) {
 485         ppc_avr_t *avr = cpu_avr_ptr(env, n);
 486         gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1));
 487         mem_buf = gdb_get_reg_ptr(buf, 16);
 488         ppc_maybe_bswap_register(env, mem_buf, 16);
 489         return 16;
 490     }
 491     if (n == 32) {
 492         gdb_get_reg32(buf, ppc_get_vscr(env));
 493         mem_buf = gdb_get_reg_ptr(buf, 4);
 494         ppc_maybe_bswap_register(env, mem_buf, 4);
 495         return 4;
 496     }
 497     if (n == 33) {
 498         gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]);
 499         mem_buf = gdb_get_reg_ptr(buf, 4);
 500         ppc_maybe_bswap_register(env, mem_buf, 4);
 501         return 4;
 502     }
 503     return 0;
 504 }
 505
 506 static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n)
 507 {
 508     PowerPCCPU *cpu = POWERPC_CPU(cs);
 509     CPUPPCState *env = &cpu->env;
 510
 511     if (n < 32) {
 512         ppc_avr_t *avr = cpu_avr_ptr(env, n);
 513         ppc_maybe_bswap_register(env, mem_buf, 16);
 514         avr->VsrD(0) = ldq_p(mem_buf);
 515         avr->VsrD(1) = ldq_p(mem_buf + 8);
 516         return 16;
 517     }
 518     if (n == 32) {
 519         ppc_maybe_bswap_register(env, mem_buf, 4);
 520         ppc_store_vscr(env, ldl_p(mem_buf));
 521         return 4;
 522     }
 523     if (n == 33) {
 524         ppc_maybe_bswap_register(env, mem_buf, 4);
 525         env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
 526         return 4;
 527     }
 528     return 0;
 529 }
 530
 531 static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n)
 532 {
 533     PowerPCCPU *cpu = POWERPC_CPU(cs);
 534     CPUPPCState *env = &cpu->env;
 535
 536     if (n < 32) {
 537 #if defined(TARGET_PPC64)
 538         gdb_get_reg32(buf, env->gpr[n] >> 32);
 539         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
 540 #else
 541         gdb_get_reg32(buf, env->gprh[n]);
 542 #endif
 543         return 4;
 544     }
 545     if (n == 32) {
 546         gdb_get_reg64(buf, env->spe_acc);
 547         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
 548         return 8;
 549     }
 550     if (n == 33) {
 551         gdb_get_reg32(buf, env->spe_fscr);
 552         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4);
 553         return 4;
 554     }
 555     return 0;
 556 }
 557
 558 static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n)
 559 {
 560     PowerPCCPU *cpu = POWERPC_CPU(cs);
 561     CPUPPCState *env = &cpu->env;
 562
 563     if (n < 32) {
 564 #if defined(TARGET_PPC64)
 565         target_ulong lo = (uint32_t)env->gpr[n];
 566         target_ulong hi;
 567
 568         ppc_maybe_bswap_register(env, mem_buf, 4);
 569
 570         hi = (target_ulong)ldl_p(mem_buf) << 32;
 571         env->gpr[n] = lo | hi;
 572 #else
 573         env->gprh[n] = ldl_p(mem_buf);
 574 #endif
 575         return 4;
 576     }
 577     if (n == 32) {
 578         ppc_maybe_bswap_register(env, mem_buf, 8);
 579         env->spe_acc = ldq_p(mem_buf);
 580         return 8;
 581     }
 582     if (n == 33) {
 583         ppc_maybe_bswap_register(env, mem_buf, 4);
 584         env->spe_fscr = ldl_p(mem_buf);
 585         return 4;
 586     }
 587     return 0;
 588 }
 589
 590 static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n)
 591 {
 592     PowerPCCPU *cpu = POWERPC_CPU(cs);
 593     CPUPPCState *env = &cpu->env;
 594
 595     if (n < 32) {
 596         gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));
 597         ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);
 598         return 8;
 599     }
 600     return 0;
 601 }
 602
 603 static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n)
 604 {
 605     PowerPCCPU *cpu = POWERPC_CPU(cs);
 606     CPUPPCState *env = &cpu->env;
 607
 608     if (n < 32) {
 609         ppc_maybe_bswap_register(env, mem_buf, 8);
 610         *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);
 611         return 8;
 612     }
 613     return 0;
 614 }
 615
 616 const gchar *ppc_gdb_arch_name(CPUState *cs)
 617 {
 618 #if defined(TARGET_PPC64)
 619     return "powerpc:common64";
 620 #else
 621     return "powerpc:common";
 622 #endif
 623 }
 624
 625 void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)
 626 {
 627     if (pcc->insns_flags & PPC_FLOAT) {
 628         gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
 629                                  gdb_find_static_feature("power-fpu.xml"), 0);
 630     }
 631     if (pcc->insns_flags & PPC_ALTIVEC) {
 632         gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
 633                                  gdb_find_static_feature("power-altivec.xml"),
 634                                  0);
 635     }
 636     if (pcc->insns_flags & PPC_SPE) {
 637         gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
 638                                  gdb_find_static_feature("power-spe.xml"), 0);
 639     }
 640     if (pcc->insns_flags2 & PPC2_VSX) {
 641         gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
 642                                  gdb_find_static_feature("power-vsx.xml"), 0);
 643     }
 644 #ifndef CONFIG_USER_ONLY
 645     gdb_gen_spr_feature(cs);
 646     gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,
 647                              &pcc->gdb_spr, 0);
 648 #endif
 649 }