tcg/arm/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  * Copyright (c) 2008 Andrzej Zaborowski
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #ifndef ARM_TCG_TARGET_H
  27 #define ARM_TCG_TARGET_H
  28
  29 extern int arm_arch;
  30
  31 #define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
  32
  33 #define TCG_TARGET_INSN_UNIT_SIZE 4
  34 #define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
  35
  36 typedef enum {
  37     TCG_REG_R0 = 0,
  38     TCG_REG_R1,
  39     TCG_REG_R2,
  40     TCG_REG_R3,
  41     TCG_REG_R4,
  42     TCG_REG_R5,
  43     TCG_REG_R6,
  44     TCG_REG_R7,
  45     TCG_REG_R8,
  46     TCG_REG_R9,
  47     TCG_REG_R10,
  48     TCG_REG_R11,
  49     TCG_REG_R12,
  50     TCG_REG_R13,
  51     TCG_REG_R14,
  52     TCG_REG_PC,
  53
  54     TCG_REG_Q0,
  55     TCG_REG_Q1,
  56     TCG_REG_Q2,
  57     TCG_REG_Q3,
  58     TCG_REG_Q4,
  59     TCG_REG_Q5,
  60     TCG_REG_Q6,
  61     TCG_REG_Q7,
  62     TCG_REG_Q8,
  63     TCG_REG_Q9,
  64     TCG_REG_Q10,
  65     TCG_REG_Q11,
  66     TCG_REG_Q12,
  67     TCG_REG_Q13,
  68     TCG_REG_Q14,
  69     TCG_REG_Q15,
  70
  71     TCG_AREG0 = TCG_REG_R6,
  72     TCG_REG_CALL_STACK = TCG_REG_R13,
  73 } TCGReg;
  74
  75 #define TCG_TARGET_NB_REGS 32
  76
  77 #ifdef __ARM_ARCH_EXT_IDIV__
  78 #define use_idiv_instructions  1
  79 #else
  80 extern bool use_idiv_instructions;
  81 #endif
  82 #ifdef __ARM_NEON__
  83 #define use_neon_instructions  1
  84 #else
  85 extern bool use_neon_instructions;
  86 #endif
  87
  88 /* used for function call generation */
  89 #define TCG_TARGET_STACK_ALIGN          8
  90 #define TCG_TARGET_CALL_STACK_OFFSET    0
  91 #define TCG_TARGET_CALL_ARG_I32         TCG_CALL_ARG_NORMAL
  92 #define TCG_TARGET_CALL_ARG_I64         TCG_CALL_ARG_EVEN
  93 #define TCG_TARGET_CALL_ARG_I128        TCG_CALL_ARG_EVEN
  94 #define TCG_TARGET_CALL_RET_I128        TCG_CALL_RET_BY_REF
  95
  96 /* optional instructions */
  97 #define TCG_TARGET_HAS_ext8s_i32        1
  98 #define TCG_TARGET_HAS_ext16s_i32       1
  99 #define TCG_TARGET_HAS_ext8u_i32        0 /* and r0, r1, #0xff */
 100 #define TCG_TARGET_HAS_ext16u_i32       1
 101 #define TCG_TARGET_HAS_bswap16_i32      1
 102 #define TCG_TARGET_HAS_bswap32_i32      1
 103 #define TCG_TARGET_HAS_not_i32          1
 104 #define TCG_TARGET_HAS_rot_i32          1
 105 #define TCG_TARGET_HAS_andc_i32         1
 106 #define TCG_TARGET_HAS_orc_i32          0
 107 #define TCG_TARGET_HAS_eqv_i32          0
 108 #define TCG_TARGET_HAS_nand_i32         0
 109 #define TCG_TARGET_HAS_nor_i32          0
 110 #define TCG_TARGET_HAS_clz_i32          1
 111 #define TCG_TARGET_HAS_ctz_i32          use_armv7_instructions
 112 #define TCG_TARGET_HAS_ctpop_i32        0
 113 #define TCG_TARGET_HAS_deposit_i32      use_armv7_instructions
 114 #define TCG_TARGET_HAS_extract_i32      use_armv7_instructions
 115 #define TCG_TARGET_HAS_sextract_i32     use_armv7_instructions
 116 #define TCG_TARGET_HAS_extract2_i32     1
 117 #define TCG_TARGET_HAS_negsetcond_i32   1
 118 #define TCG_TARGET_HAS_mulu2_i32        1
 119 #define TCG_TARGET_HAS_muls2_i32        1
 120 #define TCG_TARGET_HAS_muluh_i32        0
 121 #define TCG_TARGET_HAS_mulsh_i32        0
 122 #define TCG_TARGET_HAS_div_i32          use_idiv_instructions
 123 #define TCG_TARGET_HAS_rem_i32          0
 124 #define TCG_TARGET_HAS_qemu_st8_i32     0
 125
 126 #define TCG_TARGET_HAS_qemu_ldst_i128   0
 127
 128 #define TCG_TARGET_HAS_tst              1
 129
 130 #define TCG_TARGET_HAS_v64              use_neon_instructions
 131 #define TCG_TARGET_HAS_v128             use_neon_instructions
 132 #define TCG_TARGET_HAS_v256             0
 133
 134 #define TCG_TARGET_HAS_andc_vec         1
 135 #define TCG_TARGET_HAS_orc_vec          1
 136 #define TCG_TARGET_HAS_nand_vec         0
 137 #define TCG_TARGET_HAS_nor_vec          0
 138 #define TCG_TARGET_HAS_eqv_vec          0
 139 #define TCG_TARGET_HAS_not_vec          1
 140 #define TCG_TARGET_HAS_neg_vec          1
 141 #define TCG_TARGET_HAS_abs_vec          1
 142 #define TCG_TARGET_HAS_roti_vec         0
 143 #define TCG_TARGET_HAS_rots_vec         0
 144 #define TCG_TARGET_HAS_rotv_vec         0
 145 #define TCG_TARGET_HAS_shi_vec          1
 146 #define TCG_TARGET_HAS_shs_vec          0
 147 #define TCG_TARGET_HAS_shv_vec          0
 148 #define TCG_TARGET_HAS_mul_vec          1
 149 #define TCG_TARGET_HAS_sat_vec          1
 150 #define TCG_TARGET_HAS_minmax_vec       1
 151 #define TCG_TARGET_HAS_bitsel_vec       1
 152 #define TCG_TARGET_HAS_cmpsel_vec       0
 153 #define TCG_TARGET_HAS_tst_vec          1
 154
 155 #define TCG_TARGET_DEFAULT_MO (0)
 156 #define TCG_TARGET_NEED_LDST_LABELS
 157 #define TCG_TARGET_NEED_POOL_LABELS
 158
 159 #endif