tcg/loongarch64/tcg-target.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
   5  *
   6  * Based on tcg/riscv/tcg-target.h
   7  *
   8  * Copyright (c) 2018 SiFive, Inc
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28
  29 #ifndef LOONGARCH_TCG_TARGET_H
  30 #define LOONGARCH_TCG_TARGET_H
  31
  32 #include "host/cpuinfo.h"
  33
  34 #define TCG_TARGET_INSN_UNIT_SIZE 4
  35 #define TCG_TARGET_NB_REGS 64
  36
  37 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
  38
  39 typedef enum {
  40     TCG_REG_ZERO,
  41     TCG_REG_RA,
  42     TCG_REG_TP,
  43     TCG_REG_SP,
  44     TCG_REG_A0,
  45     TCG_REG_A1,
  46     TCG_REG_A2,
  47     TCG_REG_A3,
  48     TCG_REG_A4,
  49     TCG_REG_A5,
  50     TCG_REG_A6,
  51     TCG_REG_A7,
  52     TCG_REG_T0,
  53     TCG_REG_T1,
  54     TCG_REG_T2,
  55     TCG_REG_T3,
  56     TCG_REG_T4,
  57     TCG_REG_T5,
  58     TCG_REG_T6,
  59     TCG_REG_T7,
  60     TCG_REG_T8,
  61     TCG_REG_RESERVED,
  62     TCG_REG_S9,
  63     TCG_REG_S0,
  64     TCG_REG_S1,
  65     TCG_REG_S2,
  66     TCG_REG_S3,
  67     TCG_REG_S4,
  68     TCG_REG_S5,
  69     TCG_REG_S6,
  70     TCG_REG_S7,
  71     TCG_REG_S8,
  72
  73     TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
  74     TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
  75     TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
  76     TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
  77     TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
  78     TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
  79     TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
  80     TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
  81
  82     /* aliases */
  83     TCG_AREG0    = TCG_REG_S0,
  84     TCG_REG_TMP0 = TCG_REG_T8,
  85     TCG_REG_TMP1 = TCG_REG_T7,
  86     TCG_REG_TMP2 = TCG_REG_T6,
  87     TCG_VEC_TMP0 = TCG_REG_V23,
  88 } TCGReg;
  89
  90 /* used for function call generation */
  91 #define TCG_REG_CALL_STACK              TCG_REG_SP
  92 #define TCG_TARGET_STACK_ALIGN          16
  93 #define TCG_TARGET_CALL_STACK_OFFSET    0
  94 #define TCG_TARGET_CALL_ARG_I32         TCG_CALL_ARG_NORMAL
  95 #define TCG_TARGET_CALL_ARG_I64         TCG_CALL_ARG_NORMAL
  96 #define TCG_TARGET_CALL_ARG_I128        TCG_CALL_ARG_NORMAL
  97 #define TCG_TARGET_CALL_RET_I128        TCG_CALL_RET_NORMAL
  98
  99 /* optional instructions */
 100 #define TCG_TARGET_HAS_negsetcond_i32   0
 101 #define TCG_TARGET_HAS_div_i32          1
 102 #define TCG_TARGET_HAS_rem_i32          1
 103 #define TCG_TARGET_HAS_div2_i32         0
 104 #define TCG_TARGET_HAS_rot_i32          1
 105 #define TCG_TARGET_HAS_deposit_i32      1
 106 #define TCG_TARGET_HAS_extract_i32      1
 107 #define TCG_TARGET_HAS_sextract_i32     0
 108 #define TCG_TARGET_HAS_extract2_i32     0
 109 #define TCG_TARGET_HAS_add2_i32         0
 110 #define TCG_TARGET_HAS_sub2_i32         0
 111 #define TCG_TARGET_HAS_mulu2_i32        0
 112 #define TCG_TARGET_HAS_muls2_i32        0
 113 #define TCG_TARGET_HAS_muluh_i32        1
 114 #define TCG_TARGET_HAS_mulsh_i32        1
 115 #define TCG_TARGET_HAS_ext8s_i32        1
 116 #define TCG_TARGET_HAS_ext16s_i32       1
 117 #define TCG_TARGET_HAS_ext8u_i32        1
 118 #define TCG_TARGET_HAS_ext16u_i32       1
 119 #define TCG_TARGET_HAS_bswap16_i32      1
 120 #define TCG_TARGET_HAS_bswap32_i32      1
 121 #define TCG_TARGET_HAS_not_i32          1
 122 #define TCG_TARGET_HAS_andc_i32         1
 123 #define TCG_TARGET_HAS_orc_i32          1
 124 #define TCG_TARGET_HAS_eqv_i32          0
 125 #define TCG_TARGET_HAS_nand_i32         0
 126 #define TCG_TARGET_HAS_nor_i32          1
 127 #define TCG_TARGET_HAS_clz_i32          1
 128 #define TCG_TARGET_HAS_ctz_i32          1
 129 #define TCG_TARGET_HAS_ctpop_i32        0
 130 #define TCG_TARGET_HAS_brcond2          0
 131 #define TCG_TARGET_HAS_setcond2         0
 132 #define TCG_TARGET_HAS_qemu_st8_i32     0
 133
 134 /* 64-bit operations */
 135 #define TCG_TARGET_HAS_negsetcond_i64   0
 136 #define TCG_TARGET_HAS_div_i64          1
 137 #define TCG_TARGET_HAS_rem_i64          1
 138 #define TCG_TARGET_HAS_div2_i64         0
 139 #define TCG_TARGET_HAS_rot_i64          1
 140 #define TCG_TARGET_HAS_deposit_i64      1
 141 #define TCG_TARGET_HAS_extract_i64      1
 142 #define TCG_TARGET_HAS_sextract_i64     0
 143 #define TCG_TARGET_HAS_extract2_i64     0
 144 #define TCG_TARGET_HAS_extr_i64_i32     1
 145 #define TCG_TARGET_HAS_ext8s_i64        1
 146 #define TCG_TARGET_HAS_ext16s_i64       1
 147 #define TCG_TARGET_HAS_ext32s_i64       1
 148 #define TCG_TARGET_HAS_ext8u_i64        1
 149 #define TCG_TARGET_HAS_ext16u_i64       1
 150 #define TCG_TARGET_HAS_ext32u_i64       1
 151 #define TCG_TARGET_HAS_bswap16_i64      1
 152 #define TCG_TARGET_HAS_bswap32_i64      1
 153 #define TCG_TARGET_HAS_bswap64_i64      1
 154 #define TCG_TARGET_HAS_not_i64          1
 155 #define TCG_TARGET_HAS_andc_i64         1
 156 #define TCG_TARGET_HAS_orc_i64          1
 157 #define TCG_TARGET_HAS_eqv_i64          0
 158 #define TCG_TARGET_HAS_nand_i64         0
 159 #define TCG_TARGET_HAS_nor_i64          1
 160 #define TCG_TARGET_HAS_clz_i64          1
 161 #define TCG_TARGET_HAS_ctz_i64          1
 162 #define TCG_TARGET_HAS_ctpop_i64        0
 163 #define TCG_TARGET_HAS_add2_i64         0
 164 #define TCG_TARGET_HAS_sub2_i64         0
 165 #define TCG_TARGET_HAS_mulu2_i64        0
 166 #define TCG_TARGET_HAS_muls2_i64        0
 167 #define TCG_TARGET_HAS_muluh_i64        1
 168 #define TCG_TARGET_HAS_mulsh_i64        1
 169
 170 #define TCG_TARGET_HAS_qemu_ldst_i128   (cpuinfo & CPUINFO_LSX)
 171
 172 #define TCG_TARGET_HAS_tst              0
 173
 174 #define TCG_TARGET_HAS_v64              (cpuinfo & CPUINFO_LSX)
 175 #define TCG_TARGET_HAS_v128             (cpuinfo & CPUINFO_LSX)
 176 #define TCG_TARGET_HAS_v256             (cpuinfo & CPUINFO_LASX)
 177
 178 #define TCG_TARGET_HAS_not_vec          1
 179 #define TCG_TARGET_HAS_neg_vec          1
 180 #define TCG_TARGET_HAS_abs_vec          0
 181 #define TCG_TARGET_HAS_andc_vec         1
 182 #define TCG_TARGET_HAS_orc_vec          1
 183 #define TCG_TARGET_HAS_nand_vec         0
 184 #define TCG_TARGET_HAS_nor_vec          1
 185 #define TCG_TARGET_HAS_eqv_vec          0
 186 #define TCG_TARGET_HAS_mul_vec          1
 187 #define TCG_TARGET_HAS_shi_vec          1
 188 #define TCG_TARGET_HAS_shs_vec          0
 189 #define TCG_TARGET_HAS_shv_vec          1
 190 #define TCG_TARGET_HAS_roti_vec         1
 191 #define TCG_TARGET_HAS_rots_vec         0
 192 #define TCG_TARGET_HAS_rotv_vec         1
 193 #define TCG_TARGET_HAS_sat_vec          1
 194 #define TCG_TARGET_HAS_minmax_vec       1
 195 #define TCG_TARGET_HAS_bitsel_vec       1
 196 #define TCG_TARGET_HAS_cmpsel_vec       0
 197 #define TCG_TARGET_HAS_tst_vec          0
 198
 199 #define TCG_TARGET_DEFAULT_MO (0)
 200
 201 #define TCG_TARGET_NEED_LDST_LABELS
 202
 203 #endif /* LOONGARCH_TCG_TARGET_H */