target/nios2/cpu.c

   1 /*
   2  * QEMU Nios II CPU
   3  *
   4  * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/module.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "exec/log.h"
  26 #include "gdbstub/helpers.h"
  27 #include "hw/qdev-properties.h"
  28
  29 static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     Nios2CPU *cpu = NIOS2_CPU(cs);
  32     CPUNios2State *env = &cpu->env;
  33
  34     env->pc = value;
  35 }
  36
  37 static vaddr nios2_cpu_get_pc(CPUState *cs)
  38 {
  39     Nios2CPU *cpu = NIOS2_CPU(cs);
  40     CPUNios2State *env = &cpu->env;
  41
  42     return env->pc;
  43 }
  44
  45 static void nios2_restore_state_to_opc(CPUState *cs,
  46                                        const TranslationBlock *tb,
  47                                        const uint64_t *data)
  48 {
  49     Nios2CPU *cpu = NIOS2_CPU(cs);
  50     CPUNios2State *env = &cpu->env;
  51
  52     env->pc = data[0];
  53 }
  54
  55 static bool nios2_cpu_has_work(CPUState *cs)
  56 {
  57     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  58 }
  59
  60 static void nios2_cpu_reset_hold(Object *obj)
  61 {
  62     CPUState *cs = CPU(obj);
  63     Nios2CPU *cpu = NIOS2_CPU(cs);
  64     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
  65     CPUNios2State *env = &cpu->env;
  66
  67     if (ncc->parent_phases.hold) {
  68         ncc->parent_phases.hold(obj);
  69     }
  70
  71     memset(env->ctrl, 0, sizeof(env->ctrl));
  72     env->pc = cpu->reset_addr;
  73
  74 #if defined(CONFIG_USER_ONLY)
  75     /* Start in user mode with interrupts enabled. */
  76     env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE;
  77     memset(env->regs, 0, sizeof(env->regs));
  78 #else
  79     env->ctrl[CR_STATUS] = CR_STATUS_RSIE;
  80     nios2_update_crs(env);
  81     memset(env->shadow_regs, 0, sizeof(env->shadow_regs));
  82 #endif
  83 }
  84
  85 #ifndef CONFIG_USER_ONLY
  86 static void eic_set_irq(void *opaque, int irq, int level)
  87 {
  88     Nios2CPU *cpu = opaque;
  89     CPUState *cs = CPU(cpu);
  90
  91     if (level) {
  92         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  93     } else {
  94         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  95     }
  96 }
  97
  98 static void iic_set_irq(void *opaque, int irq, int level)
  99 {
 100     Nios2CPU *cpu = opaque;
 101     CPUNios2State *env = &cpu->env;
 102     CPUState *cs = CPU(cpu);
 103
 104     env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level);
 105
 106     if (env->ctrl[CR_IPENDING]) {
 107         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 108     } else {
 109         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 110     }
 111 }
 112 #endif
 113
 114 static void nios2_cpu_initfn(Object *obj)
 115 {
 116     Nios2CPU *cpu = NIOS2_CPU(obj);
 117
 118     cpu_set_cpustate_pointers(cpu);
 119
 120 #if !defined(CONFIG_USER_ONLY)
 121     mmu_init(&cpu->env);
 122 #endif
 123 }
 124
 125 static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
 126 {
 127     return object_class_by_name(TYPE_NIOS2_CPU);
 128 }
 129
 130 static void realize_cr_status(CPUState *cs)
 131 {
 132     Nios2CPU *cpu = NIOS2_CPU(cs);
 133
 134     /* Begin with all fields of all registers are reserved. */
 135     memset(cpu->cr_state, 0, sizeof(cpu->cr_state));
 136
 137     /*
 138      * The combination of writable and readonly is the set of all
 139      * non-reserved fields.  We apply writable as a mask to bits,
 140      * and merge in existing readonly bits, before storing.
 141      */
 142 #define WR_REG(C)       cpu->cr_state[C].writable = -1
 143 #define RO_REG(C)       cpu->cr_state[C].readonly = -1
 144 #define WR_FIELD(C, F)  cpu->cr_state[C].writable |= R_##C##_##F##_MASK
 145 #define RO_FIELD(C, F)  cpu->cr_state[C].readonly |= R_##C##_##F##_MASK
 146
 147     WR_FIELD(CR_STATUS, PIE);
 148     WR_REG(CR_ESTATUS);
 149     WR_REG(CR_BSTATUS);
 150     RO_REG(CR_CPUID);
 151     RO_REG(CR_EXCEPTION);
 152     WR_REG(CR_BADADDR);
 153
 154     if (cpu->eic_present) {
 155         WR_FIELD(CR_STATUS, RSIE);
 156         RO_FIELD(CR_STATUS, NMI);
 157         WR_FIELD(CR_STATUS, PRS);
 158         RO_FIELD(CR_STATUS, CRS);
 159         WR_FIELD(CR_STATUS, IL);
 160         WR_FIELD(CR_STATUS, IH);
 161     } else {
 162         RO_FIELD(CR_STATUS, RSIE);
 163         WR_REG(CR_IENABLE);
 164         RO_REG(CR_IPENDING);
 165     }
 166
 167     if (cpu->mmu_present) {
 168         WR_FIELD(CR_STATUS, U);
 169         WR_FIELD(CR_STATUS, EH);
 170
 171         WR_FIELD(CR_PTEADDR, VPN);
 172         WR_FIELD(CR_PTEADDR, PTBASE);
 173
 174         RO_FIELD(CR_TLBMISC, D);
 175         RO_FIELD(CR_TLBMISC, PERM);
 176         RO_FIELD(CR_TLBMISC, BAD);
 177         RO_FIELD(CR_TLBMISC, DBL);
 178         WR_FIELD(CR_TLBMISC, PID);
 179         WR_FIELD(CR_TLBMISC, WE);
 180         WR_FIELD(CR_TLBMISC, RD);
 181         WR_FIELD(CR_TLBMISC, WAY);
 182
 183         WR_REG(CR_TLBACC);
 184     }
 185
 186     /*
 187      * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are
 188      * unimplemented, so their corresponding control regs remain reserved.
 189      */
 190
 191 #undef WR_REG
 192 #undef RO_REG
 193 #undef WR_FIELD
 194 #undef RO_FIELD
 195 }
 196
 197 static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
 198 {
 199     CPUState *cs = CPU(dev);
 200     Nios2CPU *cpu = NIOS2_CPU(cs);
 201     Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
 202     Error *local_err = NULL;
 203
 204 #ifndef CONFIG_USER_ONLY
 205     if (cpu->eic_present) {
 206         qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
 207     } else {
 208         qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
 209     }
 210 #endif
 211
 212     cpu_exec_realizefn(cs, &local_err);
 213     if (local_err != NULL) {
 214         error_propagate(errp, local_err);
 215         return;
 216     }
 217
 218     realize_cr_status(cs);
 219     qemu_init_vcpu(cs);
 220     cpu_reset(cs);
 221
 222     /* We have reserved storage for cpuid; might as well use it. */
 223     cpu->env.ctrl[CR_CPUID] = cs->cpu_index;
 224
 225     ncc->parent_realize(dev, errp);
 226 }
 227
 228 #ifndef CONFIG_USER_ONLY
 229 static bool eic_take_interrupt(Nios2CPU *cpu)
 230 {
 231     CPUNios2State *env = &cpu->env;
 232     const uint32_t status = env->ctrl[CR_STATUS];
 233
 234     if (cpu->rnmi) {
 235         return !(status & CR_STATUS_NMI);
 236     }
 237     if (!(status & CR_STATUS_PIE)) {
 238         return false;
 239     }
 240     if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) {
 241         return false;
 242     }
 243     if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) {
 244         return true;
 245     }
 246     return status & CR_STATUS_RSIE;
 247 }
 248
 249 static bool iic_take_interrupt(Nios2CPU *cpu)
 250 {
 251     CPUNios2State *env = &cpu->env;
 252
 253     if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) {
 254         return false;
 255     }
 256     return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE];
 257 }
 258
 259 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 260 {
 261     Nios2CPU *cpu = NIOS2_CPU(cs);
 262
 263     if (interrupt_request & CPU_INTERRUPT_HARD) {
 264         if (cpu->eic_present
 265             ? eic_take_interrupt(cpu)
 266             : iic_take_interrupt(cpu)) {
 267             cs->exception_index = EXCP_IRQ;
 268             nios2_cpu_do_interrupt(cs);
 269             return true;
 270         }
 271     }
 272     return false;
 273 }
 274 #endif /* !CONFIG_USER_ONLY */
 275
 276 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 277 {
 278     /* NOTE: NiosII R2 is not supported yet. */
 279     info->mach = bfd_arch_nios2;
 280     info->print_insn = print_insn_nios2;
 281 }
 282
 283 static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
 284 {
 285     Nios2CPU *cpu = NIOS2_CPU(cs);
 286     CPUNios2State *env = &cpu->env;
 287     uint32_t val;
 288
 289     if (n < 32) {          /* GP regs */
 290         val = env->regs[n];
 291     } else if (n == 32) {    /* PC */
 292         val = env->pc;
 293     } else if (n < 49) {     /* Status regs */
 294         unsigned cr = n - 33;
 295         if (nios2_cr_reserved(&cpu->cr_state[cr])) {
 296             val = 0;
 297         } else {
 298             val = env->ctrl[n - 33];
 299         }
 300     } else {
 301         /* Invalid regs */
 302         return 0;
 303     }
 304
 305     return gdb_get_reg32(mem_buf, val);
 306 }
 307
 308 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 309 {
 310     Nios2CPU *cpu = NIOS2_CPU(cs);
 311     CPUClass *cc = CPU_GET_CLASS(cs);
 312     CPUNios2State *env = &cpu->env;
 313     uint32_t val;
 314
 315     if (n > cc->gdb_num_core_regs) {
 316         return 0;
 317     }
 318     val = ldl_p(mem_buf);
 319
 320     if (n < 32) {            /* GP regs */
 321         env->regs[n] = val;
 322     } else if (n == 32) {    /* PC */
 323         env->pc = val;
 324     } else if (n < 49) {     /* Status regs */
 325         unsigned cr = n - 33;
 326         /* ??? Maybe allow the debugger to write to readonly fields. */
 327         val &= cpu->cr_state[cr].writable;
 328         val |= cpu->cr_state[cr].readonly & env->ctrl[cr];
 329         env->ctrl[cr] = val;
 330     } else {
 331         g_assert_not_reached();
 332     }
 333
 334     return 4;
 335 }
 336
 337 static Property nios2_properties[] = {
 338     DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true),
 339     DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
 340     /* ALTR,pid-num-bits */
 341     DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
 342     /* ALTR,tlb-num-ways */
 343     DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
 344     /* ALTR,tlb-num-entries */
 345     DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
 346     DEFINE_PROP_END_OF_LIST(),
 347 };
 348
 349 #ifndef CONFIG_USER_ONLY
 350 #include "hw/core/sysemu-cpu-ops.h"
 351
 352 static const struct SysemuCPUOps nios2_sysemu_ops = {
 353     .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
 354 };
 355 #endif
 356
 357 #include "hw/core/tcg-cpu-ops.h"
 358
 359 static const struct TCGCPUOps nios2_tcg_ops = {
 360     .initialize = nios2_tcg_init,
 361     .restore_state_to_opc = nios2_restore_state_to_opc,
 362
 363 #ifndef CONFIG_USER_ONLY
 364     .tlb_fill = nios2_cpu_tlb_fill,
 365     .cpu_exec_interrupt = nios2_cpu_exec_interrupt,
 366     .do_interrupt = nios2_cpu_do_interrupt,
 367     .do_unaligned_access = nios2_cpu_do_unaligned_access,
 368 #endif /* !CONFIG_USER_ONLY */
 369 };
 370
 371 static void nios2_cpu_class_init(ObjectClass *oc, void *data)
 372 {
 373     DeviceClass *dc = DEVICE_CLASS(oc);
 374     CPUClass *cc = CPU_CLASS(oc);
 375     Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
 376     ResettableClass *rc = RESETTABLE_CLASS(oc);
 377
 378     device_class_set_parent_realize(dc, nios2_cpu_realizefn,
 379                                     &ncc->parent_realize);
 380     device_class_set_props(dc, nios2_properties);
 381     resettable_class_set_parent_phases(rc, NULL, nios2_cpu_reset_hold, NULL,
 382                                        &ncc->parent_phases);
 383
 384     cc->class_by_name = nios2_cpu_class_by_name;
 385     cc->has_work = nios2_cpu_has_work;
 386     cc->dump_state = nios2_cpu_dump_state;
 387     cc->set_pc = nios2_cpu_set_pc;
 388     cc->get_pc = nios2_cpu_get_pc;
 389     cc->disas_set_info = nios2_cpu_disas_set_info;
 390 #ifndef CONFIG_USER_ONLY
 391     cc->sysemu_ops = &nios2_sysemu_ops;
 392 #endif
 393     cc->gdb_read_register = nios2_cpu_gdb_read_register;
 394     cc->gdb_write_register = nios2_cpu_gdb_write_register;
 395     cc->gdb_num_core_regs = 49;
 396     cc->tcg_ops = &nios2_tcg_ops;
 397 }
 398
 399 static const TypeInfo nios2_cpu_type_info = {
 400     .name = TYPE_NIOS2_CPU,
 401     .parent = TYPE_CPU,
 402     .instance_size = sizeof(Nios2CPU),
 403     .instance_init = nios2_cpu_initfn,
 404     .class_size = sizeof(Nios2CPUClass),
 405     .class_init = nios2_cpu_class_init,
 406 };
 407
 408 static void nios2_cpu_register_types(void)
 409 {
 410     type_register_static(&nios2_cpu_type_info);
 411 }
 412
 413 type_init(nios2_cpu_register_types)