target/tricore/cpu.h

   1 /*
   2  *  TriCore emulation for qemu: main CPU struct.
   3  *
   4  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TRICORE_CPU_H
  21 #define TRICORE_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "qemu/cpu-float.h"
  26 #include "tricore-defs.h"
  27
  28 typedef struct CPUArchState {
  29     /* GPR Register */
  30     uint32_t gpr_a[16];
  31     uint32_t gpr_d[16];
  32     /* CSFR Register */
  33     uint32_t PCXI;
  34 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
  35        This contains all the other bits.  Use psw_{read,write} to access
  36        the whole PSW.  */
  37     uint32_t PSW;
  38
  39     /* PSW flag cache for faster execution
  40     */
  41     uint32_t PSW_USB_C;
  42     uint32_t PSW_USB_V;   /* Only if bit 31 set, then flag is set  */
  43     uint32_t PSW_USB_SV;  /* Only if bit 31 set, then flag is set  */
  44     uint32_t PSW_USB_AV;  /* Only if bit 31 set, then flag is set. */
  45     uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
  46
  47     uint32_t PC;
  48     uint32_t SYSCON;
  49     uint32_t CPU_ID;
  50     uint32_t CORE_ID;
  51     uint32_t BIV;
  52     uint32_t BTV;
  53     uint32_t ISP;
  54     uint32_t ICR;
  55     uint32_t FCX;
  56     uint32_t LCX;
  57     uint32_t COMPAT;
  58
  59     /* Mem Protection Register */
  60     uint32_t DPR0_0L;
  61     uint32_t DPR0_0U;
  62     uint32_t DPR0_1L;
  63     uint32_t DPR0_1U;
  64     uint32_t DPR0_2L;
  65     uint32_t DPR0_2U;
  66     uint32_t DPR0_3L;
  67     uint32_t DPR0_3U;
  68
  69     uint32_t DPR1_0L;
  70     uint32_t DPR1_0U;
  71     uint32_t DPR1_1L;
  72     uint32_t DPR1_1U;
  73     uint32_t DPR1_2L;
  74     uint32_t DPR1_2U;
  75     uint32_t DPR1_3L;
  76     uint32_t DPR1_3U;
  77
  78     uint32_t DPR2_0L;
  79     uint32_t DPR2_0U;
  80     uint32_t DPR2_1L;
  81     uint32_t DPR2_1U;
  82     uint32_t DPR2_2L;
  83     uint32_t DPR2_2U;
  84     uint32_t DPR2_3L;
  85     uint32_t DPR2_3U;
  86
  87     uint32_t DPR3_0L;
  88     uint32_t DPR3_0U;
  89     uint32_t DPR3_1L;
  90     uint32_t DPR3_1U;
  91     uint32_t DPR3_2L;
  92     uint32_t DPR3_2U;
  93     uint32_t DPR3_3L;
  94     uint32_t DPR3_3U;
  95
  96     uint32_t CPR0_0L;
  97     uint32_t CPR0_0U;
  98     uint32_t CPR0_1L;
  99     uint32_t CPR0_1U;
 100     uint32_t CPR0_2L;
 101     uint32_t CPR0_2U;
 102     uint32_t CPR0_3L;
 103     uint32_t CPR0_3U;
 104
 105     uint32_t CPR1_0L;
 106     uint32_t CPR1_0U;
 107     uint32_t CPR1_1L;
 108     uint32_t CPR1_1U;
 109     uint32_t CPR1_2L;
 110     uint32_t CPR1_2U;
 111     uint32_t CPR1_3L;
 112     uint32_t CPR1_3U;
 113
 114     uint32_t CPR2_0L;
 115     uint32_t CPR2_0U;
 116     uint32_t CPR2_1L;
 117     uint32_t CPR2_1U;
 118     uint32_t CPR2_2L;
 119     uint32_t CPR2_2U;
 120     uint32_t CPR2_3L;
 121     uint32_t CPR2_3U;
 122
 123     uint32_t CPR3_0L;
 124     uint32_t CPR3_0U;
 125     uint32_t CPR3_1L;
 126     uint32_t CPR3_1U;
 127     uint32_t CPR3_2L;
 128     uint32_t CPR3_2U;
 129     uint32_t CPR3_3L;
 130     uint32_t CPR3_3U;
 131
 132     uint32_t DPM0;
 133     uint32_t DPM1;
 134     uint32_t DPM2;
 135     uint32_t DPM3;
 136
 137     uint32_t CPM0;
 138     uint32_t CPM1;
 139     uint32_t CPM2;
 140     uint32_t CPM3;
 141
 142     /* Memory Management Registers */
 143     uint32_t MMU_CON;
 144     uint32_t MMU_ASI;
 145     uint32_t MMU_TVA;
 146     uint32_t MMU_TPA;
 147     uint32_t MMU_TPX;
 148     uint32_t MMU_TFA;
 149     /* {1.3.1 only */
 150     uint32_t BMACON;
 151     uint32_t SMACON;
 152     uint32_t DIEAR;
 153     uint32_t DIETR;
 154     uint32_t CCDIER;
 155     uint32_t MIECON;
 156     uint32_t PIEAR;
 157     uint32_t PIETR;
 158     uint32_t CCPIER;
 159     /*} */
 160     /* Debug Registers */
 161     uint32_t DBGSR;
 162     uint32_t EXEVT;
 163     uint32_t CREVT;
 164     uint32_t SWEVT;
 165     uint32_t TR0EVT;
 166     uint32_t TR1EVT;
 167     uint32_t DMS;
 168     uint32_t DCX;
 169     uint32_t DBGTCR;
 170     uint32_t CCTRL;
 171     uint32_t CCNT;
 172     uint32_t ICNT;
 173     uint32_t M1CNT;
 174     uint32_t M2CNT;
 175     uint32_t M3CNT;
 176     /* Floating Point Registers */
 177     float_status fp_status;
 178
 179     /* Internal CPU feature flags.  */
 180     uint64_t features;
 181 } CPUTriCoreState;
 182
 183 /**
 184  * TriCoreCPU:
 185  * @env: #CPUTriCoreState
 186  *
 187  * A TriCore CPU.
 188  */
 189 struct ArchCPU {
 190     /*< private >*/
 191     CPUState parent_obj;
 192     /*< public >*/
 193
 194     CPUNegativeOffsetState neg;
 195     CPUTriCoreState env;
 196 };
 197
 198
 199 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 200 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
 201
 202
 203 #define MASK_PCXI_PCPN 0xff000000
 204 #define MASK_PCXI_PIE_1_3  0x00800000
 205 #define MASK_PCXI_PIE_1_6  0x00200000
 206 #define MASK_PCXI_UL   0x00400000
 207 #define MASK_PCXI_PCXS 0x000f0000
 208 #define MASK_PCXI_PCXO 0x0000ffff
 209
 210 #define MASK_PSW_USB 0xff000000
 211 #define MASK_USB_C   0x80000000
 212 #define MASK_USB_V   0x40000000
 213 #define MASK_USB_SV  0x20000000
 214 #define MASK_USB_AV  0x10000000
 215 #define MASK_USB_SAV 0x08000000
 216 #define MASK_PSW_PRS 0x00003000
 217 #define MASK_PSW_IO  0x00000c00
 218 #define MASK_PSW_IS  0x00000200
 219 #define MASK_PSW_GW  0x00000100
 220 #define MASK_PSW_CDE 0x00000080
 221 #define MASK_PSW_CDC 0x0000007f
 222 #define MASK_PSW_FPU_RM 0x3000000
 223
 224 #define MASK_SYSCON_PRO_TEN 0x2
 225 #define MASK_SYSCON_FCD_SF  0x1
 226
 227 #define MASK_CPUID_MOD     0xffff0000
 228 #define MASK_CPUID_MOD_32B 0x0000ff00
 229 #define MASK_CPUID_REV     0x000000ff
 230
 231 #define MASK_ICR_PIPN 0x00ff0000
 232 #define MASK_ICR_IE_1_3   0x00000100
 233 #define MASK_ICR_IE_1_6   0x00008000
 234 #define MASK_ICR_CCPN 0x000000ff
 235
 236 #define MASK_FCX_FCXS 0x000f0000
 237 #define MASK_FCX_FCXO 0x0000ffff
 238
 239 #define MASK_LCX_LCXS 0x000f0000
 240 #define MASK_LCX_LCX0 0x0000ffff
 241
 242 #define MASK_DBGSR_DE 0x1
 243 #define MASK_DBGSR_HALT 0x6
 244 #define MASK_DBGSR_SUSP 0x10
 245 #define MASK_DBGSR_PREVSUSP 0x20
 246 #define MASK_DBGSR_PEVT 0x40
 247 #define MASK_DBGSR_EVTSRC 0x1f00
 248
 249 #define TRICORE_HFLAG_KUU     0x3
 250 #define TRICORE_HFLAG_UM0     0x00002 /* user mode-0 flag          */
 251 #define TRICORE_HFLAG_UM1     0x00001 /* user mode-1 flag          */
 252 #define TRICORE_HFLAG_SM      0x00000 /* kernel mode flag          */
 253
 254 enum tricore_features {
 255     TRICORE_FEATURE_13,
 256     TRICORE_FEATURE_131,
 257     TRICORE_FEATURE_16,
 258     TRICORE_FEATURE_161,
 259 };
 260
 261 static inline int tricore_feature(CPUTriCoreState *env, int feature)
 262 {
 263     return (env->features & (1ULL << feature)) != 0;
 264 }
 265
 266 /* TriCore Traps Classes*/
 267 enum {
 268     TRAPC_NONE     = -1,
 269     TRAPC_MMU      = 0,
 270     TRAPC_PROT     = 1,
 271     TRAPC_INSN_ERR = 2,
 272     TRAPC_CTX_MNG  = 3,
 273     TRAPC_SYSBUS   = 4,
 274     TRAPC_ASSERT   = 5,
 275     TRAPC_SYSCALL  = 6,
 276     TRAPC_NMI      = 7,
 277     TRAPC_IRQ      = 8
 278 };
 279
 280 /* Class 0 TIN */
 281 enum {
 282     TIN0_VAF = 0,
 283     TIN0_VAP = 1,
 284 };
 285
 286 /* Class 1 TIN */
 287 enum {
 288     TIN1_PRIV = 1,
 289     TIN1_MPR  = 2,
 290     TIN1_MPW  = 3,
 291     TIN1_MPX  = 4,
 292     TIN1_MPP  = 5,
 293     TIN1_MPN  = 6,
 294     TIN1_GRWP = 7,
 295 };
 296
 297 /* Class 2 TIN */
 298 enum {
 299     TIN2_IOPC = 1,
 300     TIN2_UOPC = 2,
 301     TIN2_OPD  = 3,
 302     TIN2_ALN  = 4,
 303     TIN2_MEM  = 5,
 304 };
 305
 306 /* Class 3 TIN */
 307 enum {
 308     TIN3_FCD  = 1,
 309     TIN3_CDO  = 2,
 310     TIN3_CDU  = 3,
 311     TIN3_FCU  = 4,
 312     TIN3_CSU  = 5,
 313     TIN3_CTYP = 6,
 314     TIN3_NEST = 7,
 315 };
 316
 317 /* Class 4 TIN */
 318 enum {
 319     TIN4_PSE = 1,
 320     TIN4_DSE = 2,
 321     TIN4_DAE = 3,
 322     TIN4_CAE = 4,
 323     TIN4_PIE = 5,
 324     TIN4_DIE = 6,
 325 };
 326
 327 /* Class 5 TIN */
 328 enum {
 329     TIN5_OVF  = 1,
 330     TIN5_SOVF = 1,
 331 };
 332
 333 /* Class 6 TIN
 334  *
 335  * Is always TIN6_SYS
 336  */
 337
 338 /* Class 7 TIN */
 339 enum {
 340     TIN7_NMI = 0,
 341 };
 342
 343 uint32_t psw_read(CPUTriCoreState *env);
 344 void psw_write(CPUTriCoreState *env, uint32_t val);
 345 int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
 346 int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
 347
 348 void fpu_set_state(CPUTriCoreState *env);
 349
 350 #define MMU_USER_IDX 2
 351
 352 void tricore_cpu_list(void);
 353
 354 #define cpu_list tricore_cpu_list
 355
 356 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
 357 {
 358     return 0;
 359 }
 360
 361 #include "exec/cpu-all.h"
 362
 363 void cpu_state_reset(CPUTriCoreState *s);
 364 void tricore_tcg_init(void);
 365
 366 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
 367                                         target_ulong *cs_base, uint32_t *flags)
 368 {
 369     *pc = env->PC;
 370     *cs_base = 0;
 371     *flags = 0;
 372 }
 373
 374 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
 375 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
 376 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
 377
 378 /* helpers.c */
 379 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 380                           MMUAccessType access_type, int mmu_idx,
 381                           bool probe, uintptr_t retaddr);
 382
 383 #endif /* TRICORE_CPU_H */