MAINTAINERS: Make section QOM cover hw/core/*bus.c as well
[qemu/armbru.git] / include / hw / i2c / aspeed_i2c.h
blobf1b9e5bf91e2c9645a0765f920dce4c1e9e3793c
1 /*
2 * ASPEED AST2400 I2C Controller
4 * Copyright (C) 2016 IBM Corp.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #ifndef ASPEED_I2C_H
22 #define ASPEED_I2C_H
24 #include "hw/i2c/i2c.h"
25 #include "hw/sysbus.h"
27 #define TYPE_ASPEED_I2C "aspeed.i2c"
28 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
29 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
30 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
31 #define ASPEED_I2C(obj) \
32 OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C)
34 #define ASPEED_I2C_NR_BUSSES 16
35 #define ASPEED_I2C_MAX_POOL_SIZE 0x800
37 struct AspeedI2CState;
39 typedef struct AspeedI2CBus {
40 struct AspeedI2CState *controller;
42 MemoryRegion mr;
44 I2CBus *bus;
45 uint8_t id;
46 qemu_irq irq;
48 uint32_t ctrl;
49 uint32_t timing[2];
50 uint32_t intr_ctrl;
51 uint32_t intr_status;
52 uint32_t cmd;
53 uint32_t buf;
54 uint32_t pool_ctrl;
55 uint32_t dma_addr;
56 uint32_t dma_len;
57 } AspeedI2CBus;
59 typedef struct AspeedI2CState {
60 SysBusDevice parent_obj;
62 MemoryRegion iomem;
63 qemu_irq irq;
65 uint32_t intr_status;
66 uint32_t ctrl_global;
67 MemoryRegion pool_iomem;
68 uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
70 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
71 MemoryRegion *dram_mr;
72 AddressSpace dram_as;
73 } AspeedI2CState;
75 #define ASPEED_I2C_CLASS(klass) \
76 OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C)
77 #define ASPEED_I2C_GET_CLASS(obj) \
78 OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C)
80 typedef struct AspeedI2CClass {
81 SysBusDeviceClass parent_class;
83 uint8_t num_busses;
84 uint8_t reg_size;
85 uint8_t gap;
86 qemu_irq (*bus_get_irq)(AspeedI2CBus *);
88 uint64_t pool_size;
89 hwaddr pool_base;
90 uint8_t *(*bus_pool_base)(AspeedI2CBus *);
91 bool check_sram;
92 bool has_dma;
94 } AspeedI2CClass;
96 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);
98 #endif /* ASPEED_I2C_H */