include/hw/i386/apic_internal.h

   1 /*
   2  *  APIC support - internal interfaces
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20
  21 #ifndef QEMU_APIC_INTERNAL_H
  22 #define QEMU_APIC_INTERNAL_H
  23
  24 #include "cpu.h"
  25 #include "exec/memory.h"
  26 #include "qemu/timer.h"
  27 #include "target/i386/cpu-qom.h"
  28
  29 /* APIC Local Vector Table */
  30 #define APIC_LVT_TIMER                  0
  31 #define APIC_LVT_THERMAL                1
  32 #define APIC_LVT_PERFORM                2
  33 #define APIC_LVT_LINT0                  3
  34 #define APIC_LVT_LINT1                  4
  35 #define APIC_LVT_ERROR                  5
  36 #define APIC_LVT_NB                     6
  37
  38 /* APIC delivery modes */
  39 #define APIC_DM_FIXED                   0
  40 #define APIC_DM_LOWPRI                  1
  41 #define APIC_DM_SMI                     2
  42 #define APIC_DM_NMI                     4
  43 #define APIC_DM_INIT                    5
  44 #define APIC_DM_SIPI                    6
  45 #define APIC_DM_EXTINT                  7
  46
  47 /* APIC destination mode */
  48 #define APIC_DESTMODE_FLAT              0xf
  49 #define APIC_DESTMODE_CLUSTER           1
  50
  51 #define APIC_TRIGGER_EDGE               0
  52 #define APIC_TRIGGER_LEVEL              1
  53
  54 #define APIC_VECTOR_MASK                0xff
  55 #define APIC_DCR_MASK                   0xf
  56
  57 #define APIC_LVT_TIMER_SHIFT            17
  58 #define APIC_LVT_MASKED_SHIFT           16
  59 #define APIC_LVT_LEVEL_TRIGGER_SHIFT    15
  60 #define APIC_LVT_REMOTE_IRR_SHIFT       14
  61 #define APIC_LVT_INT_POLARITY_SHIFT     13
  62 #define APIC_LVT_DELIV_STS_SHIFT        12
  63 #define APIC_LVT_DELIV_MOD_SHIFT        8
  64
  65 #define APIC_LVT_TIMER_TSCDEADLINE      (2 << APIC_LVT_TIMER_SHIFT)
  66 #define APIC_LVT_TIMER_PERIODIC         (1 << APIC_LVT_TIMER_SHIFT)
  67 #define APIC_LVT_MASKED                 (1 << APIC_LVT_MASKED_SHIFT)
  68 #define APIC_LVT_LEVEL_TRIGGER          (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
  69 #define APIC_LVT_REMOTE_IRR             (1 << APIC_LVT_REMOTE_IRR_SHIFT)
  70 #define APIC_LVT_INT_POLARITY           (1 << APIC_LVT_INT_POLARITY_SHIFT)
  71 #define APIC_LVT_DELIV_STS              (1 << APIC_LVT_DELIV_STS_SHIFT)
  72 #define APIC_LVT_DELIV_MOD              (7 << APIC_LVT_DELIV_MOD_SHIFT)
  73
  74 #define APIC_ESR_ILL_ADDRESS_SHIFT      7
  75 #define APIC_ESR_RECV_ILL_VECT_SHIFT    6
  76 #define APIC_ESR_SEND_ILL_VECT_SHIFT    5
  77 #define APIC_ESR_RECV_ACCEPT_SHIFT      3
  78 #define APIC_ESR_SEND_ACCEPT_SHIFT      2
  79 #define APIC_ESR_RECV_CHECK_SUM_SHIFT   1
  80
  81 #define APIC_ESR_ILLEGAL_ADDRESS        (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
  82 #define APIC_ESR_RECV_ILLEGAL_VECT      (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
  83 #define APIC_ESR_SEND_ILLEGAL_VECT      (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
  84 #define APIC_ESR_RECV_ACCEPT            (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
  85 #define APIC_ESR_SEND_ACCEPT            (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
  86 #define APIC_ESR_RECV_CHECK_SUM         (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
  87 #define APIC_ESR_SEND_CHECK_SUM         1
  88
  89 #define APIC_ICR_DEST_SHIFT             24
  90 #define APIC_ICR_DEST_SHORT_SHIFT       18
  91 #define APIC_ICR_TRIGGER_MOD_SHIFT      15
  92 #define APIC_ICR_LEVEL_SHIFT            14
  93 #define APIC_ICR_DELIV_STS_SHIFT        12
  94 #define APIC_ICR_DEST_MOD_SHIFT         11
  95 #define APIC_ICR_DELIV_MOD_SHIFT        8
  96
  97 #define APIC_ICR_DEST_SHORT             (3 << APIC_ICR_DEST_SHORT_SHIFT)
  98 #define APIC_ICR_TRIGGER_MOD            (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
  99 #define APIC_ICR_LEVEL                  (1 << APIC_ICR_LEVEL_SHIFT)
 100 #define APIC_ICR_DELIV_STS              (1 << APIC_ICR_DELIV_STS_SHIFT)
 101 #define APIC_ICR_DEST_MOD               (1 << APIC_ICR_DEST_MOD_SHIFT)
 102 #define APIC_ICR_DELIV_MOD              (7 << APIC_ICR_DELIV_MOD_SHIFT)
 103
 104 #define APIC_PR_CLASS_SHIFT             4
 105 #define APIC_PR_SUB_CLASS               0xf
 106
 107 #define APIC_LOGDEST_XAPIC_SHIFT        4
 108 #define APIC_LOGDEST_XAPIC_ID           0xf
 109
 110 #define APIC_LOGDEST_X2APIC_SHIFT       16
 111 #define APIC_LOGDEST_X2APIC_ID          0xffff
 112
 113 #define APIC_SPURIO_FOCUS_SHIFT         9
 114 #define APIC_SPURIO_ENABLED_SHIFT       8
 115
 116 #define APIC_SPURIO_FOCUS               (1 << APIC_SPURIO_FOCUS_SHIFT)
 117 #define APIC_SPURIO_ENABLED             (1 << APIC_SPURIO_ENABLED_SHIFT)
 118
 119 #define APIC_SV_DIRECTED_IO             (1 << 12)
 120 #define APIC_SV_ENABLE                  (1 << 8)
 121
 122 #define VAPIC_ENABLE_BIT                0
 123 #define VAPIC_ENABLE_MASK               (1 << VAPIC_ENABLE_BIT)
 124
 125 typedef struct APICCommonState APICCommonState;
 126
 127 #define TYPE_APIC_COMMON "apic-common"
 128 #define APIC_COMMON(obj) \
 129      OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
 130 #define APIC_COMMON_CLASS(klass) \
 131      OBJECT_CLASS_CHECK(APICCommonClass, (klass), TYPE_APIC_COMMON)
 132 #define APIC_COMMON_GET_CLASS(obj) \
 133      OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
 134
 135 typedef struct APICCommonClass
 136 {
 137     DeviceClass parent_class;
 138
 139     DeviceRealize realize;
 140     DeviceUnrealize unrealize;
 141     void (*set_base)(APICCommonState *s, uint64_t val);
 142     void (*set_tpr)(APICCommonState *s, uint8_t val);
 143     uint8_t (*get_tpr)(APICCommonState *s);
 144     void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
 145     void (*vapic_base_update)(APICCommonState *s);
 146     void (*external_nmi)(APICCommonState *s);
 147     void (*pre_save)(APICCommonState *s);
 148     void (*post_load)(APICCommonState *s);
 149     void (*reset)(APICCommonState *s);
 150     /* send_msi emulates an APIC bus and its proper place would be in a new
 151      * device, but it's convenient to have it here for now.
 152      */
 153     void (*send_msi)(MSIMessage *msi);
 154 } APICCommonClass;
 155
 156 struct APICCommonState {
 157     /*< private >*/
 158     DeviceState parent_obj;
 159     /*< public >*/
 160
 161     MemoryRegion io_memory;
 162     X86CPU *cpu;
 163     uint32_t apicbase;
 164     uint8_t id; /* legacy APIC ID */
 165     uint32_t initial_apic_id;
 166     uint8_t version;
 167     uint8_t arb_id;
 168     uint8_t tpr;
 169     uint32_t spurious_vec;
 170     uint8_t log_dest;
 171     uint8_t dest_mode;
 172     uint32_t isr[8];  /* in service register */
 173     uint32_t tmr[8];  /* trigger mode register */
 174     uint32_t irr[8]; /* interrupt request register */
 175     uint32_t lvt[APIC_LVT_NB];
 176     uint32_t esr; /* error register */
 177     uint32_t icr[2];
 178
 179     uint32_t divide_conf;
 180     int count_shift;
 181     uint32_t initial_count;
 182     int64_t initial_count_load_time;
 183     int64_t next_time;
 184     QEMUTimer *timer;
 185     int64_t timer_expiry;
 186     int sipi_vector;
 187     int wait_for_sipi;
 188
 189     uint32_t vapic_control;
 190     DeviceState *vapic;
 191     hwaddr vapic_paddr; /* note: persistence via kvmvapic */
 192     bool legacy_instance_id;
 193 };
 194
 195 typedef struct VAPICState {
 196     uint8_t tpr;
 197     uint8_t isr;
 198     uint8_t zero;
 199     uint8_t irr;
 200     uint8_t enabled;
 201 } QEMU_PACKED VAPICState;
 202
 203 extern bool apic_report_tpr_access;
 204
 205 void apic_report_irq_delivered(int delivered);
 206 bool apic_next_timer(APICCommonState *s, int64_t current_time);
 207 void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
 208 void apic_enable_vapic(DeviceState *d, hwaddr paddr);
 209
 210 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
 211                              TPRAccess access);
 212
 213 int apic_get_ppr(APICCommonState *s);
 214
 215 static inline void apic_set_bit(uint32_t *tab, int index)
 216 {
 217     int i, mask;
 218     i = index >> 5;
 219     mask = 1 << (index & 0x1f);
 220     tab[i] |= mask;
 221 }
 222
 223 static inline int apic_get_bit(uint32_t *tab, int index)
 224 {
 225     int i, mask;
 226     i = index >> 5;
 227     mask = 1 << (index & 0x1f);
 228     return !!(tab[i] & mask);
 229 }
 230
 231 APICCommonClass *apic_get_class(void);
 232
 233 #endif /* QEMU_APIC_INTERNAL_H */