include/hw/i386/intel_iommu.h

   1 /*
   2  * QEMU emulation of an Intel IOMMU (VT-d)
   3  *   (DMA Remapping device)
   4  *
   5  * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
   6  * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #ifndef INTEL_IOMMU_H
  23 #define INTEL_IOMMU_H
  24
  25 #include "hw/i386/x86-iommu.h"
  26 #include "qemu/iova-tree.h"
  27
  28 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
  29 #define INTEL_IOMMU_DEVICE(obj) \
  30      OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
  31
  32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
  33
  34 /* DMAR Hardware Unit Definition address (IOMMU unit) */
  35 #define Q35_HOST_BRIDGE_IOMMU_ADDR  0xfed90000ULL
  36
  37 #define VTD_PCI_BUS_MAX             256
  38 #define VTD_PCI_SLOT_MAX            32
  39 #define VTD_PCI_FUNC_MAX            8
  40 #define VTD_PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  41 #define VTD_PCI_FUNC(devfn)         ((devfn) & 0x07)
  42 #define VTD_SID_TO_BUS(sid)         (((sid) >> 8) & 0xff)
  43 #define VTD_SID_TO_DEVFN(sid)       ((sid) & 0xff)
  44
  45 #define DMAR_REG_SIZE               0x230
  46 #define VTD_HOST_AW_39BIT           39
  47 #define VTD_HOST_AW_48BIT           48
  48 #define VTD_HOST_ADDRESS_WIDTH      VTD_HOST_AW_39BIT
  49 #define VTD_HAW_MASK(aw)            ((1ULL << (aw)) - 1)
  50
  51 #define DMAR_REPORT_F_INTR          (1)
  52
  53 #define  VTD_MSI_ADDR_HI_MASK        (0xffffffff00000000ULL)
  54 #define  VTD_MSI_ADDR_HI_SHIFT       (32)
  55 #define  VTD_MSI_ADDR_LO_MASK        (0x00000000ffffffffULL)
  56
  57 typedef struct VTDContextEntry VTDContextEntry;
  58 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
  59 typedef struct IntelIOMMUState IntelIOMMUState;
  60 typedef struct VTDAddressSpace VTDAddressSpace;
  61 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
  62 typedef struct VTDBus VTDBus;
  63 typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
  64 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
  65 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
  66 typedef struct VTDPASIDEntry VTDPASIDEntry;
  67
  68 /* Context-Entry */
  69 struct VTDContextEntry {
  70     union {
  71         struct {
  72             uint64_t lo;
  73             uint64_t hi;
  74         };
  75         struct {
  76             uint64_t val[4];
  77         };
  78     };
  79 };
  80
  81 struct VTDContextCacheEntry {
  82     /* The cache entry is obsolete if
  83      * context_cache_gen!=IntelIOMMUState.context_cache_gen
  84      */
  85     uint32_t context_cache_gen;
  86     struct VTDContextEntry context_entry;
  87 };
  88
  89 /* PASID Directory Entry */
  90 struct VTDPASIDDirEntry {
  91     uint64_t val;
  92 };
  93
  94 /* PASID Table Entry */
  95 struct VTDPASIDEntry {
  96     uint64_t val[8];
  97 };
  98
  99 struct VTDAddressSpace {
 100     PCIBus *bus;
 101     uint8_t devfn;
 102     AddressSpace as;
 103     IOMMUMemoryRegion iommu;
 104     MemoryRegion root;          /* The root container of the device */
 105     MemoryRegion nodmar;        /* The alias of shared nodmar MR */
 106     MemoryRegion iommu_ir;      /* Interrupt region: 0xfeeXXXXX */
 107     IntelIOMMUState *iommu_state;
 108     VTDContextCacheEntry context_cache_entry;
 109     QLIST_ENTRY(VTDAddressSpace) next;
 110     /* Superset of notifier flags that this address space has */
 111     IOMMUNotifierFlag notifier_flags;
 112     IOVATree *iova_tree;          /* Traces mapped IOVA ranges */
 113 };
 114
 115 struct VTDBus {
 116     PCIBus* bus;                /* A reference to the bus to provide translation for */
 117     /* A table of VTDAddressSpace objects indexed by devfn */
 118     VTDAddressSpace *dev_as[];
 119 };
 120
 121 struct VTDIOTLBEntry {
 122     uint64_t gfn;
 123     uint16_t domain_id;
 124     uint64_t slpte;
 125     uint64_t mask;
 126     uint8_t access_flags;
 127 };
 128
 129 /* VT-d Source-ID Qualifier types */
 130 enum {
 131     VTD_SQ_FULL = 0x00,     /* Full SID verification */
 132     VTD_SQ_IGN_3 = 0x01,    /* Ignore bit 3 */
 133     VTD_SQ_IGN_2_3 = 0x02,  /* Ignore bits 2 & 3 */
 134     VTD_SQ_IGN_1_3 = 0x03,  /* Ignore bits 1-3 */
 135     VTD_SQ_MAX,
 136 };
 137
 138 /* VT-d Source Validation Types */
 139 enum {
 140     VTD_SVT_NONE = 0x00,    /* No validation */
 141     VTD_SVT_ALL = 0x01,     /* Do full validation */
 142     VTD_SVT_BUS = 0x02,     /* Validate bus range */
 143     VTD_SVT_MAX,
 144 };
 145
 146 /* Interrupt Remapping Table Entry Definition */
 147 union VTD_IR_TableEntry {
 148     struct {
 149 #ifdef HOST_WORDS_BIGENDIAN
 150         uint32_t __reserved_1:8;     /* Reserved 1 */
 151         uint32_t vector:8;           /* Interrupt Vector */
 152         uint32_t irte_mode:1;        /* IRTE Mode */
 153         uint32_t __reserved_0:3;     /* Reserved 0 */
 154         uint32_t __avail:4;          /* Available spaces for software */
 155         uint32_t delivery_mode:3;    /* Delivery Mode */
 156         uint32_t trigger_mode:1;     /* Trigger Mode */
 157         uint32_t redir_hint:1;       /* Redirection Hint */
 158         uint32_t dest_mode:1;        /* Destination Mode */
 159         uint32_t fault_disable:1;    /* Fault Processing Disable */
 160         uint32_t present:1;          /* Whether entry present/available */
 161 #else
 162         uint32_t present:1;          /* Whether entry present/available */
 163         uint32_t fault_disable:1;    /* Fault Processing Disable */
 164         uint32_t dest_mode:1;        /* Destination Mode */
 165         uint32_t redir_hint:1;       /* Redirection Hint */
 166         uint32_t trigger_mode:1;     /* Trigger Mode */
 167         uint32_t delivery_mode:3;    /* Delivery Mode */
 168         uint32_t __avail:4;          /* Available spaces for software */
 169         uint32_t __reserved_0:3;     /* Reserved 0 */
 170         uint32_t irte_mode:1;        /* IRTE Mode */
 171         uint32_t vector:8;           /* Interrupt Vector */
 172         uint32_t __reserved_1:8;     /* Reserved 1 */
 173 #endif
 174         uint32_t dest_id;            /* Destination ID */
 175         uint16_t source_id;          /* Source-ID */
 176 #ifdef HOST_WORDS_BIGENDIAN
 177         uint64_t __reserved_2:44;    /* Reserved 2 */
 178         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 179         uint64_t sid_q:2;            /* Source-ID Qualifier */
 180 #else
 181         uint64_t sid_q:2;            /* Source-ID Qualifier */
 182         uint64_t sid_vtype:2;        /* Source-ID Validation Type */
 183         uint64_t __reserved_2:44;    /* Reserved 2 */
 184 #endif
 185     } QEMU_PACKED irte;
 186     uint64_t data[2];
 187 };
 188
 189 #define VTD_IR_INT_FORMAT_COMPAT     (0) /* Compatible Interrupt */
 190 #define VTD_IR_INT_FORMAT_REMAP      (1) /* Remappable Interrupt */
 191
 192 /* Programming format for MSI/MSI-X addresses */
 193 union VTD_IR_MSIAddress {
 194     struct {
 195 #ifdef HOST_WORDS_BIGENDIAN
 196         uint32_t __head:12;          /* Should always be: 0x0fee */
 197         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 198         uint32_t int_mode:1;         /* Interrupt format */
 199         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 200         uint32_t index_h:1;          /* Interrupt index bit 15 */
 201         uint32_t __not_care:2;
 202 #else
 203         uint32_t __not_care:2;
 204         uint32_t index_h:1;          /* Interrupt index bit 15 */
 205         uint32_t sub_valid:1;        /* SHV: Sub-Handle Valid bit */
 206         uint32_t int_mode:1;         /* Interrupt format */
 207         uint32_t index_l:15;         /* Interrupt index bit 14-0 */
 208         uint32_t __head:12;          /* Should always be: 0x0fee */
 209 #endif
 210     } QEMU_PACKED addr;
 211     uint32_t data;
 212 };
 213
 214 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
 215 #define VTD_IR_MSI_DATA          (0)
 216
 217 /* The iommu (DMAR) device state struct */
 218 struct IntelIOMMUState {
 219     X86IOMMUState x86_iommu;
 220     MemoryRegion csrmem;
 221     MemoryRegion mr_nodmar;
 222     MemoryRegion mr_ir;
 223     MemoryRegion mr_sys_alias;
 224     uint8_t csr[DMAR_REG_SIZE];     /* register values */
 225     uint8_t wmask[DMAR_REG_SIZE];   /* R/W bytes */
 226     uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
 227     uint8_t womask[DMAR_REG_SIZE];  /* WO (write only - read returns 0) */
 228     uint32_t version;
 229
 230     bool caching_mode;              /* RO - is cap CM enabled? */
 231     bool scalable_mode;             /* RO - is Scalable Mode supported? */
 232
 233     dma_addr_t root;                /* Current root table pointer */
 234     bool root_scalable;             /* Type of root table (scalable or not) */
 235     bool dmar_enabled;              /* Set if DMA remapping is enabled */
 236
 237     uint16_t iq_head;               /* Current invalidation queue head */
 238     uint16_t iq_tail;               /* Current invalidation queue tail */
 239     dma_addr_t iq;                  /* Current invalidation queue pointer */
 240     uint16_t iq_size;               /* IQ Size in number of entries */
 241     bool iq_dw;                     /* IQ descriptor width 256bit or not */
 242     bool qi_enabled;                /* Set if the QI is enabled */
 243     uint8_t iq_last_desc_type;      /* The type of last completed descriptor */
 244
 245     /* The index of the Fault Recording Register to be used next.
 246      * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
 247      */
 248     uint16_t next_frcd_reg;
 249
 250     uint64_t cap;                   /* The value of capability reg */
 251     uint64_t ecap;                  /* The value of extended capability reg */
 252
 253     uint32_t context_cache_gen;     /* Should be in [1,MAX] */
 254     GHashTable *iotlb;              /* IOTLB */
 255
 256     GHashTable *vtd_as_by_busptr;   /* VTDBus objects indexed by PCIBus* reference */
 257     VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
 258     /* list of registered notifiers */
 259     QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
 260
 261     /* interrupt remapping */
 262     bool intr_enabled;              /* Whether guest enabled IR */
 263     dma_addr_t intr_root;           /* Interrupt remapping table pointer */
 264     uint32_t intr_size;             /* Number of IR table entries */
 265     bool intr_eime;                 /* Extended interrupt mode enabled */
 266     OnOffAuto intr_eim;             /* Toggle for EIM cabability */
 267     bool buggy_eim;                 /* Force buggy EIM unless eim=off */
 268     uint8_t aw_bits;                /* Host/IOVA address width (in bits) */
 269     bool dma_drain;                 /* Whether DMA r/w draining enabled */
 270
 271     /*
 272      * Protects IOMMU states in general.  Currently it protects the
 273      * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
 274      */
 275     QemuMutex iommu_lock;
 276 };
 277
 278 /* Find the VTD Address space associated with the given bus pointer,
 279  * create a new one if none exists
 280  */
 281 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
 282
 283 #endif