include/hw/i386/x86.h

   1 /*
   2  * Copyright (c) 2019 Red Hat, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2 or later, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef HW_I386_X86_H
  18 #define HW_I386_X86_H
  19
  20 #include "qemu-common.h"
  21 #include "exec/hwaddr.h"
  22 #include "qemu/notify.h"
  23
  24 #include "hw/i386/topology.h"
  25 #include "hw/boards.h"
  26 #include "hw/nmi.h"
  27 #include "hw/isa/isa.h"
  28 #include "hw/i386/ioapic.h"
  29
  30 typedef struct {
  31     /*< private >*/
  32     MachineClass parent;
  33
  34     /*< public >*/
  35
  36     /* TSC rate migration: */
  37     bool save_tsc_khz;
  38     /* Enables contiguous-apic-ID mode */
  39     bool compat_apic_id_mode;
  40 } X86MachineClass;
  41
  42 typedef struct {
  43     /*< private >*/
  44     MachineState parent;
  45
  46     /*< public >*/
  47
  48     /* Pointers to devices and objects: */
  49     ISADevice *rtc;
  50     FWCfgState *fw_cfg;
  51     qemu_irq *gsi;
  52     GMappedFile *initrd_mapped_file;
  53
  54     /* Configuration options: */
  55     uint64_t max_ram_below_4g;
  56
  57     /* RAM information (sizes, addresses, configuration): */
  58     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  59
  60     /* CPU and apic information: */
  61     bool apic_xrupt_override;
  62     unsigned apic_id_limit;
  63     uint16_t boot_cpus;
  64     unsigned smp_dies;
  65
  66     OnOffAuto smm;
  67     OnOffAuto acpi;
  68
  69     /* Apic id specific handlers */
  70     uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info,
  71                                     unsigned cpu_index);
  72     void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_info,
  73                                  X86CPUTopoIDs *topo_ids);
  74     apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info,
  75                                       const X86CPUTopoIDs *topo_ids);
  76     uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info);
  77
  78     /*
  79      * Address space used by IOAPIC device. All IOAPIC interrupts
  80      * will be translated to MSI messages in the address space.
  81      */
  82     AddressSpace *ioapic_as;
  83 } X86MachineState;
  84
  85 #define X86_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
  86 #define X86_MACHINE_SMM              "smm"
  87 #define X86_MACHINE_ACPI             "acpi"
  88
  89 #define TYPE_X86_MACHINE   MACHINE_TYPE_NAME("x86")
  90 #define X86_MACHINE(obj) \
  91     OBJECT_CHECK(X86MachineState, (obj), TYPE_X86_MACHINE)
  92 #define X86_MACHINE_GET_CLASS(obj) \
  93     OBJECT_GET_CLASS(X86MachineClass, obj, TYPE_X86_MACHINE)
  94 #define X86_MACHINE_CLASS(class) \
  95     OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE)
  96
  97 void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
  98
  99 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
 100                                     unsigned int cpu_index);
 101
 102 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
 103 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
 104 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
 105                                              unsigned cpu_index);
 106 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
 107 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
 108
 109 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw);
 110
 111 void x86_load_linux(X86MachineState *x86ms,
 112                     FWCfgState *fw_cfg,
 113                     int acpi_data_size,
 114                     bool pvh_enabled,
 115                     bool linuxboot_dma_enabled);
 116
 117 bool x86_machine_is_smm_enabled(X86MachineState *x86ms);
 118 bool x86_machine_is_acpi_enabled(X86MachineState *x86ms);
 119
 120 /* Global System Interrupts */
 121
 122 #define GSI_NUM_PINS IOAPIC_NUM_PINS
 123
 124 typedef struct GSIState {
 125     qemu_irq i8259_irq[ISA_NUM_IRQS];
 126     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 127 } GSIState;
 128
 129 qemu_irq x86_allocate_cpu_irq(void);
 130 void gsi_handler(void *opaque, int n, int level);
 131 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 132
 133 /* hpet.c */
 134 extern int no_hpet;
 135
 136 #endif