include/hw/intc/arm_gic_common.h

   1 /*
   2  * ARM GIC support
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation, either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef HW_ARM_GIC_COMMON_H
  22 #define HW_ARM_GIC_COMMON_H
  23
  24 #include "hw/sysbus.h"
  25
  26 /* Maximum number of possible interrupts, determined by the GIC architecture */
  27 #define GIC_MAXIRQ 1020
  28 /* First 32 are private to each CPU (SGIs and PPIs). */
  29 #define GIC_INTERNAL 32
  30 #define GIC_NR_SGIS 16
  31 /* Maximum number of possible CPU interfaces, determined by GIC architecture */
  32 #define GIC_NCPU 8
  33 /* Maximum number of possible CPU interfaces with their respective vCPU */
  34 #define GIC_NCPU_VCPU (GIC_NCPU * 2)
  35
  36 #define MAX_NR_GROUP_PRIO 128
  37 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
  38
  39 #define GIC_MIN_BPR 0
  40 #define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
  41
  42 /* Architectural maximum number of list registers in the virtual interface */
  43 #define GIC_MAX_LR 64
  44
  45 /* Only 32 priority levels and 32 preemption levels in the vCPU interfaces */
  46 #define GIC_VIRT_MAX_GROUP_PRIO_BITS 5
  47 #define GIC_VIRT_MAX_NR_GROUP_PRIO (1 << GIC_VIRT_MAX_GROUP_PRIO_BITS)
  48 #define GIC_VIRT_NR_APRS (GIC_VIRT_MAX_NR_GROUP_PRIO / 32)
  49
  50 #define GIC_VIRT_MIN_BPR 2
  51 #define GIC_VIRT_MIN_ABPR (GIC_VIRT_MIN_BPR + 1)
  52
  53 typedef struct gic_irq_state {
  54     /* The enable bits are only banked for per-cpu interrupts.  */
  55     uint8_t enabled;
  56     uint8_t pending;
  57     uint8_t active;
  58     uint8_t level;
  59     bool model; /* 0 = N:N, 1 = 1:N */
  60     bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
  61     uint8_t group;
  62 } gic_irq_state;
  63
  64 typedef struct GICState {
  65     /*< private >*/
  66     SysBusDevice parent_obj;
  67     /*< public >*/
  68
  69     qemu_irq parent_irq[GIC_NCPU];
  70     qemu_irq parent_fiq[GIC_NCPU];
  71     qemu_irq parent_virq[GIC_NCPU];
  72     qemu_irq parent_vfiq[GIC_NCPU];
  73     qemu_irq maintenance_irq[GIC_NCPU];
  74
  75     /* GICD_CTLR; for a GIC with the security extensions the NS banked version
  76      * of this register is just an alias of bit 1 of the S banked version.
  77      */
  78     uint32_t ctlr;
  79     /* GICC_CTLR; again, the NS banked version is just aliases of bits of
  80      * the S banked register, so our state only needs to store the S version.
  81      */
  82     uint32_t cpu_ctlr[GIC_NCPU_VCPU];
  83
  84     gic_irq_state irq_state[GIC_MAXIRQ];
  85     uint8_t irq_target[GIC_MAXIRQ];
  86     uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
  87     uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
  88     /* For each SGI on the target CPU, we store 8 bits
  89      * indicating which source CPUs have made this SGI
  90      * pending on the target CPU. These correspond to
  91      * the bytes in the GIC_SPENDSGIR* registers as
  92      * read by the target CPU.
  93      */
  94     uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
  95
  96     uint16_t priority_mask[GIC_NCPU_VCPU];
  97     uint16_t running_priority[GIC_NCPU_VCPU];
  98     uint16_t current_pending[GIC_NCPU_VCPU];
  99     uint32_t n_prio_bits;
 100
 101     /* If we present the GICv2 without security extensions to a guest,
 102      * the guest can configure the GICC_CTLR to configure group 1 binary point
 103      * in the abpr.
 104      * For a GIC with Security Extensions we use use bpr for the
 105      * secure copy and abpr as storage for the non-secure copy of the register.
 106      */
 107     uint8_t  bpr[GIC_NCPU_VCPU];
 108     uint8_t  abpr[GIC_NCPU_VCPU];
 109
 110     /* The APR is implementation defined, so we choose a layout identical to
 111      * the KVM ABI layout for QEMU's implementation of the gic:
 112      * If an interrupt for preemption level X is active, then
 113      *   APRn[X mod 32] == 0b1,  where n = X / 32
 114      * otherwise the bit is clear.
 115      */
 116     uint32_t apr[GIC_NR_APRS][GIC_NCPU];
 117     uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
 118
 119     /* Virtual interface control registers */
 120     uint32_t h_hcr[GIC_NCPU];
 121     uint32_t h_misr[GIC_NCPU];
 122     uint32_t h_lr[GIC_MAX_LR][GIC_NCPU];
 123     uint32_t h_apr[GIC_NCPU];
 124
 125     /* Number of LRs implemented in this GIC instance */
 126     uint32_t num_lrs;
 127
 128     uint32_t num_cpu;
 129
 130     MemoryRegion iomem; /* Distributor */
 131     /* This is just so we can have an opaque pointer which identifies
 132      * both this GIC and which CPU interface we should be accessing.
 133      */
 134     struct GICState *backref[GIC_NCPU];
 135     MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
 136     MemoryRegion vifaceiomem[GIC_NCPU + 1]; /* Virtual interfaces */
 137     MemoryRegion vcpuiomem; /* vCPU interface */
 138
 139     uint32_t num_irq;
 140     uint32_t revision;
 141     bool security_extn;
 142     bool virt_extn;
 143     bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
 144     int dev_fd; /* kvm device fd if backed by kvm vgic support */
 145     Error *migration_blocker;
 146 } GICState;
 147
 148 #define TYPE_ARM_GIC_COMMON "arm_gic_common"
 149 #define ARM_GIC_COMMON(obj) \
 150      OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON)
 151 #define ARM_GIC_COMMON_CLASS(klass) \
 152      OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
 153 #define ARM_GIC_COMMON_GET_CLASS(obj) \
 154      OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
 155
 156 typedef struct ARMGICCommonClass {
 157     /*< private >*/
 158     SysBusDeviceClass parent_class;
 159     /*< public >*/
 160
 161     void (*pre_save)(GICState *s);
 162     void (*post_load)(GICState *s);
 163 } ARMGICCommonClass;
 164
 165 void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
 166                             const MemoryRegionOps *ops,
 167                             const MemoryRegionOps *virt_ops);
 168
 169 #endif