include/hw/pci-host/spapr.h

   1 /*
   2  * QEMU SPAPR PCI BUS definitions
   3  *
   4  * Copyright (c) 2011 Alexey Kardashevskiy <aik@au1.ibm.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef PCI_HOST_SPAPR_H
  21 #define PCI_HOST_SPAPR_H
  22
  23 #include "hw/ppc/spapr.h"
  24 #include "hw/pci/pci.h"
  25 #include "hw/pci/pci_host.h"
  26 #include "hw/ppc/xics.h"
  27
  28 #define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
  29
  30 #define SPAPR_PCI_HOST_BRIDGE(obj) \
  31     OBJECT_CHECK(SpaprPhbState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
  32
  33 #define SPAPR_PCI_DMA_MAX_WINDOWS    2
  34
  35 typedef struct SpaprPhbState SpaprPhbState;
  36
  37 typedef struct SpaprPciMsi {
  38     uint32_t first_irq;
  39     uint32_t num;
  40 } SpaprPciMsi;
  41
  42 typedef struct SpaprPciMsiMig {
  43     uint32_t key;
  44     SpaprPciMsi value;
  45 } SpaprPciMsiMig;
  46
  47 typedef struct SpaprPciLsi {
  48     uint32_t irq;
  49 } SpaprPciLsi;
  50
  51 typedef struct SpaprPhbPciNvGpuConfig SpaprPhbPciNvGpuConfig;
  52
  53 struct SpaprPhbState {
  54     PCIHostState parent_obj;
  55
  56     uint32_t index;
  57     uint64_t buid;
  58     char *dtbusname;
  59     bool dr_enabled;
  60
  61     MemoryRegion memspace, iospace;
  62     hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
  63     uint64_t mem64_win_pciaddr;
  64     hwaddr io_win_addr, io_win_size;
  65     MemoryRegion mem32window, mem64window, iowindow, msiwindow;
  66
  67     uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
  68     hwaddr dma_win_addr, dma_win_size;
  69     AddressSpace iommu_as;
  70     MemoryRegion iommu_root;
  71
  72     SpaprPciLsi lsi_table[PCI_NUM_PINS];
  73
  74     GHashTable *msi;
  75     /* Temporary cache for migration purposes */
  76     int32_t msi_devs_num;
  77     SpaprPciMsiMig *msi_devs;
  78
  79     QLIST_ENTRY(SpaprPhbState) list;
  80
  81     bool ddw_enabled;
  82     uint64_t page_size_mask;
  83     uint64_t dma64_win_addr;
  84
  85     uint32_t numa_node;
  86
  87     bool pcie_ecs; /* Allow access to PCIe extended config space? */
  88
  89     /* Fields for migration compatibility hacks */
  90     bool pre_2_8_migration;
  91     uint32_t mig_liobn;
  92     hwaddr mig_mem_win_addr, mig_mem_win_size;
  93     hwaddr mig_io_win_addr, mig_io_win_size;
  94     hwaddr nv2_gpa_win_addr;
  95     hwaddr nv2_atsd_win_addr;
  96     SpaprPhbPciNvGpuConfig *nvgpus;
  97 };
  98
  99 #define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
 100 #define SPAPR_PCI_MEM32_WIN_SIZE     \
 101     ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
 102 #define SPAPR_PCI_MEM64_WIN_SIZE     0x10000000000ULL /* 1 TiB */
 103
 104 /* All PCI outbound windows will be within this range */
 105 #define SPAPR_PCI_BASE               (1ULL << 45) /* 32 TiB */
 106 #define SPAPR_PCI_LIMIT              (1ULL << 46) /* 64 TiB */
 107
 108 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
 109                         SPAPR_PCI_MEM64_WIN_SIZE - 1)
 110
 111 #define SPAPR_PCI_IO_WIN_SIZE        0x10000
 112
 113 #define SPAPR_PCI_MSI_WINDOW         0x40000000000ULL
 114
 115 #define SPAPR_PCI_NV2RAM64_WIN_BASE  SPAPR_PCI_LIMIT
 116 #define SPAPR_PCI_NV2RAM64_WIN_SIZE  (2 * TiB) /* For up to 6 GPUs 256GB each */
 117
 118 /* Max number of these GPUsper a physical box */
 119 #define NVGPU_MAX_NUM                6
 120 /* Max number of NVLinks per GPU in any physical box */
 121 #define NVGPU_MAX_LINKS              3
 122
 123 /*
 124  * GPU RAM starts at 64TiB so huge DMA window to cover it all ends at 128TiB
 125  * which is enough. We do not need DMA for ATSD so we put them at 128TiB.
 126  */
 127 #define SPAPR_PCI_NV2ATSD_WIN_BASE   (128 * TiB)
 128 #define SPAPR_PCI_NV2ATSD_WIN_SIZE   (NVGPU_MAX_NUM * NVGPU_MAX_LINKS * \
 129                                       64 * KiB)
 130
 131 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
 132                  uint32_t intc_phandle, void *fdt, int *node_offset);
 133
 134 void spapr_pci_rtas_init(void);
 135
 136 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid);
 137 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
 138                               uint32_t config_addr);
 139
 140 /* DRC callbacks */
 141 void spapr_phb_remove_pci_device_cb(DeviceState *dev);
 142 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 143                           void *fdt, int *fdt_start_offset, Error **errp);
 144
 145 /* VFIO EEH hooks */
 146 #ifdef CONFIG_LINUX
 147 bool spapr_phb_eeh_available(SpaprPhbState *sphb);
 148 int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
 149                                   unsigned int addr, int option);
 150 int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb, int *state);
 151 int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option);
 152 int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb);
 153 void spapr_phb_vfio_reset(DeviceState *qdev);
 154 void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp);
 155 void spapr_phb_nvgpu_free(SpaprPhbState *sphb);
 156 void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
 157                                  Error **errp);
 158 void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt);
 159 void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt, int offset,
 160                                         SpaprPhbState *sphb);
 161 #else
 162 static inline bool spapr_phb_eeh_available(SpaprPhbState *sphb)
 163 {
 164     return false;
 165 }
 166 static inline int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb,
 167                                                 unsigned int addr, int option)
 168 {
 169     return RTAS_OUT_HW_ERROR;
 170 }
 171 static inline int spapr_phb_vfio_eeh_get_state(SpaprPhbState *sphb,
 172                                                int *state)
 173 {
 174     return RTAS_OUT_HW_ERROR;
 175 }
 176 static inline int spapr_phb_vfio_eeh_reset(SpaprPhbState *sphb, int option)
 177 {
 178     return RTAS_OUT_HW_ERROR;
 179 }
 180 static inline int spapr_phb_vfio_eeh_configure(SpaprPhbState *sphb)
 181 {
 182     return RTAS_OUT_HW_ERROR;
 183 }
 184 static inline void spapr_phb_vfio_reset(DeviceState *qdev)
 185 {
 186 }
 187 static inline void spapr_phb_nvgpu_setup(SpaprPhbState *sphb, Error **errp)
 188 {
 189 }
 190 static inline void spapr_phb_nvgpu_free(SpaprPhbState *sphb)
 191 {
 192 }
 193 static inline void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt,
 194                                                int bus_off, Error **errp)
 195 {
 196 }
 197 static inline void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb,
 198                                                    void *fdt)
 199 {
 200 }
 201 static inline void spapr_phb_nvgpu_populate_pcidev_dt(PCIDevice *dev, void *fdt,
 202                                                       int offset,
 203                                                       SpaprPhbState *sphb)
 204 {
 205 }
 206 #endif
 207
 208 void spapr_phb_dma_reset(SpaprPhbState *sphb);
 209
 210 static inline unsigned spapr_phb_windows_supported(SpaprPhbState *sphb)
 211 {
 212     return sphb->ddw_enabled ? SPAPR_PCI_DMA_MAX_WINDOWS : 1;
 213 }
 214
 215 #endif /* PCI_HOST_SPAPR_H */