include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "exec/memory.h"
   5 #include "sysemu/dma.h"
   6
   7 /* PCI includes legacy ISA access.  */
   8 #include "hw/isa/isa.h"
   9
  10 #include "hw/pci/pcie.h"
  11
  12 extern bool pci_available;
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  21 #define PCI_BUS_MAX             256
  22 #define PCI_DEVFN_MAX           256
  23 #define PCI_SLOT_MAX            32
  24 #define PCI_FUNC_MAX            8
  25
  26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  27 #include "hw/pci/pci_ids.h"
  28
  29 /* QEMU-specific Vendor and Device ID definitions */
  30
  31 /* IBM (0x1014) */
  32 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  33 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  34
  35 /* Hitachi (0x1054) */
  36 #define PCI_VENDOR_ID_HITACHI            0x1054
  37 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  38
  39 /* Apple (0x106b) */
  40 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  44 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  45
  46 /* Realtek (0x10ec) */
  47 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  48
  49 /* Xilinx (0x10ee) */
  50 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  51
  52 /* Marvell (0x11ab) */
  53 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  54
  55 /* QEMU/Bochs VGA (0x1234) */
  56 #define PCI_VENDOR_ID_QEMU               0x1234
  57 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  58 #define PCI_DEVICE_ID_QEMU_IPMI          0x1112
  59
  60 /* VMWare (0x15ad) */
  61 #define PCI_VENDOR_ID_VMWARE             0x15ad
  62 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  63 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  64 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  65 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  66 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  67 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  68 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  69
  70 /* Intel (0x8086) */
  71 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  72 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  73 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  74
  75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  76 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  78 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  79
  80 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  81 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  82 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  84 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  85 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  86 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  87 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  88 #define PCI_DEVICE_ID_VIRTIO_PMEM        0x1013
  89 #define PCI_DEVICE_ID_VIRTIO_IOMMU       0x1014
  90
  91 #define PCI_VENDOR_ID_REDHAT             0x1b36
  92 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  93 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  94 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  95 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  96 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  97 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  98 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  99 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
 100 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
 101 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 102 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 103 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 104 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 105 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 106 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 107 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 108
 109 #define FMT_PCIBUS                      PRIx64
 110
 111 typedef uint64_t pcibus_t;
 112
 113 struct PCIHostDeviceAddress {
 114     unsigned int domain;
 115     unsigned int bus;
 116     unsigned int slot;
 117     unsigned int function;
 118 };
 119
 120 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 121                                 uint32_t address, uint32_t data, int len);
 122 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 123                                    uint32_t address, int len);
 124 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 125                                 pcibus_t addr, pcibus_t size, int type);
 126 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 127
 128 typedef struct PCIIORegion {
 129     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 130 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 131     pcibus_t size;
 132     uint8_t type;
 133     MemoryRegion *memory;
 134     MemoryRegion *address_space;
 135 } PCIIORegion;
 136
 137 #define PCI_ROM_SLOT 6
 138 #define PCI_NUM_REGIONS 7
 139
 140 enum {
 141     QEMU_PCI_VGA_MEM,
 142     QEMU_PCI_VGA_IO_LO,
 143     QEMU_PCI_VGA_IO_HI,
 144     QEMU_PCI_VGA_NUM_REGIONS,
 145 };
 146
 147 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 148 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 149 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 150 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 151 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 152 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 153
 154 #include "hw/pci/pci_regs.h"
 155
 156 /* PCI HEADER_TYPE */
 157 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 158
 159 /* Size of the standard PCI config header */
 160 #define PCI_CONFIG_HEADER_SIZE 0x40
 161 /* Size of the standard PCI config space */
 162 #define PCI_CONFIG_SPACE_SIZE 0x100
 163 /* Size of the standard PCIe config space: 4KB */
 164 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 165
 166 #define PCI_NUM_PINS 4 /* A-D */
 167
 168 /* Bits in cap_present field. */
 169 enum {
 170     QEMU_PCI_CAP_MSI = 0x1,
 171     QEMU_PCI_CAP_MSIX = 0x2,
 172     QEMU_PCI_CAP_EXPRESS = 0x4,
 173
 174     /* multifunction capable device */
 175 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 176     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 177
 178     /* command register SERR bit enabled - unused since QEMU v5.0 */
 179 #define QEMU_PCI_CAP_SERR_BITNR 4
 180     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 181     /* Standard hot plug controller. */
 182 #define QEMU_PCI_SHPC_BITNR 5
 183     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 184 #define QEMU_PCI_SLOTID_BITNR 6
 185     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 186     /* PCI Express capability - Power Controller Present */
 187 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 188     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 189     /* Link active status in endpoint capability is always set */
 190 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 191     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 192 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 193     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 194 };
 195
 196 #define TYPE_PCI_DEVICE "pci-device"
 197 #define PCI_DEVICE(obj) \
 198      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 199 #define PCI_DEVICE_CLASS(klass) \
 200      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 201 #define PCI_DEVICE_GET_CLASS(obj) \
 202      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 203
 204 /* Implemented by devices that can be plugged on PCI Express buses */
 205 #define INTERFACE_PCIE_DEVICE "pci-express-device"
 206
 207 /* Implemented by devices that can be plugged on Conventional PCI buses */
 208 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
 209
 210 typedef struct PCIINTxRoute {
 211     enum {
 212         PCI_INTX_ENABLED,
 213         PCI_INTX_INVERTED,
 214         PCI_INTX_DISABLED,
 215     } mode;
 216     int irq;
 217 } PCIINTxRoute;
 218
 219 typedef struct PCIDeviceClass {
 220     DeviceClass parent_class;
 221
 222     void (*realize)(PCIDevice *dev, Error **errp);
 223     PCIUnregisterFunc *exit;
 224     PCIConfigReadFunc *config_read;
 225     PCIConfigWriteFunc *config_write;
 226
 227     uint16_t vendor_id;
 228     uint16_t device_id;
 229     uint8_t revision;
 230     uint16_t class_id;
 231     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 232     uint16_t subsystem_id;              /* only for header type = 0 */
 233
 234     /*
 235      * pci-to-pci bridge or normal device.
 236      * This doesn't mean pci host switch.
 237      * When card bus bridge is supported, this would be enhanced.
 238      */
 239     bool is_bridge;
 240
 241     /* rom bar */
 242     const char *romfile;
 243 } PCIDeviceClass;
 244
 245 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 246 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 247                                       MSIMessage msg);
 248 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 249 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 250                                       unsigned int vector_start,
 251                                       unsigned int vector_end);
 252
 253 enum PCIReqIDType {
 254     PCI_REQ_ID_INVALID = 0,
 255     PCI_REQ_ID_BDF,
 256     PCI_REQ_ID_SECONDARY_BUS,
 257     PCI_REQ_ID_MAX,
 258 };
 259 typedef enum PCIReqIDType PCIReqIDType;
 260
 261 struct PCIReqIDCache {
 262     PCIDevice *dev;
 263     PCIReqIDType type;
 264 };
 265 typedef struct PCIReqIDCache PCIReqIDCache;
 266
 267 struct PCIDevice {
 268     DeviceState qdev;
 269     bool partially_hotplugged;
 270
 271     /* PCI config space */
 272     uint8_t *config;
 273
 274     /* Used to enable config checks on load. Note that writable bits are
 275      * never checked even if set in cmask. */
 276     uint8_t *cmask;
 277
 278     /* Used to implement R/W bytes */
 279     uint8_t *wmask;
 280
 281     /* Used to implement RW1C(Write 1 to Clear) bytes */
 282     uint8_t *w1cmask;
 283
 284     /* Used to allocate config space for capabilities. */
 285     uint8_t *used;
 286
 287     /* the following fields are read only */
 288     int32_t devfn;
 289     /* Cached device to fetch requester ID from, to avoid the PCI
 290      * tree walking every time we invoke PCI request (e.g.,
 291      * MSI). For conventional PCI root complex, this field is
 292      * meaningless. */
 293     PCIReqIDCache requester_id_cache;
 294     char name[64];
 295     PCIIORegion io_regions[PCI_NUM_REGIONS];
 296     AddressSpace bus_master_as;
 297     MemoryRegion bus_master_container_region;
 298     MemoryRegion bus_master_enable_region;
 299
 300     /* do not access the following fields */
 301     PCIConfigReadFunc *config_read;
 302     PCIConfigWriteFunc *config_write;
 303
 304     /* Legacy PCI VGA regions */
 305     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 306     bool has_vga;
 307
 308     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 309     uint8_t irq_state;
 310
 311     /* Capability bits */
 312     uint32_t cap_present;
 313
 314     /* Offset of MSI-X capability in config space */
 315     uint8_t msix_cap;
 316
 317     /* MSI-X entries */
 318     int msix_entries_nr;
 319
 320     /* Space to store MSIX table & pending bit array */
 321     uint8_t *msix_table;
 322     uint8_t *msix_pba;
 323     /* MemoryRegion container for msix exclusive BAR setup */
 324     MemoryRegion msix_exclusive_bar;
 325     /* Memory Regions for MSIX table and pending bit entries. */
 326     MemoryRegion msix_table_mmio;
 327     MemoryRegion msix_pba_mmio;
 328     /* Reference-count for entries actually in use by driver. */
 329     unsigned *msix_entry_used;
 330     /* MSIX function mask set or MSIX disabled */
 331     bool msix_function_masked;
 332     /* Version id needed for VMState */
 333     int32_t version_id;
 334
 335     /* Offset of MSI capability in config space */
 336     uint8_t msi_cap;
 337
 338     /* PCI Express */
 339     PCIExpressDevice exp;
 340
 341     /* SHPC */
 342     SHPCDevice *shpc;
 343
 344     /* Location of option rom */
 345     char *romfile;
 346     bool has_rom;
 347     MemoryRegion rom;
 348     uint32_t rom_bar;
 349
 350     /* INTx routing notifier */
 351     PCIINTxRoutingNotifier intx_routing_notifier;
 352
 353     /* MSI-X notifiers */
 354     MSIVectorUseNotifier msix_vector_use_notifier;
 355     MSIVectorReleaseNotifier msix_vector_release_notifier;
 356     MSIVectorPollNotifier msix_vector_poll_notifier;
 357
 358     /* ID of standby device in net_failover pair */
 359     char *failover_pair_id;
 360 };
 361
 362 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 363                       uint8_t attr, MemoryRegion *memory);
 364 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 365                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 366 void pci_unregister_vga(PCIDevice *pci_dev);
 367 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 368
 369 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 370                        uint8_t offset, uint8_t size,
 371                        Error **errp);
 372
 373 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 374
 375 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 376
 377
 378 uint32_t pci_default_read_config(PCIDevice *d,
 379                                  uint32_t address, int len);
 380 void pci_default_write_config(PCIDevice *d,
 381                               uint32_t address, uint32_t val, int len);
 382 void pci_device_save(PCIDevice *s, QEMUFile *f);
 383 int pci_device_load(PCIDevice *s, QEMUFile *f);
 384 MemoryRegion *pci_address_space(PCIDevice *dev);
 385 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 386
 387 /*
 388  * Should not normally be used by devices. For use by sPAPR target
 389  * where QEMU emulates firmware.
 390  */
 391 int pci_bar(PCIDevice *d, int reg);
 392
 393 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 394 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 395 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 396
 397 #define TYPE_PCI_BUS "PCI"
 398 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 399 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 400 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 401 #define TYPE_PCIE_BUS "PCIE"
 402
 403 bool pci_bus_is_express(PCIBus *bus);
 404
 405 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 406                               const char *name,
 407                               MemoryRegion *address_space_mem,
 408                               MemoryRegion *address_space_io,
 409                               uint8_t devfn_min, const char *typename);
 410 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
 411                          MemoryRegion *address_space_mem,
 412                          MemoryRegion *address_space_io,
 413                          uint8_t devfn_min, const char *typename);
 414 void pci_root_bus_cleanup(PCIBus *bus);
 415 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 416                   void *irq_opaque, int nirq);
 417 void pci_bus_irqs_cleanup(PCIBus *bus);
 418 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 419 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 420 static inline int pci_swizzle(int slot, int pin)
 421 {
 422     return (slot + pin) % PCI_NUM_PINS;
 423 }
 424 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 425 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
 426                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 427                               void *irq_opaque,
 428                               MemoryRegion *address_space_mem,
 429                               MemoryRegion *address_space_io,
 430                               uint8_t devfn_min, int nirq,
 431                               const char *typename);
 432 void pci_unregister_root_bus(PCIBus *bus);
 433 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 434 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 435 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 436 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 437 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 438                                           PCIINTxRoutingNotifier notifier);
 439 void pci_device_reset(PCIDevice *dev);
 440
 441 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 442                                const char *default_model,
 443                                const char *default_devaddr);
 444
 445 PCIDevice *pci_vga_init(PCIBus *bus);
 446
 447 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
 448 {
 449     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
 450 }
 451 int pci_bus_num(PCIBus *s);
 452 static inline int pci_dev_bus_num(const PCIDevice *dev)
 453 {
 454     return pci_bus_num(pci_get_bus(dev));
 455 }
 456
 457 int pci_bus_numa_node(PCIBus *bus);
 458 void pci_for_each_device(PCIBus *bus, int bus_num,
 459                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 460                          void *opaque);
 461 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 462                                  void (*fn)(PCIBus *bus, PCIDevice *d,
 463                                             void *opaque),
 464                                  void *opaque);
 465 void pci_for_each_bus_depth_first(PCIBus *bus,
 466                                   void *(*begin)(PCIBus *bus, void *parent_state),
 467                                   void (*end)(PCIBus *bus, void *state),
 468                                   void *parent_state);
 469 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 470
 471 /* Use this wrapper when specific scan order is not required. */
 472 static inline
 473 void pci_for_each_bus(PCIBus *bus,
 474                       void (*fn)(PCIBus *bus, void *opaque),
 475                       void *opaque)
 476 {
 477     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 478 }
 479
 480 PCIBus *pci_device_root_bus(const PCIDevice *d);
 481 const char *pci_root_bus_path(PCIDevice *dev);
 482 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 483 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 484 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 485
 486 void pci_device_deassert_intx(PCIDevice *dev);
 487
 488 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 489
 490 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 491 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 492
 493 static inline void
 494 pci_set_byte(uint8_t *config, uint8_t val)
 495 {
 496     *config = val;
 497 }
 498
 499 static inline uint8_t
 500 pci_get_byte(const uint8_t *config)
 501 {
 502     return *config;
 503 }
 504
 505 static inline void
 506 pci_set_word(uint8_t *config, uint16_t val)
 507 {
 508     stw_le_p(config, val);
 509 }
 510
 511 static inline uint16_t
 512 pci_get_word(const uint8_t *config)
 513 {
 514     return lduw_le_p(config);
 515 }
 516
 517 static inline void
 518 pci_set_long(uint8_t *config, uint32_t val)
 519 {
 520     stl_le_p(config, val);
 521 }
 522
 523 static inline uint32_t
 524 pci_get_long(const uint8_t *config)
 525 {
 526     return ldl_le_p(config);
 527 }
 528
 529 /*
 530  * PCI capabilities and/or their fields
 531  * are generally DWORD aligned only so
 532  * mechanism used by pci_set/get_quad()
 533  * must be tolerant to unaligned pointers
 534  *
 535  */
 536 static inline void
 537 pci_set_quad(uint8_t *config, uint64_t val)
 538 {
 539     stq_le_p(config, val);
 540 }
 541
 542 static inline uint64_t
 543 pci_get_quad(const uint8_t *config)
 544 {
 545     return ldq_le_p(config);
 546 }
 547
 548 static inline void
 549 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 550 {
 551     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 552 }
 553
 554 static inline void
 555 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 556 {
 557     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 558 }
 559
 560 static inline void
 561 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 562 {
 563     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 564 }
 565
 566 static inline void
 567 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 568 {
 569     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 570 }
 571
 572 static inline void
 573 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 574 {
 575     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 576 }
 577
 578 static inline void
 579 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 580 {
 581     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 582 }
 583
 584 /*
 585  * helper functions to do bit mask operation on configuration space.
 586  * Just to set bit, use test-and-set and discard returned value.
 587  * Just to clear bit, use test-and-clear and discard returned value.
 588  * NOTE: They aren't atomic.
 589  */
 590 static inline uint8_t
 591 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 592 {
 593     uint8_t val = pci_get_byte(config);
 594     pci_set_byte(config, val & ~mask);
 595     return val & mask;
 596 }
 597
 598 static inline uint8_t
 599 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 600 {
 601     uint8_t val = pci_get_byte(config);
 602     pci_set_byte(config, val | mask);
 603     return val & mask;
 604 }
 605
 606 static inline uint16_t
 607 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 608 {
 609     uint16_t val = pci_get_word(config);
 610     pci_set_word(config, val & ~mask);
 611     return val & mask;
 612 }
 613
 614 static inline uint16_t
 615 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 616 {
 617     uint16_t val = pci_get_word(config);
 618     pci_set_word(config, val | mask);
 619     return val & mask;
 620 }
 621
 622 static inline uint32_t
 623 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 624 {
 625     uint32_t val = pci_get_long(config);
 626     pci_set_long(config, val & ~mask);
 627     return val & mask;
 628 }
 629
 630 static inline uint32_t
 631 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 632 {
 633     uint32_t val = pci_get_long(config);
 634     pci_set_long(config, val | mask);
 635     return val & mask;
 636 }
 637
 638 static inline uint64_t
 639 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 640 {
 641     uint64_t val = pci_get_quad(config);
 642     pci_set_quad(config, val & ~mask);
 643     return val & mask;
 644 }
 645
 646 static inline uint64_t
 647 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 648 {
 649     uint64_t val = pci_get_quad(config);
 650     pci_set_quad(config, val | mask);
 651     return val & mask;
 652 }
 653
 654 /* Access a register specified by a mask */
 655 static inline void
 656 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 657 {
 658     uint8_t val = pci_get_byte(config);
 659     uint8_t rval = reg << ctz32(mask);
 660     pci_set_byte(config, (~mask & val) | (mask & rval));
 661 }
 662
 663 static inline uint8_t
 664 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 665 {
 666     uint8_t val = pci_get_byte(config);
 667     return (val & mask) >> ctz32(mask);
 668 }
 669
 670 static inline void
 671 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 672 {
 673     uint16_t val = pci_get_word(config);
 674     uint16_t rval = reg << ctz32(mask);
 675     pci_set_word(config, (~mask & val) | (mask & rval));
 676 }
 677
 678 static inline uint16_t
 679 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 680 {
 681     uint16_t val = pci_get_word(config);
 682     return (val & mask) >> ctz32(mask);
 683 }
 684
 685 static inline void
 686 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 687 {
 688     uint32_t val = pci_get_long(config);
 689     uint32_t rval = reg << ctz32(mask);
 690     pci_set_long(config, (~mask & val) | (mask & rval));
 691 }
 692
 693 static inline uint32_t
 694 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 695 {
 696     uint32_t val = pci_get_long(config);
 697     return (val & mask) >> ctz32(mask);
 698 }
 699
 700 static inline void
 701 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 702 {
 703     uint64_t val = pci_get_quad(config);
 704     uint64_t rval = reg << ctz32(mask);
 705     pci_set_quad(config, (~mask & val) | (mask & rval));
 706 }
 707
 708 static inline uint64_t
 709 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 710 {
 711     uint64_t val = pci_get_quad(config);
 712     return (val & mask) >> ctz32(mask);
 713 }
 714
 715 PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
 716                                     const char *name);
 717 PCIDevice *pci_new(int devfn, const char *name);
 718 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
 719
 720 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 721                                            bool multifunction,
 722                                            const char *name);
 723 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 724
 725 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
 726
 727 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 728 void pci_set_irq(PCIDevice *pci_dev, int level);
 729
 730 static inline void pci_irq_assert(PCIDevice *pci_dev)
 731 {
 732     pci_set_irq(pci_dev, 1);
 733 }
 734
 735 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 736 {
 737     pci_set_irq(pci_dev, 0);
 738 }
 739
 740 /*
 741  * FIXME: PCI does not work this way.
 742  * All the callers to this method should be fixed.
 743  */
 744 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 745 {
 746     pci_irq_assert(pci_dev);
 747     pci_irq_deassert(pci_dev);
 748 }
 749
 750 static inline int pci_is_express(const PCIDevice *d)
 751 {
 752     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 753 }
 754
 755 static inline int pci_is_express_downstream_port(const PCIDevice *d)
 756 {
 757     uint8_t type;
 758
 759     if (!pci_is_express(d) || !d->exp.exp_cap) {
 760         return 0;
 761     }
 762
 763     type = pcie_cap_get_type(d);
 764
 765     return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
 766 }
 767
 768 static inline uint32_t pci_config_size(const PCIDevice *d)
 769 {
 770     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 771 }
 772
 773 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 774 {
 775     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
 776 }
 777
 778 uint16_t pci_requester_id(PCIDevice *dev);
 779
 780 /* DMA access functions */
 781 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 782 {
 783     return &dev->bus_master_as;
 784 }
 785
 786 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 787                              void *buf, dma_addr_t len, DMADirection dir)
 788 {
 789     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 790     return 0;
 791 }
 792
 793 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 794                                void *buf, dma_addr_t len)
 795 {
 796     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 797 }
 798
 799 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 800                                 const void *buf, dma_addr_t len)
 801 {
 802     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 803 }
 804
 805 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 806     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 807                                                    dma_addr_t addr)     \
 808     {                                                                   \
 809         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 810     }                                                                   \
 811     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 812                                         dma_addr_t addr, uint##_bits##_t val) \
 813     {                                                                   \
 814         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 815     }
 816
 817 PCI_DMA_DEFINE_LDST(ub, b, 8);
 818 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 819 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 820 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 821 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 822 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 823 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 824
 825 #undef PCI_DMA_DEFINE_LDST
 826
 827 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 828                                 dma_addr_t *plen, DMADirection dir)
 829 {
 830     void *buf;
 831
 832     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 833     return buf;
 834 }
 835
 836 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 837                                  DMADirection dir, dma_addr_t access_len)
 838 {
 839     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 840 }
 841
 842 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 843                                        int alloc_hint)
 844 {
 845     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 846 }
 847
 848 extern const VMStateDescription vmstate_pci_device;
 849
 850 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 851     .name       = (stringify(_field)),                               \
 852     .size       = sizeof(PCIDevice),                                 \
 853     .vmsd       = &vmstate_pci_device,                               \
 854     .flags      = VMS_STRUCT,                                        \
 855     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 856 }
 857
 858 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 859     .name       = (stringify(_field)),                               \
 860     .size       = sizeof(PCIDevice),                                 \
 861     .vmsd       = &vmstate_pci_device,                               \
 862     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 863     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 864 }
 865
 866 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 867
 868 #endif