include/hw/ppc/pnv_xive.h

   1 /*
   2  * QEMU PowerPC XIVE interrupt controller model
   3  *
   4  * Copyright (c) 2017-2019, IBM Corporation.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #ifndef PPC_PNV_XIVE_H
  11 #define PPC_PNV_XIVE_H
  12
  13 #include "hw/ppc/xive.h"
  14
  15 struct PnvChip;
  16
  17 #define TYPE_PNV_XIVE "pnv-xive"
  18 #define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE)
  19 #define PNV_XIVE_CLASS(klass)                                   \
  20     OBJECT_CLASS_CHECK(PnvXiveClass, (klass), TYPE_PNV_XIVE)
  21 #define PNV_XIVE_GET_CLASS(obj)                                 \
  22     OBJECT_GET_CLASS(PnvXiveClass, (obj), TYPE_PNV_XIVE)
  23
  24 #define XIVE_BLOCK_MAX      16
  25
  26 #define XIVE_TABLE_BLK_MAX  16  /* Block Scope Table (0-15) */
  27 #define XIVE_TABLE_MIG_MAX  16  /* Migration Register Table (1-15) */
  28 #define XIVE_TABLE_VDT_MAX  16  /* VDT Domain Table (0-15) */
  29 #define XIVE_TABLE_EDT_MAX  64  /* EDT Domain Table (0-63) */
  30
  31 typedef struct PnvXive {
  32     XiveRouter    parent_obj;
  33
  34     /* Owning chip */
  35     struct PnvChip *chip;
  36
  37     /* XSCOM addresses giving access to the controller registers */
  38     MemoryRegion  xscom_regs;
  39
  40     /* Main MMIO regions that can be configured by FW */
  41     MemoryRegion  ic_mmio;
  42     MemoryRegion    ic_reg_mmio;
  43     MemoryRegion    ic_notify_mmio;
  44     MemoryRegion    ic_lsi_mmio;
  45     MemoryRegion    tm_indirect_mmio;
  46     MemoryRegion  vc_mmio;
  47     MemoryRegion  pc_mmio;
  48     MemoryRegion  tm_mmio;
  49
  50     /*
  51      * IPI and END address spaces modeling the EDT segmentation in the
  52      * VC region
  53      */
  54     AddressSpace  ipi_as;
  55     MemoryRegion  ipi_mmio;
  56     MemoryRegion    ipi_edt_mmio;
  57
  58     AddressSpace  end_as;
  59     MemoryRegion  end_mmio;
  60     MemoryRegion    end_edt_mmio;
  61
  62     /* Shortcut values for the Main MMIO regions */
  63     hwaddr        ic_base;
  64     uint32_t      ic_shift;
  65     hwaddr        vc_base;
  66     uint32_t      vc_shift;
  67     hwaddr        pc_base;
  68     uint32_t      pc_shift;
  69     hwaddr        tm_base;
  70     uint32_t      tm_shift;
  71
  72     /* Our XIVE source objects for IPIs and ENDs */
  73     XiveSource    ipi_source;
  74     XiveENDSource end_source;
  75
  76     /* Interrupt controller registers */
  77     uint64_t      regs[0x300];
  78
  79     /*
  80      * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
  81      * These are in a SRAM protected by ECC.
  82      */
  83     uint64_t      vsds[5][XIVE_BLOCK_MAX];
  84
  85     /* Translation tables */
  86     uint64_t      blk[XIVE_TABLE_BLK_MAX];
  87     uint64_t      mig[XIVE_TABLE_MIG_MAX];
  88     uint64_t      vdt[XIVE_TABLE_VDT_MAX];
  89     uint64_t      edt[XIVE_TABLE_EDT_MAX];
  90 } PnvXive;
  91
  92 typedef struct PnvXiveClass {
  93     XiveRouterClass parent_class;
  94
  95     DeviceRealize parent_realize;
  96 } PnvXiveClass;
  97
  98 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
  99
 100 #endif /* PPC_PNV_XIVE_H */