MAINTAINERS: Make section QOM cover hw/core/*bus.c as well
[qemu/armbru.git] / include / hw / ppc / spapr_irq.h
blobca8cb442137455ae92a6c0bbad73b380288de3a3
1 /*
2 * QEMU PowerPC sPAPR IRQ backend definitions
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
10 #ifndef HW_SPAPR_IRQ_H
11 #define HW_SPAPR_IRQ_H
13 #include "target/ppc/cpu-qom.h"
16 * IRQ range offsets per device type
18 #define SPAPR_IRQ_IPI 0x0
20 #define SPAPR_XIRQ_BASE XICS_IRQ_BASE /* 0x1000 */
21 #define SPAPR_IRQ_EPOW (SPAPR_XIRQ_BASE + 0x0000)
22 #define SPAPR_IRQ_HOTPLUG (SPAPR_XIRQ_BASE + 0x0001)
23 #define SPAPR_IRQ_VIO (SPAPR_XIRQ_BASE + 0x0100) /* 256 VIO devices */
24 #define SPAPR_IRQ_PCI_LSI (SPAPR_XIRQ_BASE + 0x0200) /* 32+ PHBs devices */
26 /* Offset of the dynamic range covered by the bitmap allocator */
27 #define SPAPR_IRQ_MSI (SPAPR_XIRQ_BASE + 0x0300)
29 #define SPAPR_NR_XIRQS 0x1000
31 typedef struct SpaprMachineState SpaprMachineState;
33 typedef struct SpaprInterruptController SpaprInterruptController;
35 #define TYPE_SPAPR_INTC "spapr-interrupt-controller"
36 #define SPAPR_INTC(obj) \
37 INTERFACE_CHECK(SpaprInterruptController, (obj), TYPE_SPAPR_INTC)
38 #define SPAPR_INTC_CLASS(klass) \
39 OBJECT_CLASS_CHECK(SpaprInterruptControllerClass, (klass), TYPE_SPAPR_INTC)
40 #define SPAPR_INTC_GET_CLASS(obj) \
41 OBJECT_GET_CLASS(SpaprInterruptControllerClass, (obj), TYPE_SPAPR_INTC)
43 typedef struct SpaprInterruptControllerClass {
44 InterfaceClass parent;
46 int (*activate)(SpaprInterruptController *intc, uint32_t nr_servers,
47 Error **errp);
48 void (*deactivate)(SpaprInterruptController *intc);
51 * These methods will typically be called on all intcs, active and
52 * inactive
54 int (*cpu_intc_create)(SpaprInterruptController *intc,
55 PowerPCCPU *cpu, Error **errp);
56 void (*cpu_intc_reset)(SpaprInterruptController *intc, PowerPCCPU *cpu);
57 void (*cpu_intc_destroy)(SpaprInterruptController *intc, PowerPCCPU *cpu);
58 int (*claim_irq)(SpaprInterruptController *intc, int irq, bool lsi,
59 Error **errp);
60 void (*free_irq)(SpaprInterruptController *intc, int irq);
62 /* These methods should only be called on the active intc */
63 void (*set_irq)(SpaprInterruptController *intc, int irq, int val);
64 void (*print_info)(SpaprInterruptController *intc, Monitor *mon);
65 void (*dt)(SpaprInterruptController *intc, uint32_t nr_servers,
66 void *fdt, uint32_t phandle);
67 int (*post_load)(SpaprInterruptController *intc, int version_id);
68 } SpaprInterruptControllerClass;
70 void spapr_irq_update_active_intc(SpaprMachineState *spapr);
72 int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
73 PowerPCCPU *cpu, Error **errp);
74 void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu);
75 void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu);
76 void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon);
77 void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
78 void *fdt, uint32_t phandle);
80 uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr);
81 int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
82 Error **errp);
83 void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
85 typedef struct SpaprIrq {
86 bool xics;
87 bool xive;
88 } SpaprIrq;
90 extern SpaprIrq spapr_irq_xics;
91 extern SpaprIrq spapr_irq_xics_legacy;
92 extern SpaprIrq spapr_irq_xive;
93 extern SpaprIrq spapr_irq_dual;
95 void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
96 int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
97 void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
98 qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
99 int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
100 void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
101 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
103 typedef int (*SpaprInterruptControllerInitKvm)(SpaprInterruptController *,
104 uint32_t, Error **);
106 int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
107 SpaprInterruptController *intc,
108 uint32_t nr_servers,
109 Error **errp);
112 * XICS legacy routines
114 int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
115 #define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
117 #endif