include/hw/riscv/opentitan.h

   1 /*
   2  * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_OPENTITAN_H
  20 #define HW_OPENTITAN_H
  21
  22 #include "hw/riscv/riscv_hart.h"
  23
  24 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
  25 #define RISCV_IBEX_SOC(obj) \
  26     OBJECT_CHECK(LowRISCIbexSoCState, (obj), TYPE_RISCV_IBEX_SOC)
  27
  28 typedef struct LowRISCIbexSoCState {
  29     /*< private >*/
  30     SysBusDevice parent_obj;
  31
  32     /*< public >*/
  33     RISCVHartArrayState cpus;
  34     MemoryRegion flash_mem;
  35     MemoryRegion rom;
  36 } LowRISCIbexSoCState;
  37
  38 typedef struct OpenTitanState {
  39     /*< private >*/
  40     SysBusDevice parent_obj;
  41
  42     /*< public >*/
  43     LowRISCIbexSoCState soc;
  44 } OpenTitanState;
  45
  46 enum {
  47     IBEX_ROM,
  48     IBEX_RAM,
  49     IBEX_FLASH,
  50     IBEX_UART,
  51     IBEX_GPIO,
  52     IBEX_SPI,
  53     IBEX_FLASH_CTRL,
  54     IBEX_RV_TIMER,
  55     IBEX_AES,
  56     IBEX_HMAC,
  57     IBEX_PLIC,
  58     IBEX_PWRMGR,
  59     IBEX_RSTMGR,
  60     IBEX_CLKMGR,
  61     IBEX_PINMUX,
  62     IBEX_ALERT_HANDLER,
  63     IBEX_NMI_GEN,
  64     IBEX_USBDEV,
  65     IBEX_PADCTRL,
  66 };
  67
  68 #endif