include/hw/riscv/sifive_u.h

   1 /*
   2  * SiFive U series machine interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_U_H
  20 #define HW_SIFIVE_U_H
  21
  22 #include "hw/net/cadence_gem.h"
  23 #include "hw/riscv/riscv_hart.h"
  24 #include "hw/riscv/sifive_cpu.h"
  25 #include "hw/riscv/sifive_u_prci.h"
  26 #include "hw/riscv/sifive_u_otp.h"
  27
  28 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
  29 #define RISCV_U_SOC(obj) \
  30     OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
  31
  32 typedef struct SiFiveUSoCState {
  33     /*< private >*/
  34     DeviceState parent_obj;
  35
  36     /*< public >*/
  37     CPUClusterState e_cluster;
  38     CPUClusterState u_cluster;
  39     RISCVHartArrayState e_cpus;
  40     RISCVHartArrayState u_cpus;
  41     DeviceState *plic;
  42     SiFiveUPRCIState prci;
  43     SiFiveUOTPState otp;
  44     CadenceGEMState gem;
  45
  46     uint32_t serial;
  47 } SiFiveUSoCState;
  48
  49 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
  50 #define RISCV_U_MACHINE(obj) \
  51     OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
  52
  53 typedef struct SiFiveUState {
  54     /*< private >*/
  55     MachineState parent_obj;
  56
  57     /*< public >*/
  58     SiFiveUSoCState soc;
  59
  60     void *fdt;
  61     int fdt_size;
  62
  63     bool start_in_flash;
  64     uint32_t serial;
  65 } SiFiveUState;
  66
  67 enum {
  68     SIFIVE_U_DEBUG,
  69     SIFIVE_U_MROM,
  70     SIFIVE_U_CLINT,
  71     SIFIVE_U_L2LIM,
  72     SIFIVE_U_PLIC,
  73     SIFIVE_U_PRCI,
  74     SIFIVE_U_UART0,
  75     SIFIVE_U_UART1,
  76     SIFIVE_U_OTP,
  77     SIFIVE_U_FLASH0,
  78     SIFIVE_U_DRAM,
  79     SIFIVE_U_GEM,
  80     SIFIVE_U_GEM_MGMT
  81 };
  82
  83 enum {
  84     SIFIVE_U_UART0_IRQ = 4,
  85     SIFIVE_U_UART1_IRQ = 5,
  86     SIFIVE_U_GEM_IRQ = 0x35
  87 };
  88
  89 enum {
  90     SIFIVE_U_HFCLK_FREQ = 33333333,
  91     SIFIVE_U_RTCCLK_FREQ = 1000000
  92 };
  93
  94 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
  95 #define SIFIVE_U_COMPUTE_CPU_COUNT      4
  96
  97 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
  98 #define SIFIVE_U_PLIC_NUM_SOURCES 54
  99 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
 100 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
 101 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
 102 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
 103 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
 104 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
 105 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
 106
 107 #endif