include/hw/watchdog/wdt_imx2.h

   1 /*
   2  * Copyright (c) 2017, Impinj, Inc.
   3  *
   4  * i.MX2 Watchdog IP block
   5  *
   6  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef IMX2_WDT_H
  13 #define IMX2_WDT_H
  14
  15 #include "qemu/bitops.h"
  16 #include "hw/sysbus.h"
  17 #include "hw/irq.h"
  18 #include "hw/ptimer.h"
  19
  20 #define TYPE_IMX2_WDT "imx2.wdt"
  21 #define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT)
  22
  23 enum IMX2WdtRegisters {
  24     IMX2_WDT_WCR  = 0x0000, /* Control Register */
  25     IMX2_WDT_WSR  = 0x0002, /* Service Register */
  26     IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */
  27     IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */
  28     IMX2_WDT_WMCR = 0x0008, /* Misc Register */
  29 };
  30
  31 #define IMX2_WDT_MMIO_SIZE 0x000a
  32
  33 /* Control Register definitions */
  34 #define IMX2_WDT_WCR_WT         (0xFF << 8) /* Watchdog Timeout Field */
  35 #define IMX2_WDT_WCR_WDW        BIT(7)      /* WDOG Disable for Wait */
  36 #define IMX2_WDT_WCR_WDA        BIT(5)      /* WDOG Assertion */
  37 #define IMX2_WDT_WCR_SRS        BIT(4)      /* Software Reset Signal */
  38 #define IMX2_WDT_WCR_WDT        BIT(3)      /* WDOG Timeout Assertion */
  39 #define IMX2_WDT_WCR_WDE        BIT(2)      /* Watchdog Enable */
  40 #define IMX2_WDT_WCR_WDBG       BIT(1)      /* Watchdog Debug Enable */
  41 #define IMX2_WDT_WCR_WDZST      BIT(0)      /* Watchdog Timer Suspend */
  42
  43 #define IMX2_WDT_WCR_LOCK_MASK  (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \
  44                                  | IMX2_WDT_WCR_WDW)
  45
  46 /* Service Register definitions */
  47 #define IMX2_WDT_SEQ1           0x5555      /* service sequence 1 */
  48 #define IMX2_WDT_SEQ2           0xAAAA      /* service sequence 2 */
  49
  50 /* Reset Status Register definitions */
  51 #define IMX2_WDT_WRSR_TOUT      BIT(1)      /* Reset due to Timeout */
  52 #define IMX2_WDT_WRSR_SFTW      BIT(0)      /* Reset due to software reset */
  53
  54 /* Interrupt Control Register definitions */
  55 #define IMX2_WDT_WICR_WIE       BIT(15)     /* Interrupt Enable */
  56 #define IMX2_WDT_WICR_WTIS      BIT(14)     /* Interrupt Status */
  57 #define IMX2_WDT_WICR_WICT      0xff        /* Interrupt Timeout */
  58 #define IMX2_WDT_WICR_WICT_DEF  0x04        /* Default interrupt timeout (2s) */
  59
  60 #define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT)
  61
  62 /* Misc Control Register definitions */
  63 #define IMX2_WDT_WMCR_PDE       BIT(0)      /* Power-Down Enable */
  64
  65 typedef struct IMX2WdtState {
  66     /* <private> */
  67     SysBusDevice parent_obj;
  68
  69     /*< public >*/
  70     MemoryRegion mmio;
  71     qemu_irq irq;
  72
  73     struct ptimer_state *timer;
  74     struct ptimer_state *itimer;
  75
  76     bool pretimeout_support;
  77     bool wicr_locked;
  78
  79     uint16_t wcr;
  80     uint16_t wsr;
  81     uint16_t wrsr;
  82     uint16_t wicr;
  83     uint16_t wmcr;
  84
  85     bool wcr_locked;            /* affects WDZST, WDBG, and WDW */
  86     bool wcr_wde_locked;        /* affects WDE */
  87     bool wcr_wdt_locked;        /* affects WDT (never cleared) */
  88 } IMX2WdtState;
  89
  90 #endif /* IMX2_WDT_H */