hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu/units.h"
  33 #include "hw/loader.h"
  34 #include "hw/i2c/smbus_eeprom.h"
  35 #include "hw/rtc/mc146818rtc.h"
  36 #include "sysemu/kvm.h"
  37 #include "hw/kvm/clock.h"
  38 #include "hw/pci-host/q35.h"
  39 #include "hw/pci/pcie_port.h"
  40 #include "hw/qdev-properties.h"
  41 #include "hw/i386/x86.h"
  42 #include "hw/i386/pc.h"
  43 #include "hw/i386/ich9.h"
  44 #include "hw/i386/amd_iommu.h"
  45 #include "hw/i386/intel_iommu.h"
  46 #include "hw/display/ramfb.h"
  47 #include "hw/firmware/smbios.h"
  48 #include "hw/ide/pci.h"
  49 #include "hw/ide/ahci.h"
  50 #include "hw/usb.h"
  51 #include "qapi/error.h"
  52 #include "qemu/error-report.h"
  53 #include "sysemu/numa.h"
  54 #include "hw/hyperv/vmbus-bridge.h"
  55 #include "hw/mem/nvdimm.h"
  56 #include "hw/i386/acpi-build.h"
  57
  58 /* ICH9 AHCI has 6 ports */
  59 #define MAX_SATA_PORTS     6
  60
  61 struct ehci_companions {
  62     const char *name;
  63     int func;
  64     int port;
  65 };
  66
  67 static const struct ehci_companions ich9_1d[] = {
  68     { .name = "ich9-usb-uhci1", .func = 0, .port = 0 },
  69     { .name = "ich9-usb-uhci2", .func = 1, .port = 2 },
  70     { .name = "ich9-usb-uhci3", .func = 2, .port = 4 },
  71 };
  72
  73 static const struct ehci_companions ich9_1a[] = {
  74     { .name = "ich9-usb-uhci4", .func = 0, .port = 0 },
  75     { .name = "ich9-usb-uhci5", .func = 1, .port = 2 },
  76     { .name = "ich9-usb-uhci6", .func = 2, .port = 4 },
  77 };
  78
  79 static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
  80 {
  81     const struct ehci_companions *comp;
  82     PCIDevice *ehci, *uhci;
  83     BusState *usbbus;
  84     const char *name;
  85     int i;
  86
  87     switch (slot) {
  88     case 0x1d:
  89         name = "ich9-usb-ehci1";
  90         comp = ich9_1d;
  91         break;
  92     case 0x1a:
  93         name = "ich9-usb-ehci2";
  94         comp = ich9_1a;
  95         break;
  96     default:
  97         return -1;
  98     }
  99
 100     ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
 101     pci_realize_and_unref(ehci, bus, &error_fatal);
 102     usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
 103
 104     for (i = 0; i < 3; i++) {
 105         uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
 106                                      comp[i].name);
 107         qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
 108         qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
 109         pci_realize_and_unref(uhci, bus, &error_fatal);
 110     }
 111     return 0;
 112 }
 113
 114 /* PC hardware initialisation */
 115 static void pc_q35_init(MachineState *machine)
 116 {
 117     PCMachineState *pcms = PC_MACHINE(machine);
 118     PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
 119     X86MachineState *x86ms = X86_MACHINE(machine);
 120     Q35PCIHost *q35_host;
 121     PCIHostState *phb;
 122     PCIBus *host_bus;
 123     PCIDevice *lpc;
 124     DeviceState *lpc_dev;
 125     BusState *idebus[MAX_SATA_PORTS];
 126     ISADevice *rtc_state;
 127     MemoryRegion *system_io = get_system_io();
 128     MemoryRegion *pci_memory;
 129     MemoryRegion *rom_memory;
 130     MemoryRegion *ram_memory;
 131     GSIState *gsi_state;
 132     ISABus *isa_bus;
 133     int i;
 134     ICH9LPCState *ich9_lpc;
 135     PCIDevice *ahci;
 136     ram_addr_t lowmem;
 137     DriveInfo *hd[MAX_SATA_PORTS];
 138     MachineClass *mc = MACHINE_GET_CLASS(machine);
 139     bool acpi_pcihp;
 140
 141     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
 142      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
 143      * also known as MMCFG).
 144      * If it doesn't, we need to split it in chunks below and above 4G.
 145      * In any case, try to make sure that guest addresses aligned at
 146      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
 147      */
 148     if (machine->ram_size >= 0xb0000000) {
 149         lowmem = 0x80000000;
 150     } else {
 151         lowmem = 0xb0000000;
 152     }
 153
 154     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 155      * min(qemu limit, user limit).
 156      */
 157     if (!pcms->max_ram_below_4g) {
 158         pcms->max_ram_below_4g = 4 * GiB;
 159     }
 160     if (lowmem > pcms->max_ram_below_4g) {
 161         lowmem = pcms->max_ram_below_4g;
 162         if (machine->ram_size - lowmem > lowmem &&
 163             lowmem & (1 * GiB - 1)) {
 164             warn_report("There is possibly poor performance as the ram size "
 165                         " (0x%" PRIx64 ") is more then twice the size of"
 166                         " max-ram-below-4g (%"PRIu64") and"
 167                         " max-ram-below-4g is not a multiple of 1G.",
 168                         (uint64_t)machine->ram_size, pcms->max_ram_below_4g);
 169         }
 170     }
 171
 172     if (machine->ram_size >= lowmem) {
 173         x86ms->above_4g_mem_size = machine->ram_size - lowmem;
 174         x86ms->below_4g_mem_size = lowmem;
 175     } else {
 176         x86ms->above_4g_mem_size = 0;
 177         x86ms->below_4g_mem_size = machine->ram_size;
 178     }
 179
 180     pc_machine_init_sgx_epc(pcms);
 181     x86_cpus_init(x86ms, pcmc->default_cpu_version);
 182
 183     kvmclock_create(pcmc->kvmclock_create_always);
 184
 185     /* pci enabled */
 186     if (pcmc->pci_enabled) {
 187         pci_memory = g_new(MemoryRegion, 1);
 188         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 189         rom_memory = pci_memory;
 190     } else {
 191         pci_memory = NULL;
 192         rom_memory = get_system_memory();
 193     }
 194
 195     pc_guest_info_init(pcms);
 196
 197     if (pcmc->smbios_defaults) {
 198         /* These values are guest ABI, do not change */
 199         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 200                             mc->name, pcmc->smbios_legacy_mode,
 201                             pcmc->smbios_uuid_encoded,
 202                             SMBIOS_ENTRY_POINT_21);
 203     }
 204
 205     /* allocate ram and load rom/bios */
 206     pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory);
 207
 208     /* create pci host bus */
 209     q35_host = Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE));
 210
 211     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host));
 212     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM,
 213                              OBJECT(ram_memory), NULL);
 214     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_PCI_MEM,
 215                              OBJECT(pci_memory), NULL);
 216     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_SYSTEM_MEM,
 217                              OBJECT(get_system_memory()), NULL);
 218     object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_IO_MEM,
 219                              OBJECT(system_io), NULL);
 220     object_property_set_int(OBJECT(q35_host), PCI_HOST_BELOW_4G_MEM_SIZE,
 221                             x86ms->below_4g_mem_size, NULL);
 222     object_property_set_int(OBJECT(q35_host), PCI_HOST_ABOVE_4G_MEM_SIZE,
 223                             x86ms->above_4g_mem_size, NULL);
 224     /* pci */
 225     sysbus_realize_and_unref(SYS_BUS_DEVICE(q35_host), &error_fatal);
 226     phb = PCI_HOST_BRIDGE(q35_host);
 227     host_bus = phb->bus;
 228     /* create ISA bus */
 229     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 230                                           ICH9_LPC_FUNC), true,
 231                                           TYPE_ICH9_LPC_DEVICE);
 232
 233     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 234                              TYPE_HOTPLUG_HANDLER,
 235                              (Object **)&x86ms->acpi_dev,
 236                              object_property_allow_set_link,
 237                              OBJ_PROP_LINK_STRONG);
 238     object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 239                              OBJECT(lpc), &error_abort);
 240
 241     acpi_pcihp = object_property_get_bool(OBJECT(lpc),
 242                                           ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
 243                                           NULL);
 244
 245     if (acpi_pcihp) {
 246         object_register_sugar_prop(TYPE_PCIE_SLOT, "native-hotplug",
 247                                    "false", true);
 248     }
 249
 250     /* irq lines */
 251     gsi_state = pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled);
 252
 253     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 254     lpc_dev = DEVICE(lpc);
 255     for (i = 0; i < GSI_NUM_PINS; i++) {
 256         qdev_connect_gpio_out_named(lpc_dev, ICH9_GPIO_GSI, i, x86ms->gsi[i]);
 257     }
 258     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 259                  ICH9_LPC_NB_PIRQS);
 260     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 261     isa_bus = ich9_lpc->isa_bus;
 262
 263     pc_i8259_create(isa_bus, gsi_state->i8259_irq);
 264
 265     if (pcmc->pci_enabled) {
 266         ioapic_init_gsi(gsi_state, "q35");
 267     }
 268
 269     if (tcg_enabled()) {
 270         x86_register_ferr_irq(x86ms->gsi[13]);
 271     }
 272
 273     assert(pcms->vmport != ON_OFF_AUTO__MAX);
 274     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 275         pcms->vmport = ON_OFF_AUTO_ON;
 276     }
 277
 278     /* init basic PC hardware */
 279     pc_basic_device_init(pcms, isa_bus, x86ms->gsi, &rtc_state, !mc->no_floppy,
 280                          0xff0104);
 281
 282     /* connect pm stuff to lpc */
 283     ich9_lpc_pm_init(lpc, x86_machine_is_smm_enabled(x86ms));
 284
 285     if (pcms->sata_enabled) {
 286         /* ahci and SATA device, for q35 1 ahci controller is built-in */
 287         ahci = pci_create_simple_multifunction(host_bus,
 288                                                PCI_DEVFN(ICH9_SATA1_DEV,
 289                                                          ICH9_SATA1_FUNC),
 290                                                true, "ich9-ahci");
 291         idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 292         idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 293         g_assert(MAX_SATA_PORTS == ahci_get_num_ports(ahci));
 294         ide_drive_get(hd, ahci_get_num_ports(ahci));
 295         ahci_ide_create_devs(ahci, hd);
 296     } else {
 297         idebus[0] = idebus[1] = NULL;
 298     }
 299
 300     if (machine_usb(machine)) {
 301         /* Should we create 6 UHCI according to ich9 spec? */
 302         ehci_create_ich9_with_companions(host_bus, 0x1d);
 303     }
 304
 305     if (pcms->smbus_enabled) {
 306         /* TODO: Populate SPD eeprom data.  */
 307         pcms->smbus = ich9_smb_init(host_bus,
 308                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 309                                     0xb100);
 310         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 311     }
 312
 313     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 314
 315     /* the rest devices to which pci devfn is automatically assigned */
 316     pc_vga_init(isa_bus, host_bus);
 317     pc_nic_init(pcmc, isa_bus, host_bus);
 318
 319     if (machine->nvdimms_state->is_enabled) {
 320         nvdimm_init_acpi_state(machine->nvdimms_state, system_io,
 321                                x86_nvdimm_acpi_dsmio,
 322                                x86ms->fw_cfg, OBJECT(pcms));
 323     }
 324 }
 325
 326 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 327     static void pc_init_##suffix(MachineState *machine) \
 328     { \
 329         void (*compat)(MachineState *m) = (compatfn); \
 330         if (compat) { \
 331             compat(machine); \
 332         } \
 333         pc_q35_init(machine); \
 334     } \
 335     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 336
 337
 338 static void pc_q35_machine_options(MachineClass *m)
 339 {
 340     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 341     pcmc->default_nic_model = "e1000e";
 342     pcmc->pci_root_uid = 0;
 343
 344     m->family = "pc_q35";
 345     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 346     m->units_per_default_bus = 1;
 347     m->default_machine_opts = "firmware=bios-256k.bin";
 348     m->default_display = "std";
 349     m->default_kernel_irqchip_split = false;
 350     m->no_floppy = 1;
 351     machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
 352     machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
 353     machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
 354     machine_class_allow_dynamic_sysbus_dev(m, TYPE_VMBUS_BRIDGE);
 355     m->max_cpus = 288;
 356 }
 357
 358 static void pc_q35_6_2_machine_options(MachineClass *m)
 359 {
 360     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 361     pc_q35_machine_options(m);
 362     m->alias = "q35";
 363     pcmc->default_cpu_version = 1;
 364 }
 365
 366 DEFINE_Q35_MACHINE(v6_2, "pc-q35-6.2", NULL,
 367                    pc_q35_6_2_machine_options);
 368
 369 static void pc_q35_6_1_machine_options(MachineClass *m)
 370 {
 371     pc_q35_6_2_machine_options(m);
 372     m->alias = NULL;
 373     compat_props_add(m->compat_props, hw_compat_6_1, hw_compat_6_1_len);
 374     compat_props_add(m->compat_props, pc_compat_6_1, pc_compat_6_1_len);
 375     m->smp_props.prefer_sockets = true;
 376 }
 377
 378 DEFINE_Q35_MACHINE(v6_1, "pc-q35-6.1", NULL,
 379                    pc_q35_6_1_machine_options);
 380
 381 static void pc_q35_6_0_machine_options(MachineClass *m)
 382 {
 383     pc_q35_6_1_machine_options(m);
 384     m->alias = NULL;
 385     compat_props_add(m->compat_props, hw_compat_6_0, hw_compat_6_0_len);
 386     compat_props_add(m->compat_props, pc_compat_6_0, pc_compat_6_0_len);
 387 }
 388
 389 DEFINE_Q35_MACHINE(v6_0, "pc-q35-6.0", NULL,
 390                    pc_q35_6_0_machine_options);
 391
 392 static void pc_q35_5_2_machine_options(MachineClass *m)
 393 {
 394     pc_q35_6_0_machine_options(m);
 395     m->alias = NULL;
 396     compat_props_add(m->compat_props, hw_compat_5_2, hw_compat_5_2_len);
 397     compat_props_add(m->compat_props, pc_compat_5_2, pc_compat_5_2_len);
 398 }
 399
 400 DEFINE_Q35_MACHINE(v5_2, "pc-q35-5.2", NULL,
 401                    pc_q35_5_2_machine_options);
 402
 403 static void pc_q35_5_1_machine_options(MachineClass *m)
 404 {
 405     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 406
 407     pc_q35_5_2_machine_options(m);
 408     m->alias = NULL;
 409     compat_props_add(m->compat_props, hw_compat_5_1, hw_compat_5_1_len);
 410     compat_props_add(m->compat_props, pc_compat_5_1, pc_compat_5_1_len);
 411     pcmc->kvmclock_create_always = false;
 412     pcmc->pci_root_uid = 1;
 413 }
 414
 415 DEFINE_Q35_MACHINE(v5_1, "pc-q35-5.1", NULL,
 416                    pc_q35_5_1_machine_options);
 417
 418 static void pc_q35_5_0_machine_options(MachineClass *m)
 419 {
 420     pc_q35_5_1_machine_options(m);
 421     m->alias = NULL;
 422     m->numa_mem_supported = true;
 423     compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len);
 424     compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len);
 425     m->auto_enable_numa_with_memdev = false;
 426 }
 427
 428 DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL,
 429                    pc_q35_5_0_machine_options);
 430
 431 static void pc_q35_4_2_machine_options(MachineClass *m)
 432 {
 433     pc_q35_5_0_machine_options(m);
 434     m->alias = NULL;
 435     compat_props_add(m->compat_props, hw_compat_4_2, hw_compat_4_2_len);
 436     compat_props_add(m->compat_props, pc_compat_4_2, pc_compat_4_2_len);
 437 }
 438
 439 DEFINE_Q35_MACHINE(v4_2, "pc-q35-4.2", NULL,
 440                    pc_q35_4_2_machine_options);
 441
 442 static void pc_q35_4_1_machine_options(MachineClass *m)
 443 {
 444     pc_q35_4_2_machine_options(m);
 445     m->alias = NULL;
 446     compat_props_add(m->compat_props, hw_compat_4_1, hw_compat_4_1_len);
 447     compat_props_add(m->compat_props, pc_compat_4_1, pc_compat_4_1_len);
 448 }
 449
 450 DEFINE_Q35_MACHINE(v4_1, "pc-q35-4.1", NULL,
 451                    pc_q35_4_1_machine_options);
 452
 453 static void pc_q35_4_0_1_machine_options(MachineClass *m)
 454 {
 455     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 456     pc_q35_4_1_machine_options(m);
 457     m->alias = NULL;
 458     pcmc->default_cpu_version = CPU_VERSION_LEGACY;
 459     /*
 460      * This is the default machine for the 4.0-stable branch. It is basically
 461      * a 4.0 that doesn't use split irqchip by default. It MUST hence apply the
 462      * 4.0 compat props.
 463      */
 464     compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
 465     compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
 466 }
 467
 468 DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
 469                    pc_q35_4_0_1_machine_options);
 470
 471 static void pc_q35_4_0_machine_options(MachineClass *m)
 472 {
 473     pc_q35_4_0_1_machine_options(m);
 474     m->default_kernel_irqchip_split = true;
 475     m->alias = NULL;
 476     /* Compat props are applied by the 4.0.1 machine */
 477 }
 478
 479 DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
 480                    pc_q35_4_0_machine_options);
 481
 482 static void pc_q35_3_1_machine_options(MachineClass *m)
 483 {
 484     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 485
 486     pc_q35_4_0_machine_options(m);
 487     m->default_kernel_irqchip_split = false;
 488     pcmc->do_not_add_smb_acpi = true;
 489     m->smbus_no_migration_support = true;
 490     m->alias = NULL;
 491     pcmc->pvh_enabled = false;
 492     compat_props_add(m->compat_props, hw_compat_3_1, hw_compat_3_1_len);
 493     compat_props_add(m->compat_props, pc_compat_3_1, pc_compat_3_1_len);
 494 }
 495
 496 DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
 497                    pc_q35_3_1_machine_options);
 498
 499 static void pc_q35_3_0_machine_options(MachineClass *m)
 500 {
 501     pc_q35_3_1_machine_options(m);
 502     compat_props_add(m->compat_props, hw_compat_3_0, hw_compat_3_0_len);
 503     compat_props_add(m->compat_props, pc_compat_3_0, pc_compat_3_0_len);
 504 }
 505
 506 DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
 507                     pc_q35_3_0_machine_options);
 508
 509 static void pc_q35_2_12_machine_options(MachineClass *m)
 510 {
 511     pc_q35_3_0_machine_options(m);
 512     compat_props_add(m->compat_props, hw_compat_2_12, hw_compat_2_12_len);
 513     compat_props_add(m->compat_props, pc_compat_2_12, pc_compat_2_12_len);
 514 }
 515
 516 DEFINE_Q35_MACHINE(v2_12, "pc-q35-2.12", NULL,
 517                    pc_q35_2_12_machine_options);
 518
 519 static void pc_q35_2_11_machine_options(MachineClass *m)
 520 {
 521     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 522
 523     pc_q35_2_12_machine_options(m);
 524     pcmc->default_nic_model = "e1000";
 525     compat_props_add(m->compat_props, hw_compat_2_11, hw_compat_2_11_len);
 526     compat_props_add(m->compat_props, pc_compat_2_11, pc_compat_2_11_len);
 527 }
 528
 529 DEFINE_Q35_MACHINE(v2_11, "pc-q35-2.11", NULL,
 530                    pc_q35_2_11_machine_options);
 531
 532 static void pc_q35_2_10_machine_options(MachineClass *m)
 533 {
 534     pc_q35_2_11_machine_options(m);
 535     compat_props_add(m->compat_props, hw_compat_2_10, hw_compat_2_10_len);
 536     compat_props_add(m->compat_props, pc_compat_2_10, pc_compat_2_10_len);
 537     m->auto_enable_numa_with_memhp = false;
 538 }
 539
 540 DEFINE_Q35_MACHINE(v2_10, "pc-q35-2.10", NULL,
 541                    pc_q35_2_10_machine_options);
 542
 543 static void pc_q35_2_9_machine_options(MachineClass *m)
 544 {
 545     pc_q35_2_10_machine_options(m);
 546     compat_props_add(m->compat_props, hw_compat_2_9, hw_compat_2_9_len);
 547     compat_props_add(m->compat_props, pc_compat_2_9, pc_compat_2_9_len);
 548 }
 549
 550 DEFINE_Q35_MACHINE(v2_9, "pc-q35-2.9", NULL,
 551                    pc_q35_2_9_machine_options);
 552
 553 static void pc_q35_2_8_machine_options(MachineClass *m)
 554 {
 555     pc_q35_2_9_machine_options(m);
 556     compat_props_add(m->compat_props, hw_compat_2_8, hw_compat_2_8_len);
 557     compat_props_add(m->compat_props, pc_compat_2_8, pc_compat_2_8_len);
 558 }
 559
 560 DEFINE_Q35_MACHINE(v2_8, "pc-q35-2.8", NULL,
 561                    pc_q35_2_8_machine_options);
 562
 563 static void pc_q35_2_7_machine_options(MachineClass *m)
 564 {
 565     pc_q35_2_8_machine_options(m);
 566     m->max_cpus = 255;
 567     compat_props_add(m->compat_props, hw_compat_2_7, hw_compat_2_7_len);
 568     compat_props_add(m->compat_props, pc_compat_2_7, pc_compat_2_7_len);
 569 }
 570
 571 DEFINE_Q35_MACHINE(v2_7, "pc-q35-2.7", NULL,
 572                    pc_q35_2_7_machine_options);
 573
 574 static void pc_q35_2_6_machine_options(MachineClass *m)
 575 {
 576     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 577
 578     pc_q35_2_7_machine_options(m);
 579     pcmc->legacy_cpu_hotplug = true;
 580     pcmc->linuxboot_dma_enabled = false;
 581     compat_props_add(m->compat_props, hw_compat_2_6, hw_compat_2_6_len);
 582     compat_props_add(m->compat_props, pc_compat_2_6, pc_compat_2_6_len);
 583 }
 584
 585 DEFINE_Q35_MACHINE(v2_6, "pc-q35-2.6", NULL,
 586                    pc_q35_2_6_machine_options);
 587
 588 static void pc_q35_2_5_machine_options(MachineClass *m)
 589 {
 590     X86MachineClass *x86mc = X86_MACHINE_CLASS(m);
 591
 592     pc_q35_2_6_machine_options(m);
 593     x86mc->save_tsc_khz = false;
 594     m->legacy_fw_cfg_order = 1;
 595     compat_props_add(m->compat_props, hw_compat_2_5, hw_compat_2_5_len);
 596     compat_props_add(m->compat_props, pc_compat_2_5, pc_compat_2_5_len);
 597 }
 598
 599 DEFINE_Q35_MACHINE(v2_5, "pc-q35-2.5", NULL,
 600                    pc_q35_2_5_machine_options);
 601
 602 static void pc_q35_2_4_machine_options(MachineClass *m)
 603 {
 604     PCMachineClass *pcmc = PC_MACHINE_CLASS(m);
 605
 606     pc_q35_2_5_machine_options(m);
 607     m->hw_version = "2.4.0";
 608     pcmc->broken_reserved_end = true;
 609     compat_props_add(m->compat_props, hw_compat_2_4, hw_compat_2_4_len);
 610     compat_props_add(m->compat_props, pc_compat_2_4, pc_compat_2_4_len);
 611 }
 612
 613 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 614                    pc_q35_2_4_machine_options);