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monitor/qmp: Update comment for commit 4eaca8de268
[qemu/armbru.git] / hw / arm / aspeed_soc.c
blob9ee81048326e9d761d7440132378b7184c88aba5
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_VIC] = 0x1E6C0000,
34 [ASPEED_SDMC] = 0x1E6E0000,
35 [ASPEED_SCU] = 0x1E6E2000,
36 [ASPEED_XDMA] = 0x1E6E7000,
37 [ASPEED_ADC] = 0x1E6E9000,
38 [ASPEED_SRAM] = 0x1E720000,
39 [ASPEED_GPIO] = 0x1E780000,
40 [ASPEED_RTC] = 0x1E781000,
41 [ASPEED_TIMER1] = 0x1E782000,
42 [ASPEED_WDT] = 0x1E785000,
43 [ASPEED_PWM] = 0x1E786000,
44 [ASPEED_LPC] = 0x1E789000,
45 [ASPEED_IBT] = 0x1E789140,
46 [ASPEED_I2C] = 0x1E78A000,
47 [ASPEED_ETH1] = 0x1E660000,
48 [ASPEED_ETH2] = 0x1E680000,
49 [ASPEED_UART1] = 0x1E783000,
50 [ASPEED_UART5] = 0x1E784000,
51 [ASPEED_VUART] = 0x1E787000,
52 [ASPEED_SDRAM] = 0x40000000,
53 };
54
55 static const hwaddr aspeed_soc_ast2500_memmap[] = {
56 [ASPEED_IOMEM] = 0x1E600000,
57 [ASPEED_FMC] = 0x1E620000,
58 [ASPEED_SPI1] = 0x1E630000,
59 [ASPEED_SPI2] = 0x1E631000,
60 [ASPEED_VIC] = 0x1E6C0000,
61 [ASPEED_SDMC] = 0x1E6E0000,
62 [ASPEED_SCU] = 0x1E6E2000,
63 [ASPEED_XDMA] = 0x1E6E7000,
64 [ASPEED_ADC] = 0x1E6E9000,
65 [ASPEED_SRAM] = 0x1E720000,
66 [ASPEED_GPIO] = 0x1E780000,
67 [ASPEED_RTC] = 0x1E781000,
68 [ASPEED_TIMER1] = 0x1E782000,
69 [ASPEED_WDT] = 0x1E785000,
70 [ASPEED_PWM] = 0x1E786000,
71 [ASPEED_LPC] = 0x1E789000,
72 [ASPEED_IBT] = 0x1E789140,
73 [ASPEED_I2C] = 0x1E78A000,
74 [ASPEED_ETH1] = 0x1E660000,
75 [ASPEED_ETH2] = 0x1E680000,
76 [ASPEED_UART1] = 0x1E783000,
77 [ASPEED_UART5] = 0x1E784000,
78 [ASPEED_VUART] = 0x1E787000,
79 [ASPEED_SDRAM] = 0x80000000,
80 };
81
82 static const int aspeed_soc_ast2400_irqmap[] = {
83 [ASPEED_UART1] = 9,
84 [ASPEED_UART2] = 32,
85 [ASPEED_UART3] = 33,
86 [ASPEED_UART4] = 34,
87 [ASPEED_UART5] = 10,
88 [ASPEED_VUART] = 8,
89 [ASPEED_FMC] = 19,
90 [ASPEED_SDMC] = 0,
91 [ASPEED_SCU] = 21,
92 [ASPEED_ADC] = 31,
93 [ASPEED_GPIO] = 20,
94 [ASPEED_RTC] = 22,
95 [ASPEED_TIMER1] = 16,
96 [ASPEED_TIMER2] = 17,
97 [ASPEED_TIMER3] = 18,
98 [ASPEED_TIMER4] = 35,
99 [ASPEED_TIMER5] = 36,
100 [ASPEED_TIMER6] = 37,
101 [ASPEED_TIMER7] = 38,
102 [ASPEED_TIMER8] = 39,
103 [ASPEED_WDT] = 27,
104 [ASPEED_PWM] = 28,
105 [ASPEED_LPC] = 8,
106 [ASPEED_IBT] = 8, /* LPC */
107 [ASPEED_I2C] = 12,
108 [ASPEED_ETH1] = 2,
109 [ASPEED_ETH2] = 3,
110 [ASPEED_XDMA] = 6,
111 };
112
113 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
114
115 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
116 static const char *aspeed_soc_ast2500_typenames[] = {
117 "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
118
119 static const AspeedSoCInfo aspeed_socs[] = {
120 {
121 .name = "ast2400-a0",
122 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
123 .silicon_rev = AST2400_A0_SILICON_REV,
124 .sram_size = 0x8000,
125 .spis_num = 1,
126 .fmc_typename = "aspeed.smc.fmc",
127 .spi_typename = aspeed_soc_ast2400_typenames,
128 .wdts_num = 2,
129 .irqmap = aspeed_soc_ast2400_irqmap,
130 .memmap = aspeed_soc_ast2400_memmap,
131 .num_cpus = 1,
132 }, {
133 .name = "ast2400-a1",
134 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
135 .silicon_rev = AST2400_A1_SILICON_REV,
136 .sram_size = 0x8000,
137 .spis_num = 1,
138 .fmc_typename = "aspeed.smc.fmc",
139 .spi_typename = aspeed_soc_ast2400_typenames,
140 .wdts_num = 2,
141 .irqmap = aspeed_soc_ast2400_irqmap,
142 .memmap = aspeed_soc_ast2400_memmap,
143 .num_cpus = 1,
144 }, {
145 .name = "ast2400",
146 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
147 .silicon_rev = AST2400_A0_SILICON_REV,
148 .sram_size = 0x8000,
149 .spis_num = 1,
150 .fmc_typename = "aspeed.smc.fmc",
151 .spi_typename = aspeed_soc_ast2400_typenames,
152 .wdts_num = 2,
153 .irqmap = aspeed_soc_ast2400_irqmap,
154 .memmap = aspeed_soc_ast2400_memmap,
155 .num_cpus = 1,
156 }, {
157 .name = "ast2500-a1",
158 .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
159 .silicon_rev = AST2500_A1_SILICON_REV,
160 .sram_size = 0x9000,
161 .spis_num = 2,
162 .fmc_typename = "aspeed.smc.ast2500-fmc",
163 .spi_typename = aspeed_soc_ast2500_typenames,
164 .wdts_num = 3,
165 .irqmap = aspeed_soc_ast2500_irqmap,
166 .memmap = aspeed_soc_ast2500_memmap,
167 .num_cpus = 1,
168 },
169 };
170
171 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
172 {
173 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
174
175 return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
176 }
177
178 static void aspeed_soc_init(Object *obj)
179 {
180 AspeedSoCState *s = ASPEED_SOC(obj);
181 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
182 int i;
183
184 for (i = 0; i < sc->info->num_cpus; i++) {
185 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
186 sizeof(s->cpu[i]), sc->info->cpu_type,
187 &error_abort, NULL);
188 }
189
190 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
191 TYPE_ASPEED_SCU);
192 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
193 sc->info->silicon_rev);
194 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
195 "hw-strap1", &error_abort);
196 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
197 "hw-strap2", &error_abort);
198 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
199 "hw-prot-key", &error_abort);
200
201 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
202 TYPE_ASPEED_VIC);
203
204 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
205 TYPE_ASPEED_RTC);
206
207 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
208 sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
209 object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
210 OBJECT(&s->scu), &error_abort);
211
212 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
213 TYPE_ASPEED_I2C);
214
215 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
216 sc->info->fmc_typename);
217 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
218 &error_abort);
219
220 for (i = 0; i < sc->info->spis_num; i++) {
221 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
222 sizeof(s->spi[i]), sc->info->spi_typename[i]);
223 }
224
225 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
226 TYPE_ASPEED_SDMC);
227 qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
228 sc->info->silicon_rev);
229 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
230 "ram-size", &error_abort);
231 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
232 "max-ram-size", &error_abort);
233
234 for (i = 0; i < sc->info->wdts_num; i++) {
235 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
236 sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
237 qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
238 sc->info->silicon_rev);
239 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
240 OBJECT(&s->scu), &error_abort);
241 }
242
243 for (i = 0; i < ASPEED_MACS_NUM; i++) {
244 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
245 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
246 }
247
248 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
249 TYPE_ASPEED_XDMA);
250 }
251
252 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
253 {
254 int i;
255 AspeedSoCState *s = ASPEED_SOC(dev);
256 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
257 Error *err = NULL, *local_err = NULL;
258
259 /* IO space */
260 create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
261 ASPEED_SOC_IOMEM_SIZE);
262
263 if (s->num_cpus > sc->info->num_cpus) {
264 warn_report("%s: invalid number of CPUs %d, using default %d",
265 sc->info->name, s->num_cpus, sc->info->num_cpus);
266 s->num_cpus = sc->info->num_cpus;
267 }
268
269 /* CPU */
270 for (i = 0; i < s->num_cpus; i++) {
271 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
272 if (err) {
273 error_propagate(errp, err);
274 return;
275 }
276 }
277
278 /* SRAM */
279 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
280 sc->info->sram_size, &err);
281 if (err) {
282 error_propagate(errp, err);
283 return;
284 }
285 memory_region_add_subregion(get_system_memory(),
286 sc->info->memmap[ASPEED_SRAM], &s->sram);
287
288 /* SCU */
289 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
290 if (err) {
291 error_propagate(errp, err);
292 return;
293 }
294 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
295
296 /* VIC */
297 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
298 if (err) {
299 error_propagate(errp, err);
300 return;
301 }
302 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
304 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
305 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
306 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
307
308 /* RTC */
309 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
310 if (err) {
311 error_propagate(errp, err);
312 return;
313 }
314 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
316 aspeed_soc_get_irq(s, ASPEED_RTC));
317
318 /* Timer */
319 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
320 if (err) {
321 error_propagate(errp, err);
322 return;
323 }
324 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
325 sc->info->memmap[ASPEED_TIMER1]);
326 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
327 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
328 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
329 }
330
331 /* UART - attach an 8250 to the IO space as our UART5 */
332 if (serial_hd(0)) {
333 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
334 serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
335 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
336 }
337
338 /* I2C */
339 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
340 if (err) {
341 error_propagate(errp, err);
342 return;
343 }
344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
345 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
346 aspeed_soc_get_irq(s, ASPEED_I2C));
347
348 /* FMC, The number of CS is set at the board level */
349 object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
350 "sdram-base", &err);
351 if (err) {
352 error_propagate(errp, err);
353 return;
354 }
355 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
356 if (err) {
357 error_propagate(errp, err);
358 return;
359 }
360 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
361 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
362 s->fmc.ctrl->flash_window_base);
363 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
364 aspeed_soc_get_irq(s, ASPEED_FMC));
365
366 /* SPI */
367 for (i = 0; i < sc->info->spis_num; i++) {
368 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
369 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
370 &local_err);
371 error_propagate(&err, local_err);
372 if (err) {
373 error_propagate(errp, err);
374 return;
375 }
376 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
377 sc->info->memmap[ASPEED_SPI1 + i]);
378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
379 s->spi[i].ctrl->flash_window_base);
380 }
381
382 /* SDMC - SDRAM Memory Controller */
383 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
384 if (err) {
385 error_propagate(errp, err);
386 return;
387 }
388 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
389
390 /* Watch dog */
391 for (i = 0; i < sc->info->wdts_num; i++) {
392 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
393 if (err) {
394 error_propagate(errp, err);
395 return;
396 }
397 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
398 sc->info->memmap[ASPEED_WDT] + i * 0x20);
399 }
400
401 /* Net */
402 for (i = 0; i < nb_nics; i++) {
403 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
404 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
405 &err);
406 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
407 &local_err);
408 error_propagate(&err, local_err);
409 if (err) {
410 error_propagate(errp, err);
411 return;
412 }
413 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
414 sc->info->memmap[ASPEED_ETH1 + i]);
415 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
416 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
417 }
418
419 /* XDMA */
420 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
421 if (err) {
422 error_propagate(errp, err);
423 return;
424 }
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
426 sc->info->memmap[ASPEED_XDMA]);
427 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
428 aspeed_soc_get_irq(s, ASPEED_XDMA));
429 }
430 static Property aspeed_soc_properties[] = {
431 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
432 DEFINE_PROP_END_OF_LIST(),
433 };
434
435 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
436 {
437 DeviceClass *dc = DEVICE_CLASS(oc);
438 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
439
440 sc->info = (AspeedSoCInfo *) data;
441 dc->realize = aspeed_soc_realize;
442 /* Reason: Uses serial_hds and nd_table in realize() directly */
443 dc->user_creatable = false;
444 dc->props = aspeed_soc_properties;
445 }
446
447 static const TypeInfo aspeed_soc_type_info = {
448 .name = TYPE_ASPEED_SOC,
449 .parent = TYPE_DEVICE,
450 .instance_init = aspeed_soc_init,
451 .instance_size = sizeof(AspeedSoCState),
452 .class_size = sizeof(AspeedSoCClass),
453 .abstract = true,
454 };
455
456 static void aspeed_soc_register_types(void)
457 {
458 int i;
459
460 type_register_static(&aspeed_soc_type_info);
461 for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
462 TypeInfo ti = {
463 .name = aspeed_socs[i].name,
464 .parent = TYPE_ASPEED_SOC,
465 .class_init = aspeed_soc_class_init,
466 .class_data = (void *) &aspeed_socs[i],
467 };
468 type_register(&ti);
469 }
470 }
471
472 type_init(aspeed_soc_register_types)
armbru's QEMU hackery