hw/arm/fsl-imx6.c

   1 /*
   2  * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX6 SOC emulation.
   5  *
   6  * Based on hw/arm/fsl-imx31.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "hw/arm/fsl-imx6.h"
  25 #include "hw/boards.h"
  26 #include "hw/qdev-properties.h"
  27 #include "sysemu/sysemu.h"
  28 #include "chardev/char.h"
  29 #include "qemu/error-report.h"
  30 #include "qemu/module.h"
  31
  32 #define IMX6_ESDHC_CAPABILITIES     0x057834b4
  33
  34 #define NAME_SIZE 20
  35
  36 static void fsl_imx6_init(Object *obj)
  37 {
  38     MachineState *ms = MACHINE(qdev_get_machine());
  39     FslIMX6State *s = FSL_IMX6(obj);
  40     char name[NAME_SIZE];
  41     int i;
  42
  43     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
  44         snprintf(name, NAME_SIZE, "cpu%d", i);
  45         object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
  46                                 "cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL);
  47     }
  48
  49     sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
  50                           TYPE_A9MPCORE_PRIV);
  51
  52     sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM);
  53
  54     sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
  55
  56     for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
  57         snprintf(name, NAME_SIZE, "uart%d", i + 1);
  58         sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
  59                               TYPE_IMX_SERIAL);
  60     }
  61
  62     sysbus_init_child_obj(obj, "gpt", &s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
  63
  64     for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
  65         snprintf(name, NAME_SIZE, "epit%d", i + 1);
  66         sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
  67                               TYPE_IMX_EPIT);
  68     }
  69
  70     for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
  71         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
  72         sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
  73                               TYPE_IMX_I2C);
  74     }
  75
  76     for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
  77         snprintf(name, NAME_SIZE, "gpio%d", i + 1);
  78         sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
  79                               TYPE_IMX_GPIO);
  80     }
  81
  82     for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
  83         snprintf(name, NAME_SIZE, "sdhc%d", i + 1);
  84         sysbus_init_child_obj(obj, name, &s->esdhc[i], sizeof(s->esdhc[i]),
  85                               TYPE_IMX_USDHC);
  86     }
  87
  88     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
  89         snprintf(name, NAME_SIZE, "spi%d", i + 1);
  90         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
  91                               TYPE_IMX_SPI);
  92     }
  93
  94     sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET);
  95 }
  96
  97 static void fsl_imx6_realize(DeviceState *dev, Error **errp)
  98 {
  99     MachineState *ms = MACHINE(qdev_get_machine());
 100     FslIMX6State *s = FSL_IMX6(dev);
 101     uint16_t i;
 102     Error *err = NULL;
 103     unsigned int smp_cpus = ms->smp.cpus;
 104
 105     if (smp_cpus > FSL_IMX6_NUM_CPUS) {
 106         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
 107                    TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
 108         return;
 109     }
 110
 111     for (i = 0; i < smp_cpus; i++) {
 112
 113         /* On uniprocessor, the CBAR is set to 0 */
 114         if (smp_cpus > 1) {
 115             object_property_set_int(OBJECT(&s->cpu[i]), FSL_IMX6_A9MPCORE_ADDR,
 116                                     "reset-cbar", &error_abort);
 117         }
 118
 119         /* All CPU but CPU 0 start in power off mode */
 120         if (i) {
 121             object_property_set_bool(OBJECT(&s->cpu[i]), true,
 122                                      "start-powered-off", &error_abort);
 123         }
 124
 125         object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
 126         if (err) {
 127             error_propagate(errp, err);
 128             return;
 129         }
 130     }
 131
 132     object_property_set_int(OBJECT(&s->a9mpcore), smp_cpus, "num-cpu",
 133                             &error_abort);
 134
 135     object_property_set_int(OBJECT(&s->a9mpcore),
 136                             FSL_IMX6_MAX_IRQ + GIC_INTERNAL, "num-irq",
 137                             &error_abort);
 138
 139     object_property_set_bool(OBJECT(&s->a9mpcore), true, "realized", &err);
 140     if (err) {
 141         error_propagate(errp, err);
 142         return;
 143     }
 144     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
 145
 146     for (i = 0; i < smp_cpus; i++) {
 147         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
 148                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
 149         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
 150                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
 151     }
 152
 153     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
 154     if (err) {
 155         error_propagate(errp, err);
 156         return;
 157     }
 158     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6_CCM_ADDR);
 159
 160     object_property_set_bool(OBJECT(&s->src), true, "realized", &err);
 161     if (err) {
 162         error_propagate(errp, err);
 163         return;
 164     }
 165     sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6_SRC_ADDR);
 166
 167     /* Initialize all UARTs */
 168     for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) {
 169         static const struct {
 170             hwaddr addr;
 171             unsigned int irq;
 172         } serial_table[FSL_IMX6_NUM_UARTS] = {
 173             { FSL_IMX6_UART1_ADDR, FSL_IMX6_UART1_IRQ },
 174             { FSL_IMX6_UART2_ADDR, FSL_IMX6_UART2_IRQ },
 175             { FSL_IMX6_UART3_ADDR, FSL_IMX6_UART3_IRQ },
 176             { FSL_IMX6_UART4_ADDR, FSL_IMX6_UART4_IRQ },
 177             { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ },
 178         };
 179
 180         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 181
 182         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 183         if (err) {
 184             error_propagate(errp, err);
 185             return;
 186         }
 187
 188         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 189         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 190                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 191                                             serial_table[i].irq));
 192     }
 193
 194     s->gpt.ccm = IMX_CCM(&s->ccm);
 195
 196     object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
 197     if (err) {
 198         error_propagate(errp, err);
 199         return;
 200     }
 201
 202     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
 203     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
 204                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 205                                         FSL_IMX6_GPT_IRQ));
 206
 207     /* Initialize all EPIT timers */
 208     for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
 209         static const struct {
 210             hwaddr addr;
 211             unsigned int irq;
 212         } epit_table[FSL_IMX6_NUM_EPITS] = {
 213             { FSL_IMX6_EPIT1_ADDR, FSL_IMX6_EPIT1_IRQ },
 214             { FSL_IMX6_EPIT2_ADDR, FSL_IMX6_EPIT2_IRQ },
 215         };
 216
 217         s->epit[i].ccm = IMX_CCM(&s->ccm);
 218
 219         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
 220         if (err) {
 221             error_propagate(errp, err);
 222             return;
 223         }
 224
 225         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 226         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 227                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 228                                             epit_table[i].irq));
 229     }
 230
 231     /* Initialize all I2C */
 232     for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) {
 233         static const struct {
 234             hwaddr addr;
 235             unsigned int irq;
 236         } i2c_table[FSL_IMX6_NUM_I2CS] = {
 237             { FSL_IMX6_I2C1_ADDR, FSL_IMX6_I2C1_IRQ },
 238             { FSL_IMX6_I2C2_ADDR, FSL_IMX6_I2C2_IRQ },
 239             { FSL_IMX6_I2C3_ADDR, FSL_IMX6_I2C3_IRQ }
 240         };
 241
 242         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
 243         if (err) {
 244             error_propagate(errp, err);
 245             return;
 246         }
 247
 248         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 249         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 250                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 251                                             i2c_table[i].irq));
 252     }
 253
 254     /* Initialize all GPIOs */
 255     for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) {
 256         static const struct {
 257             hwaddr addr;
 258             unsigned int irq_low;
 259             unsigned int irq_high;
 260         } gpio_table[FSL_IMX6_NUM_GPIOS] = {
 261             {
 262                 FSL_IMX6_GPIO1_ADDR,
 263                 FSL_IMX6_GPIO1_LOW_IRQ,
 264                 FSL_IMX6_GPIO1_HIGH_IRQ
 265             },
 266             {
 267                 FSL_IMX6_GPIO2_ADDR,
 268                 FSL_IMX6_GPIO2_LOW_IRQ,
 269                 FSL_IMX6_GPIO2_HIGH_IRQ
 270             },
 271             {
 272                 FSL_IMX6_GPIO3_ADDR,
 273                 FSL_IMX6_GPIO3_LOW_IRQ,
 274                 FSL_IMX6_GPIO3_HIGH_IRQ
 275             },
 276             {
 277                 FSL_IMX6_GPIO4_ADDR,
 278                 FSL_IMX6_GPIO4_LOW_IRQ,
 279                 FSL_IMX6_GPIO4_HIGH_IRQ
 280             },
 281             {
 282                 FSL_IMX6_GPIO5_ADDR,
 283                 FSL_IMX6_GPIO5_LOW_IRQ,
 284                 FSL_IMX6_GPIO5_HIGH_IRQ
 285             },
 286             {
 287                 FSL_IMX6_GPIO6_ADDR,
 288                 FSL_IMX6_GPIO6_LOW_IRQ,
 289                 FSL_IMX6_GPIO6_HIGH_IRQ
 290             },
 291             {
 292                 FSL_IMX6_GPIO7_ADDR,
 293                 FSL_IMX6_GPIO7_LOW_IRQ,
 294                 FSL_IMX6_GPIO7_HIGH_IRQ
 295             },
 296         };
 297
 298         object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-edge-sel",
 299                                  &error_abort);
 300         object_property_set_bool(OBJECT(&s->gpio[i]), true, "has-upper-pin-irq",
 301                                  &error_abort);
 302         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
 303         if (err) {
 304             error_propagate(errp, err);
 305             return;
 306         }
 307
 308         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 309         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 310                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 311                                             gpio_table[i].irq_low));
 312         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
 313                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 314                                             gpio_table[i].irq_high));
 315     }
 316
 317     /* Initialize all SDHC */
 318     for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) {
 319         static const struct {
 320             hwaddr addr;
 321             unsigned int irq;
 322         } esdhc_table[FSL_IMX6_NUM_ESDHCS] = {
 323             { FSL_IMX6_uSDHC1_ADDR, FSL_IMX6_uSDHC1_IRQ },
 324             { FSL_IMX6_uSDHC2_ADDR, FSL_IMX6_uSDHC2_IRQ },
 325             { FSL_IMX6_uSDHC3_ADDR, FSL_IMX6_uSDHC3_IRQ },
 326             { FSL_IMX6_uSDHC4_ADDR, FSL_IMX6_uSDHC4_IRQ },
 327         };
 328
 329         /* UHS-I SDIO3.0 SDR104 1.8V ADMA */
 330         object_property_set_uint(OBJECT(&s->esdhc[i]), 3, "sd-spec-version",
 331                                  &err);
 332         object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
 333                                  "capareg", &err);
 334         object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &err);
 335         if (err) {
 336             error_propagate(errp, err);
 337             return;
 338         }
 339         sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
 340         sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
 341                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 342                                             esdhc_table[i].irq));
 343     }
 344
 345     /* Initialize all ECSPI */
 346     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
 347         static const struct {
 348             hwaddr addr;
 349             unsigned int irq;
 350         } spi_table[FSL_IMX6_NUM_ECSPIS] = {
 351             { FSL_IMX6_eCSPI1_ADDR, FSL_IMX6_ECSPI1_IRQ },
 352             { FSL_IMX6_eCSPI2_ADDR, FSL_IMX6_ECSPI2_IRQ },
 353             { FSL_IMX6_eCSPI3_ADDR, FSL_IMX6_ECSPI3_IRQ },
 354             { FSL_IMX6_eCSPI4_ADDR, FSL_IMX6_ECSPI4_IRQ },
 355             { FSL_IMX6_eCSPI5_ADDR, FSL_IMX6_ECSPI5_IRQ },
 356         };
 357
 358         /* Initialize the SPI */
 359         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 360         if (err) {
 361             error_propagate(errp, err);
 362             return;
 363         }
 364
 365         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
 366         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 367                            qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 368                                             spi_table[i].irq));
 369     }
 370
 371     qdev_set_nic_properties(DEVICE(&s->eth), &nd_table[0]);
 372     object_property_set_bool(OBJECT(&s->eth), true, "realized", &err);
 373     if (err) {
 374         error_propagate(errp, err);
 375         return;
 376     }
 377     sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
 378     sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
 379                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 380                                         FSL_IMX6_ENET_MAC_IRQ));
 381     sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
 382                        qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 383                                         FSL_IMX6_ENET_MAC_1588_IRQ));
 384
 385     /* ROM memory */
 386     memory_region_init_rom(&s->rom, NULL, "imx6.rom",
 387                            FSL_IMX6_ROM_SIZE, &err);
 388     if (err) {
 389         error_propagate(errp, err);
 390         return;
 391     }
 392     memory_region_add_subregion(get_system_memory(), FSL_IMX6_ROM_ADDR,
 393                                 &s->rom);
 394
 395     /* CAAM memory */
 396     memory_region_init_rom(&s->caam, NULL, "imx6.caam",
 397                            FSL_IMX6_CAAM_MEM_SIZE, &err);
 398     if (err) {
 399         error_propagate(errp, err);
 400         return;
 401     }
 402     memory_region_add_subregion(get_system_memory(), FSL_IMX6_CAAM_MEM_ADDR,
 403                                 &s->caam);
 404
 405     /* OCRAM memory */
 406     memory_region_init_ram(&s->ocram, NULL, "imx6.ocram", FSL_IMX6_OCRAM_SIZE,
 407                            &err);
 408     if (err) {
 409         error_propagate(errp, err);
 410         return;
 411     }
 412     memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ADDR,
 413                                 &s->ocram);
 414
 415     /* internal OCRAM (256 KB) is aliased over 1 MB */
 416     memory_region_init_alias(&s->ocram_alias, NULL, "imx6.ocram_alias",
 417                              &s->ocram, 0, FSL_IMX6_OCRAM_ALIAS_SIZE);
 418     memory_region_add_subregion(get_system_memory(), FSL_IMX6_OCRAM_ALIAS_ADDR,
 419                                 &s->ocram_alias);
 420 }
 421
 422 static void fsl_imx6_class_init(ObjectClass *oc, void *data)
 423 {
 424     DeviceClass *dc = DEVICE_CLASS(oc);
 425
 426     dc->realize = fsl_imx6_realize;
 427     dc->desc = "i.MX6 SOC";
 428     /* Reason: Uses serial_hd() in the realize() function */
 429     dc->user_creatable = false;
 430 }
 431
 432 static const TypeInfo fsl_imx6_type_info = {
 433     .name = TYPE_FSL_IMX6,
 434     .parent = TYPE_DEVICE,
 435     .instance_size = sizeof(FslIMX6State),
 436     .instance_init = fsl_imx6_init,
 437     .class_init = fsl_imx6_class_init,
 438 };
 439
 440 static void fsl_imx6_register_types(void)
 441 {
 442     type_register_static(&fsl_imx6_type_info);
 443 }
 444
 445 type_init(fsl_imx6_register_types)