2 * QEMU model for the AXIS devboard 88.
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
29 #include "hw/sysbus.h"
31 #include "hw/block/flash.h"
32 #include "hw/boards.h"
33 #include "hw/cris/etraxfs.h"
34 #include "hw/loader.h"
37 #include "exec/address-spaces.h"
38 #include "sysemu/qtest.h"
39 #include "sysemu/sysemu.h"
54 static struct nand_state_t nand_state
;
55 static uint64_t nand_read(void *opaque
, hwaddr addr
, unsigned size
)
57 struct nand_state_t
*s
= opaque
;
61 r
= nand_getio(s
->nand
);
62 nand_getpins(s
->nand
, &rdy
);
65 DNAND(printf("%s addr=%x r=%x\n", __func__
, addr
, r
));
70 nand_write(void *opaque
, hwaddr addr
, uint64_t value
,
73 struct nand_state_t
*s
= opaque
;
76 DNAND(printf("%s addr=%x v=%x\n", __func__
, addr
, (unsigned)value
));
77 nand_setpins(s
->nand
, s
->cle
, s
->ale
, s
->ce
, 1, 0);
78 nand_setio(s
->nand
, value
);
79 nand_getpins(s
->nand
, &rdy
);
83 static const MemoryRegionOps nand_ops
= {
86 .endianness
= DEVICE_NATIVE_ENDIAN
,
91 unsigned int shiftreg
;
100 static void tempsensor_clkedge(struct tempsensor_t
*s
,
101 unsigned int clk
, unsigned int data_in
)
103 D(printf("%s clk=%d state=%d sr=%x\n", __func__
,
104 clk
, s
->state
, s
->shiftreg
));
111 /* Output reg is clocked at negedge. */
133 /* Indata is sampled at posedge. */
137 s
->shiftreg
|= data_in
& 1;
139 D(printf("%s cfgreg=%x\n", __func__
, s
->shiftreg
));
140 s
->regs
[0] = s
->shiftreg
;
144 if ((s
->regs
[0] & 0xff) == 0) {
145 /* 25 degrees celsius. */
146 s
->shiftreg
= 0x0b9f;
147 } else if ((s
->regs
[0] & 0xff) == 0xff) {
148 /* Sensor ID, 0x8100 LM70. */
149 s
->shiftreg
= 0x8100;
151 printf("Invalid tempsens state %x\n", s
->regs
[0]);
159 #define RW_PA_DOUT 0x00
160 #define R_PA_DIN 0x01
161 #define RW_PA_OE 0x02
162 #define RW_PD_DOUT 0x10
163 #define R_PD_DIN 0x11
164 #define RW_PD_OE 0x12
166 static struct gpio_state_t
169 struct nand_state_t
*nand
;
170 struct tempsensor_t tempsensor
;
171 uint32_t regs
[0x5c / 4];
174 static uint64_t gpio_read(void *opaque
, hwaddr addr
, unsigned size
)
176 struct gpio_state_t
*s
= opaque
;
183 r
= s
->regs
[RW_PA_DOUT
] & s
->regs
[RW_PA_OE
];
185 /* Encode pins from the nand. */
186 r
|= s
->nand
->rdy
<< 7;
189 r
= s
->regs
[RW_PD_DOUT
] & s
->regs
[RW_PD_OE
];
191 /* Encode temp sensor pins. */
192 r
|= (!!(s
->tempsensor
.shiftreg
& 0x10000)) << 4;
200 D(printf("%s %x=%x\n", __func__
, addr
, r
));
203 static void gpio_write(void *opaque
, hwaddr addr
, uint64_t value
,
206 struct gpio_state_t
*s
= opaque
;
207 D(printf("%s %x=%x\n", __func__
, addr
, (unsigned)value
));
213 /* Decode nand pins. */
214 s
->nand
->ale
= !!(value
& (1 << 6));
215 s
->nand
->cle
= !!(value
& (1 << 5));
216 s
->nand
->ce
= !!(value
& (1 << 4));
218 s
->regs
[addr
] = value
;
222 /* Temp sensor clk. */
223 if ((s
->regs
[addr
] ^ value
) & 2)
224 tempsensor_clkedge(&s
->tempsensor
, !!(value
& 2),
226 s
->regs
[addr
] = value
;
230 s
->regs
[addr
] = value
;
235 static const MemoryRegionOps gpio_ops
= {
238 .endianness
= DEVICE_NATIVE_ENDIAN
,
240 .min_access_size
= 4,
241 .max_access_size
= 4,
245 #define INTMEM_SIZE (128 * KiB)
247 static struct cris_load_info li
;
250 void axisdev88_init(MachineState
*machine
)
252 ram_addr_t ram_size
= machine
->ram_size
;
253 const char *kernel_filename
= machine
->kernel_filename
;
254 const char *kernel_cmdline
= machine
->kernel_cmdline
;
260 qemu_irq irq
[30], nmi
[2];
262 struct etraxfs_dma_client
*dma_eth
;
264 MemoryRegion
*address_space_mem
= get_system_memory();
265 MemoryRegion
*phys_ram
= g_new(MemoryRegion
, 1);
266 MemoryRegion
*phys_intmem
= g_new(MemoryRegion
, 1);
269 cpu
= CRIS_CPU(cpu_create(machine
->cpu_type
));
273 memory_region_allocate_system_memory(phys_ram
, NULL
, "axisdev88.ram",
275 memory_region_add_subregion(address_space_mem
, 0x40000000, phys_ram
);
277 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
279 memory_region_init_ram(phys_intmem
, NULL
, "axisdev88.chipram",
280 INTMEM_SIZE
, &error_fatal
);
281 memory_region_add_subregion(address_space_mem
, 0x38000000, phys_intmem
);
283 /* Attach a NAND flash to CS1. */
284 nand
= drive_get(IF_MTD
, 0, 0);
285 nand_state
.nand
= nand_init(nand
? blk_by_legacy_dinfo(nand
) : NULL
,
286 NAND_MFR_STMICRO
, 0x39);
287 memory_region_init_io(&nand_state
.iomem
, NULL
, &nand_ops
, &nand_state
,
289 memory_region_add_subregion(address_space_mem
, 0x10000000,
292 gpio_state
.nand
= &nand_state
;
293 memory_region_init_io(&gpio_state
.iomem
, NULL
, &gpio_ops
, &gpio_state
,
295 memory_region_add_subregion(address_space_mem
, 0x3001a000,
299 dev
= qdev_create(NULL
, "etraxfs,pic");
300 /* FIXME: Is there a proper way to signal vectors to the CPU core? */
301 qdev_prop_set_ptr(dev
, "interrupt_vector", &env
->interrupt_vector
);
302 qdev_init_nofail(dev
);
303 s
= SYS_BUS_DEVICE(dev
);
304 sysbus_mmio_map(s
, 0, 0x3001c000);
305 sysbus_connect_irq(s
, 0, qdev_get_gpio_in(DEVICE(cpu
), CRIS_CPU_IRQ
));
306 sysbus_connect_irq(s
, 1, qdev_get_gpio_in(DEVICE(cpu
), CRIS_CPU_NMI
));
307 for (i
= 0; i
< 30; i
++) {
308 irq
[i
] = qdev_get_gpio_in(dev
, i
);
310 nmi
[0] = qdev_get_gpio_in(dev
, 30);
311 nmi
[1] = qdev_get_gpio_in(dev
, 31);
313 etraxfs_dmac
= etraxfs_dmac_init(0x30000000, 10);
314 for (i
= 0; i
< 10; i
++) {
315 /* On ETRAX, odd numbered channels are inputs. */
316 etraxfs_dmac_connect(etraxfs_dmac
, i
, irq
+ 7 + i
, i
& 1);
319 /* Add the two ethernet blocks. */
320 dma_eth
= g_malloc0(sizeof dma_eth
[0] * 4); /* Allocate 4 channels. */
321 etraxfs_eth_init(&nd_table
[0], 0x30034000, 1, &dma_eth
[0], &dma_eth
[1]);
323 etraxfs_eth_init(&nd_table
[1], 0x30036000, 2, &dma_eth
[2], &dma_eth
[3]);
326 /* The DMA Connector block is missing, hardwire things for now. */
327 etraxfs_dmac_connect_client(etraxfs_dmac
, 0, &dma_eth
[0]);
328 etraxfs_dmac_connect_client(etraxfs_dmac
, 1, &dma_eth
[1]);
330 etraxfs_dmac_connect_client(etraxfs_dmac
, 6, &dma_eth
[2]);
331 etraxfs_dmac_connect_client(etraxfs_dmac
, 7, &dma_eth
[3]);
335 sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq
[0x1b], nmi
[1], NULL
);
336 sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq
[0x1b], nmi
[1], NULL
);
338 for (i
= 0; i
< 4; i
++) {
339 etraxfs_ser_create(0x30026000 + i
* 0x2000, irq
[0x14 + i
], serial_hd(i
));
342 if (kernel_filename
) {
343 li
.image_filename
= kernel_filename
;
344 li
.cmdline
= kernel_cmdline
;
345 cris_load_image(cpu
, &li
);
346 } else if (!qtest_enabled()) {
347 fprintf(stderr
, "Kernel image must be specified\n");
352 static void axisdev88_machine_init(MachineClass
*mc
)
354 mc
->desc
= "AXIS devboard 88";
355 mc
->init
= axisdev88_init
;
357 mc
->default_cpu_type
= CRIS_CPU_TYPE_NAME("crisv32");
360 DEFINE_MACHINE("axis-dev88", axisdev88_machine_init
)