hw/timer/puv3_ost.c

   1 /*
   2  * OSTimer device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/sysbus.h"
  14 #include "hw/irq.h"
  15 #include "hw/ptimer.h"
  16 #include "qemu/main-loop.h"
  17 #include "qemu/module.h"
  18
  19 #undef DEBUG_PUV3
  20 #include "hw/unicore32/puv3.h"
  21
  22 #define TYPE_PUV3_OST "puv3_ost"
  23 #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
  24
  25 /* puv3 ostimer implementation. */
  26 typedef struct PUV3OSTState {
  27     SysBusDevice parent_obj;
  28
  29     MemoryRegion iomem;
  30     QEMUBH *bh;
  31     qemu_irq irq;
  32     ptimer_state *ptimer;
  33
  34     uint32_t reg_OSMR0;
  35     uint32_t reg_OSCR;
  36     uint32_t reg_OSSR;
  37     uint32_t reg_OIER;
  38 } PUV3OSTState;
  39
  40 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  41         unsigned size)
  42 {
  43     PUV3OSTState *s = opaque;
  44     uint32_t ret = 0;
  45
  46     switch (offset) {
  47     case 0x10: /* Counter Register */
  48         ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  49         break;
  50     case 0x14: /* Status Register */
  51         ret = s->reg_OSSR;
  52         break;
  53     case 0x1c: /* Interrupt Enable Register */
  54         ret = s->reg_OIER;
  55         break;
  56     default:
  57         DPRINTF("Bad offset %x\n", (int)offset);
  58     }
  59     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  60     return ret;
  61 }
  62
  63 static void puv3_ost_write(void *opaque, hwaddr offset,
  64         uint64_t value, unsigned size)
  65 {
  66     PUV3OSTState *s = opaque;
  67
  68     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  69     switch (offset) {
  70     case 0x00: /* Match Register 0 */
  71         s->reg_OSMR0 = value;
  72         if (s->reg_OSMR0 > s->reg_OSCR) {
  73             ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  74         } else {
  75             ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  76                     (0xffffffff - s->reg_OSCR));
  77         }
  78         ptimer_run(s->ptimer, 2);
  79         break;
  80     case 0x14: /* Status Register */
  81         assert(value == 0);
  82         if (s->reg_OSSR) {
  83             s->reg_OSSR = value;
  84             qemu_irq_lower(s->irq);
  85         }
  86         break;
  87     case 0x1c: /* Interrupt Enable Register */
  88         s->reg_OIER = value;
  89         break;
  90     default:
  91         DPRINTF("Bad offset %x\n", (int)offset);
  92     }
  93 }
  94
  95 static const MemoryRegionOps puv3_ost_ops = {
  96     .read = puv3_ost_read,
  97     .write = puv3_ost_write,
  98     .impl = {
  99         .min_access_size = 4,
 100         .max_access_size = 4,
 101     },
 102     .endianness = DEVICE_NATIVE_ENDIAN,
 103 };
 104
 105 static void puv3_ost_tick(void *opaque)
 106 {
 107     PUV3OSTState *s = opaque;
 108
 109     DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 110             s->reg_OSCR, s->reg_OSMR0);
 111
 112     s->reg_OSCR = s->reg_OSMR0;
 113     if (s->reg_OIER) {
 114         s->reg_OSSR = 1;
 115         qemu_irq_raise(s->irq);
 116     }
 117 }
 118
 119 static void puv3_ost_realize(DeviceState *dev, Error **errp)
 120 {
 121     PUV3OSTState *s = PUV3_OST(dev);
 122     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 123
 124     s->reg_OIER = 0;
 125     s->reg_OSSR = 0;
 126     s->reg_OSMR0 = 0;
 127     s->reg_OSCR = 0;
 128
 129     sysbus_init_irq(sbd, &s->irq);
 130
 131     s->bh = qemu_bh_new(puv3_ost_tick, s);
 132     s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
 133     ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 134
 135     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 136             PUV3_REGS_OFFSET);
 137     sysbus_init_mmio(sbd, &s->iomem);
 138 }
 139
 140 static void puv3_ost_class_init(ObjectClass *klass, void *data)
 141 {
 142     DeviceClass *dc = DEVICE_CLASS(klass);
 143
 144     dc->realize = puv3_ost_realize;
 145 }
 146
 147 static const TypeInfo puv3_ost_info = {
 148     .name = TYPE_PUV3_OST,
 149     .parent = TYPE_SYS_BUS_DEVICE,
 150     .instance_size = sizeof(PUV3OSTState),
 151     .class_init = puv3_ost_class_init,
 152 };
 153
 154 static void puv3_ost_register_type(void)
 155 {
 156     type_register_static(&puv3_ost_info);
 157 }
 158
 159 type_init(puv3_ost_register_type)