include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/intc/aspeed_vic.h"
  16 #include "hw/misc/aspeed_scu.h"
  17 #include "hw/misc/aspeed_sdmc.h"
  18 #include "hw/misc/aspeed_xdma.h"
  19 #include "hw/timer/aspeed_timer.h"
  20 #include "hw/timer/aspeed_rtc.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22 #include "hw/ssi/aspeed_smc.h"
  23 #include "hw/watchdog/wdt_aspeed.h"
  24 #include "hw/net/ftgmac100.h"
  25 #include "target/arm/cpu.h"
  26
  27 #define ASPEED_SPIS_NUM  2
  28 #define ASPEED_WDTS_NUM  3
  29 #define ASPEED_CPUS_NUM  2
  30 #define ASPEED_MACS_NUM  2
  31
  32 typedef struct AspeedSoCState {
  33     /*< private >*/
  34     DeviceState parent;
  35
  36     /*< public >*/
  37     ARMCPU cpu[ASPEED_CPUS_NUM];
  38     uint32_t num_cpus;
  39     MemoryRegion sram;
  40     AspeedVICState vic;
  41     AspeedRtcState rtc;
  42     AspeedTimerCtrlState timerctrl;
  43     AspeedI2CState i2c;
  44     AspeedSCUState scu;
  45     AspeedXDMAState xdma;
  46     AspeedSMCState fmc;
  47     AspeedSMCState spi[ASPEED_SPIS_NUM];
  48     AspeedSDMCState sdmc;
  49     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  50     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  51 } AspeedSoCState;
  52
  53 #define TYPE_ASPEED_SOC "aspeed-soc"
  54 #define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
  55
  56 typedef struct AspeedSoCInfo {
  57     const char *name;
  58     const char *cpu_type;
  59     uint32_t silicon_rev;
  60     uint64_t sram_size;
  61     int spis_num;
  62     const char *fmc_typename;
  63     const char **spi_typename;
  64     int wdts_num;
  65     const int *irqmap;
  66     const hwaddr *memmap;
  67     uint32_t num_cpus;
  68 } AspeedSoCInfo;
  69
  70 typedef struct AspeedSoCClass {
  71     DeviceClass parent_class;
  72     AspeedSoCInfo *info;
  73 } AspeedSoCClass;
  74
  75 #define ASPEED_SOC_CLASS(klass)                                         \
  76     OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
  77 #define ASPEED_SOC_GET_CLASS(obj)                               \
  78     OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
  79
  80 enum {
  81     ASPEED_IOMEM,
  82     ASPEED_UART1,
  83     ASPEED_UART2,
  84     ASPEED_UART3,
  85     ASPEED_UART4,
  86     ASPEED_UART5,
  87     ASPEED_VUART,
  88     ASPEED_FMC,
  89     ASPEED_SPI1,
  90     ASPEED_SPI2,
  91     ASPEED_VIC,
  92     ASPEED_SDMC,
  93     ASPEED_SCU,
  94     ASPEED_ADC,
  95     ASPEED_SRAM,
  96     ASPEED_GPIO,
  97     ASPEED_RTC,
  98     ASPEED_TIMER1,
  99     ASPEED_TIMER2,
 100     ASPEED_TIMER3,
 101     ASPEED_TIMER4,
 102     ASPEED_TIMER5,
 103     ASPEED_TIMER6,
 104     ASPEED_TIMER7,
 105     ASPEED_TIMER8,
 106     ASPEED_WDT,
 107     ASPEED_PWM,
 108     ASPEED_LPC,
 109     ASPEED_IBT,
 110     ASPEED_I2C,
 111     ASPEED_ETH1,
 112     ASPEED_ETH2,
 113     ASPEED_SDRAM,
 114     ASPEED_XDMA,
 115 };
 116
 117 #endif /* ASPEED_SOC_H */