include/hw/arm/virt.h

   1 /*
   2  *
   3  * Copyright (c) 2015 Linaro Limited
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2 or later, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * Emulate a virtual board which works by passing Linux all the information
  18  * it needs about what devices are present via the device tree.
  19  * There are some restrictions about what we can do here:
  20  *  + we can only present devices whose Linux drivers will work based
  21  *    purely on the device tree with no platform data at all
  22  *  + we want to present a very stripped-down minimalist platform,
  23  *    both because this reduces the security attack surface from the guest
  24  *    and also because it reduces our exposure to being broken when
  25  *    the kernel updates its device tree bindings and requires further
  26  *    information in a device binding that we aren't providing.
  27  * This is essentially the same approach kvmtool uses.
  28  */
  29
  30 #ifndef QEMU_ARM_VIRT_H
  31 #define QEMU_ARM_VIRT_H
  32
  33 #include "exec/hwaddr.h"
  34 #include "qemu/notify.h"
  35 #include "hw/boards.h"
  36 #include "hw/arm/boot.h"
  37 #include "hw/block/flash.h"
  38 #include "sysemu/kvm.h"
  39 #include "hw/intc/arm_gicv3_common.h"
  40
  41 #define NUM_GICV2M_SPIS       64
  42 #define NUM_VIRTIO_TRANSPORTS 32
  43 #define NUM_SMMU_IRQS          4
  44
  45 #define ARCH_GIC_MAINT_IRQ  9
  46
  47 #define ARCH_TIMER_VIRT_IRQ   11
  48 #define ARCH_TIMER_S_EL1_IRQ  13
  49 #define ARCH_TIMER_NS_EL1_IRQ 14
  50 #define ARCH_TIMER_NS_EL2_IRQ 10
  51
  52 #define VIRTUAL_PMU_IRQ 7
  53
  54 #define PPI(irq) ((irq) + 16)
  55
  56 enum {
  57     VIRT_FLASH,
  58     VIRT_MEM,
  59     VIRT_CPUPERIPHS,
  60     VIRT_GIC_DIST,
  61     VIRT_GIC_CPU,
  62     VIRT_GIC_V2M,
  63     VIRT_GIC_HYP,
  64     VIRT_GIC_VCPU,
  65     VIRT_GIC_ITS,
  66     VIRT_GIC_REDIST,
  67     VIRT_SMMU,
  68     VIRT_UART,
  69     VIRT_MMIO,
  70     VIRT_RTC,
  71     VIRT_FW_CFG,
  72     VIRT_PCIE,
  73     VIRT_PCIE_MMIO,
  74     VIRT_PCIE_PIO,
  75     VIRT_PCIE_ECAM,
  76     VIRT_PLATFORM_BUS,
  77     VIRT_GPIO,
  78     VIRT_SECURE_UART,
  79     VIRT_SECURE_MEM,
  80     VIRT_LOWMEMMAP_LAST,
  81 };
  82
  83 /* indices of IO regions located after the RAM */
  84 enum {
  85     VIRT_HIGH_GIC_REDIST2 =  VIRT_LOWMEMMAP_LAST,
  86     VIRT_HIGH_PCIE_ECAM,
  87     VIRT_HIGH_PCIE_MMIO,
  88 };
  89
  90 typedef enum VirtIOMMUType {
  91     VIRT_IOMMU_NONE,
  92     VIRT_IOMMU_SMMUV3,
  93     VIRT_IOMMU_VIRTIO,
  94 } VirtIOMMUType;
  95
  96 typedef struct MemMapEntry {
  97     hwaddr base;
  98     hwaddr size;
  99 } MemMapEntry;
 100
 101 typedef struct {
 102     MachineClass parent;
 103     bool disallow_affinity_adjustment;
 104     bool no_its;
 105     bool no_pmu;
 106     bool claim_edge_triggered_timers;
 107     bool smbios_old_sys_ver;
 108     bool no_highmem_ecam;
 109 } VirtMachineClass;
 110
 111 typedef struct {
 112     MachineState parent;
 113     Notifier machine_done;
 114     DeviceState *platform_bus_dev;
 115     FWCfgState *fw_cfg;
 116     PFlashCFI01 *flash[2];
 117     bool secure;
 118     bool highmem;
 119     bool highmem_ecam;
 120     bool its;
 121     bool virt;
 122     int32_t gic_version;
 123     VirtIOMMUType iommu;
 124     struct arm_boot_info bootinfo;
 125     MemMapEntry *memmap;
 126     const int *irqmap;
 127     int smp_cpus;
 128     void *fdt;
 129     int fdt_size;
 130     uint32_t clock_phandle;
 131     uint32_t gic_phandle;
 132     uint32_t msi_phandle;
 133     uint32_t iommu_phandle;
 134     int psci_conduit;
 135     hwaddr highest_gpa;
 136 } VirtMachineState;
 137
 138 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
 139
 140 #define TYPE_VIRT_MACHINE   MACHINE_TYPE_NAME("virt")
 141 #define VIRT_MACHINE(obj) \
 142     OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
 143 #define VIRT_MACHINE_GET_CLASS(obj) \
 144     OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
 145 #define VIRT_MACHINE_CLASS(klass) \
 146     OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
 147
 148 void virt_acpi_setup(VirtMachineState *vms);
 149
 150 /* Return the number of used redistributor regions  */
 151 static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
 152 {
 153     uint32_t redist0_capacity =
 154                 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
 155
 156     assert(vms->gic_version == 3);
 157
 158     return vms->smp_cpus > redist0_capacity ? 2 : 1;
 159 }
 160
 161 #endif /* QEMU_ARM_VIRT_H */