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monitor/qmp: Update comment for commit 4eaca8de268
[qemu/armbru.git] / target / ppc / translate.c
blob9f9553afb46aa1b0681d1032b30306542d287546
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "internal.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
26 #include "tcg-op.h"
27 #include "tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "qemu/main-loop.h"
30 #include "exec/cpu_ldst.h"
31
32 #include "exec/helper-proto.h"
33 #include "exec/helper-gen.h"
34
35 #include "trace-tcg.h"
36 #include "exec/translator.h"
37 #include "exec/log.h"
38 #include "qemu/atomic128.h"
39
40
41 #define CPU_SINGLE_STEP 0x1
42 #define CPU_BRANCH_STEP 0x2
43 #define GDBSTUB_SINGLE_STEP 0x4
44
45 /* Include definitions for instructions classes and implementations flags */
46 /* #define PPC_DEBUG_DISAS */
47 /* #define DO_PPC_STATISTICS */
48
49 #ifdef PPC_DEBUG_DISAS
50 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
51 #else
52 # define LOG_DISAS(...) do { } while (0)
53 #endif
54 /*****************************************************************************/
55 /* Code translation helpers */
56
57 /* global register indexes */
58 static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */
59 + 10 * 4 + 22 * 5 /* SPE GPRh */
60 + 8 * 5 /* CRF */];
61 static TCGv cpu_gpr[32];
62 static TCGv cpu_gprh[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
72 static TCGv cpu_reserve;
73 static TCGv cpu_reserve_val;
74 static TCGv cpu_fpscr;
75 static TCGv_i32 cpu_access_type;
76
77 #include "exec/gen-icount.h"
78
79 void ppc_translate_init(void)
80 {
81 int i;
82 char *p;
83 size_t cpu_reg_names_size;
84
85 p = cpu_reg_names;
86 cpu_reg_names_size = sizeof(cpu_reg_names);
87
88 for (i = 0; i < 8; i++) {
89 snprintf(p, cpu_reg_names_size, "crf%d", i);
90 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
91 offsetof(CPUPPCState, crf[i]), p);
92 p += 5;
93 cpu_reg_names_size -= 5;
94 }
95
96 for (i = 0; i < 32; i++) {
97 snprintf(p, cpu_reg_names_size, "r%d", i);
98 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
99 offsetof(CPUPPCState, gpr[i]), p);
100 p += (i < 10) ? 3 : 4;
101 cpu_reg_names_size -= (i < 10) ? 3 : 4;
102 snprintf(p, cpu_reg_names_size, "r%dH", i);
103 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
104 offsetof(CPUPPCState, gprh[i]), p);
105 p += (i < 10) ? 4 : 5;
106 cpu_reg_names_size -= (i < 10) ? 4 : 5;
107 }
108
109 cpu_nip = tcg_global_mem_new(cpu_env,
110 offsetof(CPUPPCState, nip), "nip");
111
112 cpu_msr = tcg_global_mem_new(cpu_env,
113 offsetof(CPUPPCState, msr), "msr");
114
115 cpu_ctr = tcg_global_mem_new(cpu_env,
116 offsetof(CPUPPCState, ctr), "ctr");
117
118 cpu_lr = tcg_global_mem_new(cpu_env,
119 offsetof(CPUPPCState, lr), "lr");
120
121 #if defined(TARGET_PPC64)
122 cpu_cfar = tcg_global_mem_new(cpu_env,
123 offsetof(CPUPPCState, cfar), "cfar");
124 #endif
125
126 cpu_xer = tcg_global_mem_new(cpu_env,
127 offsetof(CPUPPCState, xer), "xer");
128 cpu_so = tcg_global_mem_new(cpu_env,
129 offsetof(CPUPPCState, so), "SO");
130 cpu_ov = tcg_global_mem_new(cpu_env,
131 offsetof(CPUPPCState, ov), "OV");
132 cpu_ca = tcg_global_mem_new(cpu_env,
133 offsetof(CPUPPCState, ca), "CA");
134 cpu_ov32 = tcg_global_mem_new(cpu_env,
135 offsetof(CPUPPCState, ov32), "OV32");
136 cpu_ca32 = tcg_global_mem_new(cpu_env,
137 offsetof(CPUPPCState, ca32), "CA32");
138
139 cpu_reserve = tcg_global_mem_new(cpu_env,
140 offsetof(CPUPPCState, reserve_addr),
141 "reserve_addr");
142 cpu_reserve_val = tcg_global_mem_new(cpu_env,
143 offsetof(CPUPPCState, reserve_val),
144 "reserve_val");
145
146 cpu_fpscr = tcg_global_mem_new(cpu_env,
147 offsetof(CPUPPCState, fpscr), "fpscr");
148
149 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
150 offsetof(CPUPPCState, access_type),
151 "access_type");
152 }
153
154 /* internal defines */
155 struct DisasContext {
156 DisasContextBase base;
157 uint32_t opcode;
158 uint32_t exception;
159 /* Routine used to access memory */
160 bool pr, hv, dr, le_mode;
161 bool lazy_tlb_flush;
162 bool need_access_type;
163 int mem_idx;
164 int access_type;
165 /* Translation flags */
166 TCGMemOp default_tcg_memop_mask;
167 #if defined(TARGET_PPC64)
168 bool sf_mode;
169 bool has_cfar;
170 #endif
171 bool fpu_enabled;
172 bool altivec_enabled;
173 bool vsx_enabled;
174 bool spe_enabled;
175 bool tm_enabled;
176 bool gtse;
177 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
178 int singlestep_enabled;
179 uint32_t flags;
180 uint64_t insns_flags;
181 uint64_t insns_flags2;
182 };
183
184 /* Return true iff byteswap is needed in a scalar memop */
185 static inline bool need_byteswap(const DisasContext *ctx)
186 {
187 #if defined(TARGET_WORDS_BIGENDIAN)
188 return ctx->le_mode;
189 #else
190 return !ctx->le_mode;
191 #endif
192 }
193
194 /* True when active word size < size of target_long. */
195 #ifdef TARGET_PPC64
196 # define NARROW_MODE(C) (!(C)->sf_mode)
197 #else
198 # define NARROW_MODE(C) 0
199 #endif
200
201 struct opc_handler_t {
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 uint32_t inval1;
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 uint32_t inval2;
206 /* instruction type */
207 uint64_t type;
208 /* extended instruction type */
209 uint64_t type2;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214 #endif
215 #if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217 #endif
218 };
219
220 /* SPR load/store helpers */
221 static inline void gen_load_spr(TCGv t, int reg)
222 {
223 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
224 }
225
226 static inline void gen_store_spr(int reg, TCGv t)
227 {
228 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
229 }
230
231 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
232 {
233 if (ctx->need_access_type && ctx->access_type != access_type) {
234 tcg_gen_movi_i32(cpu_access_type, access_type);
235 ctx->access_type = access_type;
236 }
237 }
238
239 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
240 {
241 if (NARROW_MODE(ctx)) {
242 nip = (uint32_t)nip;
243 }
244 tcg_gen_movi_tl(cpu_nip, nip);
245 }
246
247 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
248 {
249 TCGv_i32 t0, t1;
250
251 /*
252 * These are all synchronous exceptions, we set the PC back to the
253 * faulting instruction
254 */
255 if (ctx->exception == POWERPC_EXCP_NONE) {
256 gen_update_nip(ctx, ctx->base.pc_next - 4);
257 }
258 t0 = tcg_const_i32(excp);
259 t1 = tcg_const_i32(error);
260 gen_helper_raise_exception_err(cpu_env, t0, t1);
261 tcg_temp_free_i32(t0);
262 tcg_temp_free_i32(t1);
263 ctx->exception = (excp);
264 }
265
266 static void gen_exception(DisasContext *ctx, uint32_t excp)
267 {
268 TCGv_i32 t0;
269
270 /*
271 * These are all synchronous exceptions, we set the PC back to the
272 * faulting instruction
273 */
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->base.pc_next - 4);
276 }
277 t0 = tcg_const_i32(excp);
278 gen_helper_raise_exception(cpu_env, t0);
279 tcg_temp_free_i32(t0);
280 ctx->exception = (excp);
281 }
282
283 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
284 target_ulong nip)
285 {
286 TCGv_i32 t0;
287
288 gen_update_nip(ctx, nip);
289 t0 = tcg_const_i32(excp);
290 gen_helper_raise_exception(cpu_env, t0);
291 tcg_temp_free_i32(t0);
292 ctx->exception = (excp);
293 }
294
295 /*
296 * Tells the caller what is the appropriate exception to generate and prepares
297 * SPR registers for this exception.
298 *
299 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
300 * POWERPC_EXCP_DEBUG (on BookE).
301 */
302 static uint32_t gen_prep_dbgex(DisasContext *ctx)
303 {
304 if (ctx->flags & POWERPC_FLAG_DE) {
305 target_ulong dbsr = 0;
306 if (ctx->singlestep_enabled & CPU_SINGLE_STEP) {
307 dbsr = DBCR0_ICMP;
308 } else {
309 /* Must have been branch */
310 dbsr = DBCR0_BRT;
311 }
312 TCGv t0 = tcg_temp_new();
313 gen_load_spr(t0, SPR_BOOKE_DBSR);
314 tcg_gen_ori_tl(t0, t0, dbsr);
315 gen_store_spr(SPR_BOOKE_DBSR, t0);
316 tcg_temp_free(t0);
317 return POWERPC_EXCP_DEBUG;
318 } else {
319 return POWERPC_EXCP_TRACE;
320 }
321 }
322
323 static void gen_debug_exception(DisasContext *ctx)
324 {
325 TCGv_i32 t0;
326
327 /*
328 * These are all synchronous exceptions, we set the PC back to the
329 * faulting instruction
330 */
331 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
332 (ctx->exception != POWERPC_EXCP_SYNC)) {
333 gen_update_nip(ctx, ctx->base.pc_next);
334 }
335 t0 = tcg_const_i32(EXCP_DEBUG);
336 gen_helper_raise_exception(cpu_env, t0);
337 tcg_temp_free_i32(t0);
338 }
339
340 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
341 {
342 /* Will be converted to program check if needed */
343 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
344 }
345
346 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
347 {
348 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
349 }
350
351 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
352 {
353 /* Will be converted to program check if needed */
354 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
355 }
356
357 /* Stop translation */
358 static inline void gen_stop_exception(DisasContext *ctx)
359 {
360 gen_update_nip(ctx, ctx->base.pc_next);
361 ctx->exception = POWERPC_EXCP_STOP;
362 }
363
364 #ifndef CONFIG_USER_ONLY
365 /* No need to update nip here, as execution flow will change */
366 static inline void gen_sync_exception(DisasContext *ctx)
367 {
368 ctx->exception = POWERPC_EXCP_SYNC;
369 }
370 #endif
371
372 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
373 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
374
375 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
376 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
377
378 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
379 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
380
381 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
382 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
383
384 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
385 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
386
387 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
388 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
389
390 typedef struct opcode_t {
391 unsigned char opc1, opc2, opc3, opc4;
392 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
393 unsigned char pad[4];
394 #endif
395 opc_handler_t handler;
396 const char *oname;
397 } opcode_t;
398
399 /* Helpers for priv. check */
400 #define GEN_PRIV \
401 do { \
402 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
403 } while (0)
404
405 #if defined(CONFIG_USER_ONLY)
406 #define CHK_HV GEN_PRIV
407 #define CHK_SV GEN_PRIV
408 #define CHK_HVRM GEN_PRIV
409 #else
410 #define CHK_HV \
411 do { \
412 if (unlikely(ctx->pr || !ctx->hv)) { \
413 GEN_PRIV; \
414 } \
415 } while (0)
416 #define CHK_SV \
417 do { \
418 if (unlikely(ctx->pr)) { \
419 GEN_PRIV; \
420 } \
421 } while (0)
422 #define CHK_HVRM \
423 do { \
424 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
425 GEN_PRIV; \
426 } \
427 } while (0)
428 #endif
429
430 #define CHK_NONE
431
432 /*****************************************************************************/
433 /* PowerPC instructions table */
434
435 #if defined(DO_PPC_STATISTICS)
436 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
437 { \
438 .opc1 = op1, \
439 .opc2 = op2, \
440 .opc3 = op3, \
441 .opc4 = 0xff, \
442 .handler = { \
443 .inval1 = invl, \
444 .type = _typ, \
445 .type2 = _typ2, \
446 .handler = &gen_##name, \
447 .oname = stringify(name), \
448 }, \
449 .oname = stringify(name), \
450 }
451 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
452 { \
453 .opc1 = op1, \
454 .opc2 = op2, \
455 .opc3 = op3, \
456 .opc4 = 0xff, \
457 .handler = { \
458 .inval1 = invl1, \
459 .inval2 = invl2, \
460 .type = _typ, \
461 .type2 = _typ2, \
462 .handler = &gen_##name, \
463 .oname = stringify(name), \
464 }, \
465 .oname = stringify(name), \
466 }
467 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
468 { \
469 .opc1 = op1, \
470 .opc2 = op2, \
471 .opc3 = op3, \
472 .opc4 = 0xff, \
473 .handler = { \
474 .inval1 = invl, \
475 .type = _typ, \
476 .type2 = _typ2, \
477 .handler = &gen_##name, \
478 .oname = onam, \
479 }, \
480 .oname = onam, \
481 }
482 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
483 { \
484 .opc1 = op1, \
485 .opc2 = op2, \
486 .opc3 = op3, \
487 .opc4 = op4, \
488 .handler = { \
489 .inval1 = invl, \
490 .type = _typ, \
491 .type2 = _typ2, \
492 .handler = &gen_##name, \
493 .oname = stringify(name), \
494 }, \
495 .oname = stringify(name), \
496 }
497 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
498 { \
499 .opc1 = op1, \
500 .opc2 = op2, \
501 .opc3 = op3, \
502 .opc4 = op4, \
503 .handler = { \
504 .inval1 = invl, \
505 .type = _typ, \
506 .type2 = _typ2, \
507 .handler = &gen_##name, \
508 .oname = onam, \
509 }, \
510 .oname = onam, \
511 }
512 #else
513 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
514 { \
515 .opc1 = op1, \
516 .opc2 = op2, \
517 .opc3 = op3, \
518 .opc4 = 0xff, \
519 .handler = { \
520 .inval1 = invl, \
521 .type = _typ, \
522 .type2 = _typ2, \
523 .handler = &gen_##name, \
524 }, \
525 .oname = stringify(name), \
526 }
527 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
528 { \
529 .opc1 = op1, \
530 .opc2 = op2, \
531 .opc3 = op3, \
532 .opc4 = 0xff, \
533 .handler = { \
534 .inval1 = invl1, \
535 .inval2 = invl2, \
536 .type = _typ, \
537 .type2 = _typ2, \
538 .handler = &gen_##name, \
539 }, \
540 .oname = stringify(name), \
541 }
542 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
543 { \
544 .opc1 = op1, \
545 .opc2 = op2, \
546 .opc3 = op3, \
547 .opc4 = 0xff, \
548 .handler = { \
549 .inval1 = invl, \
550 .type = _typ, \
551 .type2 = _typ2, \
552 .handler = &gen_##name, \
553 }, \
554 .oname = onam, \
555 }
556 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
557 { \
558 .opc1 = op1, \
559 .opc2 = op2, \
560 .opc3 = op3, \
561 .opc4 = op4, \
562 .handler = { \
563 .inval1 = invl, \
564 .type = _typ, \
565 .type2 = _typ2, \
566 .handler = &gen_##name, \
567 }, \
568 .oname = stringify(name), \
569 }
570 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
571 { \
572 .opc1 = op1, \
573 .opc2 = op2, \
574 .opc3 = op3, \
575 .opc4 = op4, \
576 .handler = { \
577 .inval1 = invl, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = onam, \
583 }
584 #endif
585
586 /* Invalid instruction */
587 static void gen_invalid(DisasContext *ctx)
588 {
589 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
590 }
591
592 static opc_handler_t invalid_handler = {
593 .inval1 = 0xFFFFFFFF,
594 .inval2 = 0xFFFFFFFF,
595 .type = PPC_NONE,
596 .type2 = PPC_NONE,
597 .handler = gen_invalid,
598 };
599
600 /*** Integer comparison ***/
601
602 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
603 {
604 TCGv t0 = tcg_temp_new();
605 TCGv t1 = tcg_temp_new();
606 TCGv_i32 t = tcg_temp_new_i32();
607
608 tcg_gen_movi_tl(t0, CRF_EQ);
609 tcg_gen_movi_tl(t1, CRF_LT);
610 tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU),
611 t0, arg0, arg1, t1, t0);
612 tcg_gen_movi_tl(t1, CRF_GT);
613 tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU),
614 t0, arg0, arg1, t1, t0);
615
616 tcg_gen_trunc_tl_i32(t, t0);
617 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
618 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
619
620 tcg_temp_free(t0);
621 tcg_temp_free(t1);
622 tcg_temp_free_i32(t);
623 }
624
625 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
626 {
627 TCGv t0 = tcg_const_tl(arg1);
628 gen_op_cmp(arg0, t0, s, crf);
629 tcg_temp_free(t0);
630 }
631
632 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
633 {
634 TCGv t0, t1;
635 t0 = tcg_temp_new();
636 t1 = tcg_temp_new();
637 if (s) {
638 tcg_gen_ext32s_tl(t0, arg0);
639 tcg_gen_ext32s_tl(t1, arg1);
640 } else {
641 tcg_gen_ext32u_tl(t0, arg0);
642 tcg_gen_ext32u_tl(t1, arg1);
643 }
644 gen_op_cmp(t0, t1, s, crf);
645 tcg_temp_free(t1);
646 tcg_temp_free(t0);
647 }
648
649 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
650 {
651 TCGv t0 = tcg_const_tl(arg1);
652 gen_op_cmp32(arg0, t0, s, crf);
653 tcg_temp_free(t0);
654 }
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 if (NARROW_MODE(ctx)) {
659 gen_op_cmpi32(reg, 0, 1, 0);
660 } else {
661 gen_op_cmpi(reg, 0, 1, 0);
662 }
663 }
664
665 /* cmp */
666 static void gen_cmp(DisasContext *ctx)
667 {
668 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
669 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
670 1, crfD(ctx->opcode));
671 } else {
672 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
673 1, crfD(ctx->opcode));
674 }
675 }
676
677 /* cmpi */
678 static void gen_cmpi(DisasContext *ctx)
679 {
680 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
681 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
682 1, crfD(ctx->opcode));
683 } else {
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 }
687 }
688
689 /* cmpl */
690 static void gen_cmpl(DisasContext *ctx)
691 {
692 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
693 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
694 0, crfD(ctx->opcode));
695 } else {
696 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
697 0, crfD(ctx->opcode));
698 }
699 }
700
701 /* cmpli */
702 static void gen_cmpli(DisasContext *ctx)
703 {
704 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
705 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
706 0, crfD(ctx->opcode));
707 } else {
708 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
709 0, crfD(ctx->opcode));
710 }
711 }
712
713 /* cmprb - range comparison: isupper, isaplha, islower*/
714 static void gen_cmprb(DisasContext *ctx)
715 {
716 TCGv_i32 src1 = tcg_temp_new_i32();
717 TCGv_i32 src2 = tcg_temp_new_i32();
718 TCGv_i32 src2lo = tcg_temp_new_i32();
719 TCGv_i32 src2hi = tcg_temp_new_i32();
720 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
721
722 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
723 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
724
725 tcg_gen_andi_i32(src1, src1, 0xFF);
726 tcg_gen_ext8u_i32(src2lo, src2);
727 tcg_gen_shri_i32(src2, src2, 8);
728 tcg_gen_ext8u_i32(src2hi, src2);
729
730 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
731 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
732 tcg_gen_and_i32(crf, src2lo, src2hi);
733
734 if (ctx->opcode & 0x00200000) {
735 tcg_gen_shri_i32(src2, src2, 8);
736 tcg_gen_ext8u_i32(src2lo, src2);
737 tcg_gen_shri_i32(src2, src2, 8);
738 tcg_gen_ext8u_i32(src2hi, src2);
739 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
740 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
741 tcg_gen_and_i32(src2lo, src2lo, src2hi);
742 tcg_gen_or_i32(crf, crf, src2lo);
743 }
744 tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
745 tcg_temp_free_i32(src1);
746 tcg_temp_free_i32(src2);
747 tcg_temp_free_i32(src2lo);
748 tcg_temp_free_i32(src2hi);
749 }
750
751 #if defined(TARGET_PPC64)
752 /* cmpeqb */
753 static void gen_cmpeqb(DisasContext *ctx)
754 {
755 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
756 cpu_gpr[rB(ctx->opcode)]);
757 }
758 #endif
759
760 /* isel (PowerPC 2.03 specification) */
761 static void gen_isel(DisasContext *ctx)
762 {
763 uint32_t bi = rC(ctx->opcode);
764 uint32_t mask = 0x08 >> (bi & 0x03);
765 TCGv t0 = tcg_temp_new();
766 TCGv zr;
767
768 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
769 tcg_gen_andi_tl(t0, t0, mask);
770
771 zr = tcg_const_tl(0);
772 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
773 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
774 cpu_gpr[rB(ctx->opcode)]);
775 tcg_temp_free(zr);
776 tcg_temp_free(t0);
777 }
778
779 /* cmpb: PowerPC 2.05 specification */
780 static void gen_cmpb(DisasContext *ctx)
781 {
782 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
783 cpu_gpr[rB(ctx->opcode)]);
784 }
785
786 /*** Integer arithmetic ***/
787
788 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
789 TCGv arg1, TCGv arg2, int sub)
790 {
791 TCGv t0 = tcg_temp_new();
792
793 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
794 tcg_gen_xor_tl(t0, arg1, arg2);
795 if (sub) {
796 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
797 } else {
798 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
799 }
800 tcg_temp_free(t0);
801 if (NARROW_MODE(ctx)) {
802 tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
803 if (is_isa300(ctx)) {
804 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
805 }
806 } else {
807 if (is_isa300(ctx)) {
808 tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
809 }
810 tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1);
811 }
812 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
813 }
814
815 static inline void gen_op_arith_compute_ca32(DisasContext *ctx,
816 TCGv res, TCGv arg0, TCGv arg1,
817 TCGv ca32, int sub)
818 {
819 TCGv t0;
820
821 if (!is_isa300(ctx)) {
822 return;
823 }
824
825 t0 = tcg_temp_new();
826 if (sub) {
827 tcg_gen_eqv_tl(t0, arg0, arg1);
828 } else {
829 tcg_gen_xor_tl(t0, arg0, arg1);
830 }
831 tcg_gen_xor_tl(t0, t0, res);
832 tcg_gen_extract_tl(ca32, t0, 32, 1);
833 tcg_temp_free(t0);
834 }
835
836 /* Common add function */
837 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
838 TCGv arg2, TCGv ca, TCGv ca32,
839 bool add_ca, bool compute_ca,
840 bool compute_ov, bool compute_rc0)
841 {
842 TCGv t0 = ret;
843
844 if (compute_ca || compute_ov) {
845 t0 = tcg_temp_new();
846 }
847
848 if (compute_ca) {
849 if (NARROW_MODE(ctx)) {
850 /*
851 * Caution: a non-obvious corner case of the spec is that
852 * we must produce the *entire* 64-bit addition, but
853 * produce the carry into bit 32.
854 */
855 TCGv t1 = tcg_temp_new();
856 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
857 tcg_gen_add_tl(t0, arg1, arg2);
858 if (add_ca) {
859 tcg_gen_add_tl(t0, t0, ca);
860 }
861 tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */
862 tcg_temp_free(t1);
863 tcg_gen_extract_tl(ca, ca, 32, 1);
864 if (is_isa300(ctx)) {
865 tcg_gen_mov_tl(ca32, ca);
866 }
867 } else {
868 TCGv zero = tcg_const_tl(0);
869 if (add_ca) {
870 tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
871 tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
872 } else {
873 tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
874 }
875 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
876 tcg_temp_free(zero);
877 }
878 } else {
879 tcg_gen_add_tl(t0, arg1, arg2);
880 if (add_ca) {
881 tcg_gen_add_tl(t0, t0, ca);
882 }
883 }
884
885 if (compute_ov) {
886 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
887 }
888 if (unlikely(compute_rc0)) {
889 gen_set_Rc0(ctx, t0);
890 }
891
892 if (t0 != ret) {
893 tcg_gen_mov_tl(ret, t0);
894 tcg_temp_free(t0);
895 }
896 }
897 /* Add functions with two operands */
898 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
899 static void glue(gen_, name)(DisasContext *ctx) \
900 { \
901 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
902 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
903 ca, glue(ca, 32), \
904 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
905 }
906 /* Add functions with one operand and one immediate */
907 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
908 add_ca, compute_ca, compute_ov) \
909 static void glue(gen_, name)(DisasContext *ctx) \
910 { \
911 TCGv t0 = tcg_const_tl(const_val); \
912 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
913 cpu_gpr[rA(ctx->opcode)], t0, \
914 ca, glue(ca, 32), \
915 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
916 tcg_temp_free(t0); \
917 }
918
919 /* add add. addo addo. */
920 GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0)
921 GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1)
922 /* addc addc. addco addco. */
923 GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0)
924 GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1)
925 /* adde adde. addeo addeo. */
926 GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0)
927 GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1)
928 /* addme addme. addmeo addmeo. */
929 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0)
930 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1)
931 /* addex */
932 GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0);
933 /* addze addze. addzeo addzeo.*/
934 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0)
935 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
936 /* addi */
937 static void gen_addi(DisasContext *ctx)
938 {
939 target_long simm = SIMM(ctx->opcode);
940
941 if (rA(ctx->opcode) == 0) {
942 /* li case */
943 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
944 } else {
945 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
946 cpu_gpr[rA(ctx->opcode)], simm);
947 }
948 }
949 /* addic addic.*/
950 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
951 {
952 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
953 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
954 c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
955 tcg_temp_free(c);
956 }
957
958 static void gen_addic(DisasContext *ctx)
959 {
960 gen_op_addic(ctx, 0);
961 }
962
963 static void gen_addic_(DisasContext *ctx)
964 {
965 gen_op_addic(ctx, 1);
966 }
967
968 /* addis */
969 static void gen_addis(DisasContext *ctx)
970 {
971 target_long simm = SIMM(ctx->opcode);
972
973 if (rA(ctx->opcode) == 0) {
974 /* lis case */
975 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
976 } else {
977 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
978 cpu_gpr[rA(ctx->opcode)], simm << 16);
979 }
980 }
981
982 /* addpcis */
983 static void gen_addpcis(DisasContext *ctx)
984 {
985 target_long d = DX(ctx->opcode);
986
987 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16));
988 }
989
990 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
991 TCGv arg2, int sign, int compute_ov)
992 {
993 TCGv_i32 t0 = tcg_temp_new_i32();
994 TCGv_i32 t1 = tcg_temp_new_i32();
995 TCGv_i32 t2 = tcg_temp_new_i32();
996 TCGv_i32 t3 = tcg_temp_new_i32();
997
998 tcg_gen_trunc_tl_i32(t0, arg1);
999 tcg_gen_trunc_tl_i32(t1, arg2);
1000 if (sign) {
1001 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1002 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1003 tcg_gen_and_i32(t2, t2, t3);
1004 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1005 tcg_gen_or_i32(t2, t2, t3);
1006 tcg_gen_movi_i32(t3, 0);
1007 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1008 tcg_gen_div_i32(t3, t0, t1);
1009 tcg_gen_extu_i32_tl(ret, t3);
1010 } else {
1011 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0);
1012 tcg_gen_movi_i32(t3, 0);
1013 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1014 tcg_gen_divu_i32(t3, t0, t1);
1015 tcg_gen_extu_i32_tl(ret, t3);
1016 }
1017 if (compute_ov) {
1018 tcg_gen_extu_i32_tl(cpu_ov, t2);
1019 if (is_isa300(ctx)) {
1020 tcg_gen_extu_i32_tl(cpu_ov32, t2);
1021 }
1022 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1023 }
1024 tcg_temp_free_i32(t0);
1025 tcg_temp_free_i32(t1);
1026 tcg_temp_free_i32(t2);
1027 tcg_temp_free_i32(t3);
1028
1029 if (unlikely(Rc(ctx->opcode) != 0)) {
1030 gen_set_Rc0(ctx, ret);
1031 }
1032 }
1033 /* Div functions */
1034 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1035 static void glue(gen_, name)(DisasContext *ctx) \
1036 { \
1037 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1038 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1039 sign, compute_ov); \
1040 }
1041 /* divwu divwu. divwuo divwuo. */
1042 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1043 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1044 /* divw divw. divwo divwo. */
1045 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1046 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1047
1048 /* div[wd]eu[o][.] */
1049 #define GEN_DIVE(name, hlpr, compute_ov) \
1050 static void gen_##name(DisasContext *ctx) \
1051 { \
1052 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1053 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1054 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1055 tcg_temp_free_i32(t0); \
1056 if (unlikely(Rc(ctx->opcode) != 0)) { \
1057 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1058 } \
1059 }
1060
1061 GEN_DIVE(divweu, divweu, 0);
1062 GEN_DIVE(divweuo, divweu, 1);
1063 GEN_DIVE(divwe, divwe, 0);
1064 GEN_DIVE(divweo, divwe, 1);
1065
1066 #if defined(TARGET_PPC64)
1067 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1068 TCGv arg2, int sign, int compute_ov)
1069 {
1070 TCGv_i64 t0 = tcg_temp_new_i64();
1071 TCGv_i64 t1 = tcg_temp_new_i64();
1072 TCGv_i64 t2 = tcg_temp_new_i64();
1073 TCGv_i64 t3 = tcg_temp_new_i64();
1074
1075 tcg_gen_mov_i64(t0, arg1);
1076 tcg_gen_mov_i64(t1, arg2);
1077 if (sign) {
1078 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1079 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1080 tcg_gen_and_i64(t2, t2, t3);
1081 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1082 tcg_gen_or_i64(t2, t2, t3);
1083 tcg_gen_movi_i64(t3, 0);
1084 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1085 tcg_gen_div_i64(ret, t0, t1);
1086 } else {
1087 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0);
1088 tcg_gen_movi_i64(t3, 0);
1089 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1090 tcg_gen_divu_i64(ret, t0, t1);
1091 }
1092 if (compute_ov) {
1093 tcg_gen_mov_tl(cpu_ov, t2);
1094 if (is_isa300(ctx)) {
1095 tcg_gen_mov_tl(cpu_ov32, t2);
1096 }
1097 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1098 }
1099 tcg_temp_free_i64(t0);
1100 tcg_temp_free_i64(t1);
1101 tcg_temp_free_i64(t2);
1102 tcg_temp_free_i64(t3);
1103
1104 if (unlikely(Rc(ctx->opcode) != 0)) {
1105 gen_set_Rc0(ctx, ret);
1106 }
1107 }
1108
1109 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1110 static void glue(gen_, name)(DisasContext *ctx) \
1111 { \
1112 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115 }
1116 /* divdu divdu. divduo divduo. */
1117 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1118 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1119 /* divd divd. divdo divdo. */
1120 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1121 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1122
1123 GEN_DIVE(divdeu, divdeu, 0);
1124 GEN_DIVE(divdeuo, divdeu, 1);
1125 GEN_DIVE(divde, divde, 0);
1126 GEN_DIVE(divdeo, divde, 1);
1127 #endif
1128
1129 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1130 TCGv arg2, int sign)
1131 {
1132 TCGv_i32 t0 = tcg_temp_new_i32();
1133 TCGv_i32 t1 = tcg_temp_new_i32();
1134
1135 tcg_gen_trunc_tl_i32(t0, arg1);
1136 tcg_gen_trunc_tl_i32(t1, arg2);
1137 if (sign) {
1138 TCGv_i32 t2 = tcg_temp_new_i32();
1139 TCGv_i32 t3 = tcg_temp_new_i32();
1140 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1141 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1142 tcg_gen_and_i32(t2, t2, t3);
1143 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1144 tcg_gen_or_i32(t2, t2, t3);
1145 tcg_gen_movi_i32(t3, 0);
1146 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1147 tcg_gen_rem_i32(t3, t0, t1);
1148 tcg_gen_ext_i32_tl(ret, t3);
1149 tcg_temp_free_i32(t2);
1150 tcg_temp_free_i32(t3);
1151 } else {
1152 TCGv_i32 t2 = tcg_const_i32(1);
1153 TCGv_i32 t3 = tcg_const_i32(0);
1154 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1155 tcg_gen_remu_i32(t3, t0, t1);
1156 tcg_gen_extu_i32_tl(ret, t3);
1157 tcg_temp_free_i32(t2);
1158 tcg_temp_free_i32(t3);
1159 }
1160 tcg_temp_free_i32(t0);
1161 tcg_temp_free_i32(t1);
1162 }
1163
1164 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1165 static void glue(gen_, name)(DisasContext *ctx) \
1166 { \
1167 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1168 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1169 sign); \
1170 }
1171
1172 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1173 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1174
1175 #if defined(TARGET_PPC64)
1176 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1177 TCGv arg2, int sign)
1178 {
1179 TCGv_i64 t0 = tcg_temp_new_i64();
1180 TCGv_i64 t1 = tcg_temp_new_i64();
1181
1182 tcg_gen_mov_i64(t0, arg1);
1183 tcg_gen_mov_i64(t1, arg2);
1184 if (sign) {
1185 TCGv_i64 t2 = tcg_temp_new_i64();
1186 TCGv_i64 t3 = tcg_temp_new_i64();
1187 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1188 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1189 tcg_gen_and_i64(t2, t2, t3);
1190 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1191 tcg_gen_or_i64(t2, t2, t3);
1192 tcg_gen_movi_i64(t3, 0);
1193 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1194 tcg_gen_rem_i64(ret, t0, t1);
1195 tcg_temp_free_i64(t2);
1196 tcg_temp_free_i64(t3);
1197 } else {
1198 TCGv_i64 t2 = tcg_const_i64(1);
1199 TCGv_i64 t3 = tcg_const_i64(0);
1200 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1201 tcg_gen_remu_i64(ret, t0, t1);
1202 tcg_temp_free_i64(t2);
1203 tcg_temp_free_i64(t3);
1204 }
1205 tcg_temp_free_i64(t0);
1206 tcg_temp_free_i64(t1);
1207 }
1208
1209 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1210 static void glue(gen_, name)(DisasContext *ctx) \
1211 { \
1212 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1213 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1214 sign); \
1215 }
1216
1217 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1218 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1219 #endif
1220
1221 /* mulhw mulhw. */
1222 static void gen_mulhw(DisasContext *ctx)
1223 {
1224 TCGv_i32 t0 = tcg_temp_new_i32();
1225 TCGv_i32 t1 = tcg_temp_new_i32();
1226
1227 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1228 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1229 tcg_gen_muls2_i32(t0, t1, t0, t1);
1230 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1231 tcg_temp_free_i32(t0);
1232 tcg_temp_free_i32(t1);
1233 if (unlikely(Rc(ctx->opcode) != 0)) {
1234 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1235 }
1236 }
1237
1238 /* mulhwu mulhwu. */
1239 static void gen_mulhwu(DisasContext *ctx)
1240 {
1241 TCGv_i32 t0 = tcg_temp_new_i32();
1242 TCGv_i32 t1 = tcg_temp_new_i32();
1243
1244 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1245 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1246 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1247 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1248 tcg_temp_free_i32(t0);
1249 tcg_temp_free_i32(t1);
1250 if (unlikely(Rc(ctx->opcode) != 0)) {
1251 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1252 }
1253 }
1254
1255 /* mullw mullw. */
1256 static void gen_mullw(DisasContext *ctx)
1257 {
1258 #if defined(TARGET_PPC64)
1259 TCGv_i64 t0, t1;
1260 t0 = tcg_temp_new_i64();
1261 t1 = tcg_temp_new_i64();
1262 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1263 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1264 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1265 tcg_temp_free(t0);
1266 tcg_temp_free(t1);
1267 #else
1268 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1269 cpu_gpr[rB(ctx->opcode)]);
1270 #endif
1271 if (unlikely(Rc(ctx->opcode) != 0)) {
1272 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1273 }
1274 }
1275
1276 /* mullwo mullwo. */
1277 static void gen_mullwo(DisasContext *ctx)
1278 {
1279 TCGv_i32 t0 = tcg_temp_new_i32();
1280 TCGv_i32 t1 = tcg_temp_new_i32();
1281
1282 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1283 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1284 tcg_gen_muls2_i32(t0, t1, t0, t1);
1285 #if defined(TARGET_PPC64)
1286 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1287 #else
1288 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1289 #endif
1290
1291 tcg_gen_sari_i32(t0, t0, 31);
1292 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1293 tcg_gen_extu_i32_tl(cpu_ov, t0);
1294 if (is_isa300(ctx)) {
1295 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1296 }
1297 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1298
1299 tcg_temp_free_i32(t0);
1300 tcg_temp_free_i32(t1);
1301 if (unlikely(Rc(ctx->opcode) != 0)) {
1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1303 }
1304 }
1305
1306 /* mulli */
1307 static void gen_mulli(DisasContext *ctx)
1308 {
1309 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1310 SIMM(ctx->opcode));
1311 }
1312
1313 #if defined(TARGET_PPC64)
1314 /* mulhd mulhd. */
1315 static void gen_mulhd(DisasContext *ctx)
1316 {
1317 TCGv lo = tcg_temp_new();
1318 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1319 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1320 tcg_temp_free(lo);
1321 if (unlikely(Rc(ctx->opcode) != 0)) {
1322 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1323 }
1324 }
1325
1326 /* mulhdu mulhdu. */
1327 static void gen_mulhdu(DisasContext *ctx)
1328 {
1329 TCGv lo = tcg_temp_new();
1330 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1331 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1332 tcg_temp_free(lo);
1333 if (unlikely(Rc(ctx->opcode) != 0)) {
1334 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1335 }
1336 }
1337
1338 /* mulld mulld. */
1339 static void gen_mulld(DisasContext *ctx)
1340 {
1341 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1342 cpu_gpr[rB(ctx->opcode)]);
1343 if (unlikely(Rc(ctx->opcode) != 0)) {
1344 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1345 }
1346 }
1347
1348 /* mulldo mulldo. */
1349 static void gen_mulldo(DisasContext *ctx)
1350 {
1351 TCGv_i64 t0 = tcg_temp_new_i64();
1352 TCGv_i64 t1 = tcg_temp_new_i64();
1353
1354 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1355 cpu_gpr[rB(ctx->opcode)]);
1356 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1357
1358 tcg_gen_sari_i64(t0, t0, 63);
1359 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1360 if (is_isa300(ctx)) {
1361 tcg_gen_mov_tl(cpu_ov32, cpu_ov);
1362 }
1363 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1364
1365 tcg_temp_free_i64(t0);
1366 tcg_temp_free_i64(t1);
1367
1368 if (unlikely(Rc(ctx->opcode) != 0)) {
1369 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1370 }
1371 }
1372 #endif
1373
1374 /* Common subf function */
1375 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1376 TCGv arg2, bool add_ca, bool compute_ca,
1377 bool compute_ov, bool compute_rc0)
1378 {
1379 TCGv t0 = ret;
1380
1381 if (compute_ca || compute_ov) {
1382 t0 = tcg_temp_new();
1383 }
1384
1385 if (compute_ca) {
1386 /* dest = ~arg1 + arg2 [+ ca]. */
1387 if (NARROW_MODE(ctx)) {
1388 /*
1389 * Caution: a non-obvious corner case of the spec is that
1390 * we must produce the *entire* 64-bit addition, but
1391 * produce the carry into bit 32.
1392 */
1393 TCGv inv1 = tcg_temp_new();
1394 TCGv t1 = tcg_temp_new();
1395 tcg_gen_not_tl(inv1, arg1);
1396 if (add_ca) {
1397 tcg_gen_add_tl(t0, arg2, cpu_ca);
1398 } else {
1399 tcg_gen_addi_tl(t0, arg2, 1);
1400 }
1401 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1402 tcg_gen_add_tl(t0, t0, inv1);
1403 tcg_temp_free(inv1);
1404 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1405 tcg_temp_free(t1);
1406 tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
1407 if (is_isa300(ctx)) {
1408 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
1409 }
1410 } else if (add_ca) {
1411 TCGv zero, inv1 = tcg_temp_new();
1412 tcg_gen_not_tl(inv1, arg1);
1413 zero = tcg_const_tl(0);
1414 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1415 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1416 gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
1417 tcg_temp_free(zero);
1418 tcg_temp_free(inv1);
1419 } else {
1420 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1421 tcg_gen_sub_tl(t0, arg2, arg1);
1422 gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1);
1423 }
1424 } else if (add_ca) {
1425 /*
1426 * Since we're ignoring carry-out, we can simplify the
1427 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
1428 */
1429 tcg_gen_sub_tl(t0, arg2, arg1);
1430 tcg_gen_add_tl(t0, t0, cpu_ca);
1431 tcg_gen_subi_tl(t0, t0, 1);
1432 } else {
1433 tcg_gen_sub_tl(t0, arg2, arg1);
1434 }
1435
1436 if (compute_ov) {
1437 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1438 }
1439 if (unlikely(compute_rc0)) {
1440 gen_set_Rc0(ctx, t0);
1441 }
1442
1443 if (t0 != ret) {
1444 tcg_gen_mov_tl(ret, t0);
1445 tcg_temp_free(t0);
1446 }
1447 }
1448 /* Sub functions with Two operands functions */
1449 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1450 static void glue(gen_, name)(DisasContext *ctx) \
1451 { \
1452 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1453 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1454 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1455 }
1456 /* Sub functions with one operand and one immediate */
1457 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1458 add_ca, compute_ca, compute_ov) \
1459 static void glue(gen_, name)(DisasContext *ctx) \
1460 { \
1461 TCGv t0 = tcg_const_tl(const_val); \
1462 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1463 cpu_gpr[rA(ctx->opcode)], t0, \
1464 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1465 tcg_temp_free(t0); \
1466 }
1467 /* subf subf. subfo subfo. */
1468 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1469 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1470 /* subfc subfc. subfco subfco. */
1471 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1472 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1473 /* subfe subfe. subfeo subfo. */
1474 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1475 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1476 /* subfme subfme. subfmeo subfmeo. */
1477 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1478 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1479 /* subfze subfze. subfzeo subfzeo.*/
1480 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1481 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1482
1483 /* subfic */
1484 static void gen_subfic(DisasContext *ctx)
1485 {
1486 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1487 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1488 c, 0, 1, 0, 0);
1489 tcg_temp_free(c);
1490 }
1491
1492 /* neg neg. nego nego. */
1493 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1494 {
1495 TCGv zero = tcg_const_tl(0);
1496 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1497 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1498 tcg_temp_free(zero);
1499 }
1500
1501 static void gen_neg(DisasContext *ctx)
1502 {
1503 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1504 if (unlikely(Rc(ctx->opcode))) {
1505 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1506 }
1507 }
1508
1509 static void gen_nego(DisasContext *ctx)
1510 {
1511 gen_op_arith_neg(ctx, 1);
1512 }
1513
1514 /*** Integer logical ***/
1515 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1516 static void glue(gen_, name)(DisasContext *ctx) \
1517 { \
1518 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1519 cpu_gpr[rB(ctx->opcode)]); \
1520 if (unlikely(Rc(ctx->opcode) != 0)) \
1521 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1522 }
1523
1524 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1525 static void glue(gen_, name)(DisasContext *ctx) \
1526 { \
1527 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1528 if (unlikely(Rc(ctx->opcode) != 0)) \
1529 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1530 }
1531
1532 /* and & and. */
1533 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1534 /* andc & andc. */
1535 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1536
1537 /* andi. */
1538 static void gen_andi_(DisasContext *ctx)
1539 {
1540 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1541 UIMM(ctx->opcode));
1542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1543 }
1544
1545 /* andis. */
1546 static void gen_andis_(DisasContext *ctx)
1547 {
1548 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1549 UIMM(ctx->opcode) << 16);
1550 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1551 }
1552
1553 /* cntlzw */
1554 static void gen_cntlzw(DisasContext *ctx)
1555 {
1556 TCGv_i32 t = tcg_temp_new_i32();
1557
1558 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1559 tcg_gen_clzi_i32(t, t, 32);
1560 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1561 tcg_temp_free_i32(t);
1562
1563 if (unlikely(Rc(ctx->opcode) != 0)) {
1564 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1565 }
1566 }
1567
1568 /* cnttzw */
1569 static void gen_cnttzw(DisasContext *ctx)
1570 {
1571 TCGv_i32 t = tcg_temp_new_i32();
1572
1573 tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]);
1574 tcg_gen_ctzi_i32(t, t, 32);
1575 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t);
1576 tcg_temp_free_i32(t);
1577
1578 if (unlikely(Rc(ctx->opcode) != 0)) {
1579 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1580 }
1581 }
1582
1583 /* eqv & eqv. */
1584 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1585 /* extsb & extsb. */
1586 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1587 /* extsh & extsh. */
1588 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1589 /* nand & nand. */
1590 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1591 /* nor & nor. */
1592 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1593
1594 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1595 static void gen_pause(DisasContext *ctx)
1596 {
1597 TCGv_i32 t0 = tcg_const_i32(0);
1598 tcg_gen_st_i32(t0, cpu_env,
1599 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1600 tcg_temp_free_i32(t0);
1601
1602 /* Stop translation, this gives other CPUs a chance to run */
1603 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
1604 }
1605 #endif /* defined(TARGET_PPC64) */
1606
1607 /* or & or. */
1608 static void gen_or(DisasContext *ctx)
1609 {
1610 int rs, ra, rb;
1611
1612 rs = rS(ctx->opcode);
1613 ra = rA(ctx->opcode);
1614 rb = rB(ctx->opcode);
1615 /* Optimisation for mr. ri case */
1616 if (rs != ra || rs != rb) {
1617 if (rs != rb) {
1618 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1619 } else {
1620 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1621 }
1622 if (unlikely(Rc(ctx->opcode) != 0)) {
1623 gen_set_Rc0(ctx, cpu_gpr[ra]);
1624 }
1625 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1626 gen_set_Rc0(ctx, cpu_gpr[rs]);
1627 #if defined(TARGET_PPC64)
1628 } else if (rs != 0) { /* 0 is nop */
1629 int prio = 0;
1630
1631 switch (rs) {
1632 case 1:
1633 /* Set process priority to low */
1634 prio = 2;
1635 break;
1636 case 6:
1637 /* Set process priority to medium-low */
1638 prio = 3;
1639 break;
1640 case 2:
1641 /* Set process priority to normal */
1642 prio = 4;
1643 break;
1644 #if !defined(CONFIG_USER_ONLY)
1645 case 31:
1646 if (!ctx->pr) {
1647 /* Set process priority to very low */
1648 prio = 1;
1649 }
1650 break;
1651 case 5:
1652 if (!ctx->pr) {
1653 /* Set process priority to medium-hight */
1654 prio = 5;
1655 }
1656 break;
1657 case 3:
1658 if (!ctx->pr) {
1659 /* Set process priority to high */
1660 prio = 6;
1661 }
1662 break;
1663 case 7:
1664 if (ctx->hv && !ctx->pr) {
1665 /* Set process priority to very high */
1666 prio = 7;
1667 }
1668 break;
1669 #endif
1670 default:
1671 break;
1672 }
1673 if (prio) {
1674 TCGv t0 = tcg_temp_new();
1675 gen_load_spr(t0, SPR_PPR);
1676 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1677 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1678 gen_store_spr(SPR_PPR, t0);
1679 tcg_temp_free(t0);
1680 }
1681 #if !defined(CONFIG_USER_ONLY)
1682 /*
1683 * Pause out of TCG otherwise spin loops with smt_low eat too
1684 * much CPU and the kernel hangs. This applies to all
1685 * encodings other than no-op, e.g., miso(rs=26), yield(27),
1686 * mdoio(29), mdoom(30), and all currently undefined.
1687 */
1688 gen_pause(ctx);
1689 #endif
1690 #endif
1691 }
1692 }
1693 /* orc & orc. */
1694 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1695
1696 /* xor & xor. */
1697 static void gen_xor(DisasContext *ctx)
1698 {
1699 /* Optimisation for "set to zero" case */
1700 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1701 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1702 cpu_gpr[rB(ctx->opcode)]);
1703 } else {
1704 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1705 }
1706 if (unlikely(Rc(ctx->opcode) != 0)) {
1707 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1708 }
1709 }
1710
1711 /* ori */
1712 static void gen_ori(DisasContext *ctx)
1713 {
1714 target_ulong uimm = UIMM(ctx->opcode);
1715
1716 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1717 return;
1718 }
1719 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1720 }
1721
1722 /* oris */
1723 static void gen_oris(DisasContext *ctx)
1724 {
1725 target_ulong uimm = UIMM(ctx->opcode);
1726
1727 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1728 /* NOP */
1729 return;
1730 }
1731 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1732 uimm << 16);
1733 }
1734
1735 /* xori */
1736 static void gen_xori(DisasContext *ctx)
1737 {
1738 target_ulong uimm = UIMM(ctx->opcode);
1739
1740 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1741 /* NOP */
1742 return;
1743 }
1744 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1745 }
1746
1747 /* xoris */
1748 static void gen_xoris(DisasContext *ctx)
1749 {
1750 target_ulong uimm = UIMM(ctx->opcode);
1751
1752 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1753 /* NOP */
1754 return;
1755 }
1756 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
1757 uimm << 16);
1758 }
1759
1760 /* popcntb : PowerPC 2.03 specification */
1761 static void gen_popcntb(DisasContext *ctx)
1762 {
1763 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1764 }
1765
1766 static void gen_popcntw(DisasContext *ctx)
1767 {
1768 #if defined(TARGET_PPC64)
1769 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1770 #else
1771 tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1772 #endif
1773 }
1774
1775 #if defined(TARGET_PPC64)
1776 /* popcntd: PowerPC 2.06 specification */
1777 static void gen_popcntd(DisasContext *ctx)
1778 {
1779 tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1780 }
1781 #endif
1782
1783 /* prtyw: PowerPC 2.05 specification */
1784 static void gen_prtyw(DisasContext *ctx)
1785 {
1786 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1787 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1788 TCGv t0 = tcg_temp_new();
1789 tcg_gen_shri_tl(t0, rs, 16);
1790 tcg_gen_xor_tl(ra, rs, t0);
1791 tcg_gen_shri_tl(t0, ra, 8);
1792 tcg_gen_xor_tl(ra, ra, t0);
1793 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1794 tcg_temp_free(t0);
1795 }
1796
1797 #if defined(TARGET_PPC64)
1798 /* prtyd: PowerPC 2.05 specification */
1799 static void gen_prtyd(DisasContext *ctx)
1800 {
1801 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1802 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1803 TCGv t0 = tcg_temp_new();
1804 tcg_gen_shri_tl(t0, rs, 32);
1805 tcg_gen_xor_tl(ra, rs, t0);
1806 tcg_gen_shri_tl(t0, ra, 16);
1807 tcg_gen_xor_tl(ra, ra, t0);
1808 tcg_gen_shri_tl(t0, ra, 8);
1809 tcg_gen_xor_tl(ra, ra, t0);
1810 tcg_gen_andi_tl(ra, ra, 1);
1811 tcg_temp_free(t0);
1812 }
1813 #endif
1814
1815 #if defined(TARGET_PPC64)
1816 /* bpermd */
1817 static void gen_bpermd(DisasContext *ctx)
1818 {
1819 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1820 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1821 }
1822 #endif
1823
1824 #if defined(TARGET_PPC64)
1825 /* extsw & extsw. */
1826 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1827
1828 /* cntlzd */
1829 static void gen_cntlzd(DisasContext *ctx)
1830 {
1831 tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1832 if (unlikely(Rc(ctx->opcode) != 0)) {
1833 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1834 }
1835 }
1836
1837 /* cnttzd */
1838 static void gen_cnttzd(DisasContext *ctx)
1839 {
1840 tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64);
1841 if (unlikely(Rc(ctx->opcode) != 0)) {
1842 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1843 }
1844 }
1845
1846 /* darn */
1847 static void gen_darn(DisasContext *ctx)
1848 {
1849 int l = L(ctx->opcode);
1850
1851 if (l > 2) {
1852 tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
1853 } else {
1854 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
1855 gen_io_start();
1856 }
1857 if (l == 0) {
1858 gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
1859 } else {
1860 /* Return 64-bit random for both CRN and RRN */
1861 gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]);
1862 }
1863 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
1864 gen_io_end();
1865 gen_stop_exception(ctx);
1866 }
1867 }
1868 }
1869 #endif
1870
1871 /*** Integer rotate ***/
1872
1873 /* rlwimi & rlwimi. */
1874 static void gen_rlwimi(DisasContext *ctx)
1875 {
1876 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1877 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1878 uint32_t sh = SH(ctx->opcode);
1879 uint32_t mb = MB(ctx->opcode);
1880 uint32_t me = ME(ctx->opcode);
1881
1882 if (sh == (31 - me) && mb <= me) {
1883 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1884 } else {
1885 target_ulong mask;
1886 TCGv t1;
1887
1888 #if defined(TARGET_PPC64)
1889 mb += 32;
1890 me += 32;
1891 #endif
1892 mask = MASK(mb, me);
1893
1894 t1 = tcg_temp_new();
1895 if (mask <= 0xffffffffu) {
1896 TCGv_i32 t0 = tcg_temp_new_i32();
1897 tcg_gen_trunc_tl_i32(t0, t_rs);
1898 tcg_gen_rotli_i32(t0, t0, sh);
1899 tcg_gen_extu_i32_tl(t1, t0);
1900 tcg_temp_free_i32(t0);
1901 } else {
1902 #if defined(TARGET_PPC64)
1903 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1904 tcg_gen_rotli_i64(t1, t1, sh);
1905 #else
1906 g_assert_not_reached();
1907 #endif
1908 }
1909
1910 tcg_gen_andi_tl(t1, t1, mask);
1911 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1912 tcg_gen_or_tl(t_ra, t_ra, t1);
1913 tcg_temp_free(t1);
1914 }
1915 if (unlikely(Rc(ctx->opcode) != 0)) {
1916 gen_set_Rc0(ctx, t_ra);
1917 }
1918 }
1919
1920 /* rlwinm & rlwinm. */
1921 static void gen_rlwinm(DisasContext *ctx)
1922 {
1923 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1924 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1925 int sh = SH(ctx->opcode);
1926 int mb = MB(ctx->opcode);
1927 int me = ME(ctx->opcode);
1928 int len = me - mb + 1;
1929 int rsh = (32 - sh) & 31;
1930
1931 if (sh != 0 && len > 0 && me == (31 - sh)) {
1932 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
1933 } else if (me == 31 && rsh + len <= 32) {
1934 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
1935 } else {
1936 target_ulong mask;
1937 #if defined(TARGET_PPC64)
1938 mb += 32;
1939 me += 32;
1940 #endif
1941 mask = MASK(mb, me);
1942 if (sh == 0) {
1943 tcg_gen_andi_tl(t_ra, t_rs, mask);
1944 } else if (mask <= 0xffffffffu) {
1945 TCGv_i32 t0 = tcg_temp_new_i32();
1946 tcg_gen_trunc_tl_i32(t0, t_rs);
1947 tcg_gen_rotli_i32(t0, t0, sh);
1948 tcg_gen_andi_i32(t0, t0, mask);
1949 tcg_gen_extu_i32_tl(t_ra, t0);
1950 tcg_temp_free_i32(t0);
1951 } else {
1952 #if defined(TARGET_PPC64)
1953 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1954 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1955 tcg_gen_andi_i64(t_ra, t_ra, mask);
1956 #else
1957 g_assert_not_reached();
1958 #endif
1959 }
1960 }
1961 if (unlikely(Rc(ctx->opcode) != 0)) {
1962 gen_set_Rc0(ctx, t_ra);
1963 }
1964 }
1965
1966 /* rlwnm & rlwnm. */
1967 static void gen_rlwnm(DisasContext *ctx)
1968 {
1969 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1970 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1971 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1972 uint32_t mb = MB(ctx->opcode);
1973 uint32_t me = ME(ctx->opcode);
1974 target_ulong mask;
1975
1976 #if defined(TARGET_PPC64)
1977 mb += 32;
1978 me += 32;
1979 #endif
1980 mask = MASK(mb, me);
1981
1982 if (mask <= 0xffffffffu) {
1983 TCGv_i32 t0 = tcg_temp_new_i32();
1984 TCGv_i32 t1 = tcg_temp_new_i32();
1985 tcg_gen_trunc_tl_i32(t0, t_rb);
1986 tcg_gen_trunc_tl_i32(t1, t_rs);
1987 tcg_gen_andi_i32(t0, t0, 0x1f);
1988 tcg_gen_rotl_i32(t1, t1, t0);
1989 tcg_gen_extu_i32_tl(t_ra, t1);
1990 tcg_temp_free_i32(t0);
1991 tcg_temp_free_i32(t1);
1992 } else {
1993 #if defined(TARGET_PPC64)
1994 TCGv_i64 t0 = tcg_temp_new_i64();
1995 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1996 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1997 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1998 tcg_temp_free_i64(t0);
1999 #else
2000 g_assert_not_reached();
2001 #endif
2002 }
2003
2004 tcg_gen_andi_tl(t_ra, t_ra, mask);
2005
2006 if (unlikely(Rc(ctx->opcode) != 0)) {
2007 gen_set_Rc0(ctx, t_ra);
2008 }
2009 }
2010
2011 #if defined(TARGET_PPC64)
2012 #define GEN_PPC64_R2(name, opc1, opc2) \
2013 static void glue(gen_, name##0)(DisasContext *ctx) \
2014 { \
2015 gen_##name(ctx, 0); \
2016 } \
2017 \
2018 static void glue(gen_, name##1)(DisasContext *ctx) \
2019 { \
2020 gen_##name(ctx, 1); \
2021 }
2022 #define GEN_PPC64_R4(name, opc1, opc2) \
2023 static void glue(gen_, name##0)(DisasContext *ctx) \
2024 { \
2025 gen_##name(ctx, 0, 0); \
2026 } \
2027 \
2028 static void glue(gen_, name##1)(DisasContext *ctx) \
2029 { \
2030 gen_##name(ctx, 0, 1); \
2031 } \
2032 \
2033 static void glue(gen_, name##2)(DisasContext *ctx) \
2034 { \
2035 gen_##name(ctx, 1, 0); \
2036 } \
2037 \
2038 static void glue(gen_, name##3)(DisasContext *ctx) \
2039 { \
2040 gen_##name(ctx, 1, 1); \
2041 }
2042
2043 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2044 {
2045 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2046 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2047 int len = me - mb + 1;
2048 int rsh = (64 - sh) & 63;
2049
2050 if (sh != 0 && len > 0 && me == (63 - sh)) {
2051 tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len);
2052 } else if (me == 63 && rsh + len <= 64) {
2053 tcg_gen_extract_tl(t_ra, t_rs, rsh, len);
2054 } else {
2055 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2056 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2057 }
2058 if (unlikely(Rc(ctx->opcode) != 0)) {
2059 gen_set_Rc0(ctx, t_ra);
2060 }
2061 }
2062
2063 /* rldicl - rldicl. */
2064 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2065 {
2066 uint32_t sh, mb;
2067
2068 sh = SH(ctx->opcode) | (shn << 5);
2069 mb = MB(ctx->opcode) | (mbn << 5);
2070 gen_rldinm(ctx, mb, 63, sh);
2071 }
2072 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2073
2074 /* rldicr - rldicr. */
2075 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2076 {
2077 uint32_t sh, me;
2078
2079 sh = SH(ctx->opcode) | (shn << 5);
2080 me = MB(ctx->opcode) | (men << 5);
2081 gen_rldinm(ctx, 0, me, sh);
2082 }
2083 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2084
2085 /* rldic - rldic. */
2086 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2087 {
2088 uint32_t sh, mb;
2089
2090 sh = SH(ctx->opcode) | (shn << 5);
2091 mb = MB(ctx->opcode) | (mbn << 5);
2092 gen_rldinm(ctx, mb, 63 - sh, sh);
2093 }
2094 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2095
2096 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2097 {
2098 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2099 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2100 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2101 TCGv t0;
2102
2103 t0 = tcg_temp_new();
2104 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2105 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2106 tcg_temp_free(t0);
2107
2108 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2109 if (unlikely(Rc(ctx->opcode) != 0)) {
2110 gen_set_Rc0(ctx, t_ra);
2111 }
2112 }
2113
2114 /* rldcl - rldcl. */
2115 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2116 {
2117 uint32_t mb;
2118
2119 mb = MB(ctx->opcode) | (mbn << 5);
2120 gen_rldnm(ctx, mb, 63);
2121 }
2122 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2123
2124 /* rldcr - rldcr. */
2125 static inline void gen_rldcr(DisasContext *ctx, int men)
2126 {
2127 uint32_t me;
2128
2129 me = MB(ctx->opcode) | (men << 5);
2130 gen_rldnm(ctx, 0, me);
2131 }
2132 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2133
2134 /* rldimi - rldimi. */
2135 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2136 {
2137 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2138 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2139 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2140 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2141 uint32_t me = 63 - sh;
2142
2143 if (mb <= me) {
2144 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2145 } else {
2146 target_ulong mask = MASK(mb, me);
2147 TCGv t1 = tcg_temp_new();
2148
2149 tcg_gen_rotli_tl(t1, t_rs, sh);
2150 tcg_gen_andi_tl(t1, t1, mask);
2151 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2152 tcg_gen_or_tl(t_ra, t_ra, t1);
2153 tcg_temp_free(t1);
2154 }
2155 if (unlikely(Rc(ctx->opcode) != 0)) {
2156 gen_set_Rc0(ctx, t_ra);
2157 }
2158 }
2159 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2160 #endif
2161
2162 /*** Integer shift ***/
2163
2164 /* slw & slw. */
2165 static void gen_slw(DisasContext *ctx)
2166 {
2167 TCGv t0, t1;
2168
2169 t0 = tcg_temp_new();
2170 /* AND rS with a mask that is 0 when rB >= 0x20 */
2171 #if defined(TARGET_PPC64)
2172 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2173 tcg_gen_sari_tl(t0, t0, 0x3f);
2174 #else
2175 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2176 tcg_gen_sari_tl(t0, t0, 0x1f);
2177 #endif
2178 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2179 t1 = tcg_temp_new();
2180 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2181 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2182 tcg_temp_free(t1);
2183 tcg_temp_free(t0);
2184 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2185 if (unlikely(Rc(ctx->opcode) != 0)) {
2186 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2187 }
2188 }
2189
2190 /* sraw & sraw. */
2191 static void gen_sraw(DisasContext *ctx)
2192 {
2193 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2194 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2195 if (unlikely(Rc(ctx->opcode) != 0)) {
2196 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2197 }
2198 }
2199
2200 /* srawi & srawi. */
2201 static void gen_srawi(DisasContext *ctx)
2202 {
2203 int sh = SH(ctx->opcode);
2204 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2205 TCGv src = cpu_gpr[rS(ctx->opcode)];
2206 if (sh == 0) {
2207 tcg_gen_ext32s_tl(dst, src);
2208 tcg_gen_movi_tl(cpu_ca, 0);
2209 if (is_isa300(ctx)) {
2210 tcg_gen_movi_tl(cpu_ca32, 0);
2211 }
2212 } else {
2213 TCGv t0;
2214 tcg_gen_ext32s_tl(dst, src);
2215 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2216 t0 = tcg_temp_new();
2217 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2218 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2219 tcg_temp_free(t0);
2220 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2221 if (is_isa300(ctx)) {
2222 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2223 }
2224 tcg_gen_sari_tl(dst, dst, sh);
2225 }
2226 if (unlikely(Rc(ctx->opcode) != 0)) {
2227 gen_set_Rc0(ctx, dst);
2228 }
2229 }
2230
2231 /* srw & srw. */
2232 static void gen_srw(DisasContext *ctx)
2233 {
2234 TCGv t0, t1;
2235
2236 t0 = tcg_temp_new();
2237 /* AND rS with a mask that is 0 when rB >= 0x20 */
2238 #if defined(TARGET_PPC64)
2239 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2240 tcg_gen_sari_tl(t0, t0, 0x3f);
2241 #else
2242 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2243 tcg_gen_sari_tl(t0, t0, 0x1f);
2244 #endif
2245 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2246 tcg_gen_ext32u_tl(t0, t0);
2247 t1 = tcg_temp_new();
2248 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2249 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2250 tcg_temp_free(t1);
2251 tcg_temp_free(t0);
2252 if (unlikely(Rc(ctx->opcode) != 0)) {
2253 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2254 }
2255 }
2256
2257 #if defined(TARGET_PPC64)
2258 /* sld & sld. */
2259 static void gen_sld(DisasContext *ctx)
2260 {
2261 TCGv t0, t1;
2262
2263 t0 = tcg_temp_new();
2264 /* AND rS with a mask that is 0 when rB >= 0x40 */
2265 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2266 tcg_gen_sari_tl(t0, t0, 0x3f);
2267 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2268 t1 = tcg_temp_new();
2269 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2270 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2271 tcg_temp_free(t1);
2272 tcg_temp_free(t0);
2273 if (unlikely(Rc(ctx->opcode) != 0)) {
2274 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2275 }
2276 }
2277
2278 /* srad & srad. */
2279 static void gen_srad(DisasContext *ctx)
2280 {
2281 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2282 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2283 if (unlikely(Rc(ctx->opcode) != 0)) {
2284 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2285 }
2286 }
2287 /* sradi & sradi. */
2288 static inline void gen_sradi(DisasContext *ctx, int n)
2289 {
2290 int sh = SH(ctx->opcode) + (n << 5);
2291 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2292 TCGv src = cpu_gpr[rS(ctx->opcode)];
2293 if (sh == 0) {
2294 tcg_gen_mov_tl(dst, src);
2295 tcg_gen_movi_tl(cpu_ca, 0);
2296 if (is_isa300(ctx)) {
2297 tcg_gen_movi_tl(cpu_ca32, 0);
2298 }
2299 } else {
2300 TCGv t0;
2301 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2302 t0 = tcg_temp_new();
2303 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2304 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2305 tcg_temp_free(t0);
2306 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2307 if (is_isa300(ctx)) {
2308 tcg_gen_mov_tl(cpu_ca32, cpu_ca);
2309 }
2310 tcg_gen_sari_tl(dst, src, sh);
2311 }
2312 if (unlikely(Rc(ctx->opcode) != 0)) {
2313 gen_set_Rc0(ctx, dst);
2314 }
2315 }
2316
2317 static void gen_sradi0(DisasContext *ctx)
2318 {
2319 gen_sradi(ctx, 0);
2320 }
2321
2322 static void gen_sradi1(DisasContext *ctx)
2323 {
2324 gen_sradi(ctx, 1);
2325 }
2326
2327 /* extswsli & extswsli. */
2328 static inline void gen_extswsli(DisasContext *ctx, int n)
2329 {
2330 int sh = SH(ctx->opcode) + (n << 5);
2331 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2332 TCGv src = cpu_gpr[rS(ctx->opcode)];
2333
2334 tcg_gen_ext32s_tl(dst, src);
2335 tcg_gen_shli_tl(dst, dst, sh);
2336 if (unlikely(Rc(ctx->opcode) != 0)) {
2337 gen_set_Rc0(ctx, dst);
2338 }
2339 }
2340
2341 static void gen_extswsli0(DisasContext *ctx)
2342 {
2343 gen_extswsli(ctx, 0);
2344 }
2345
2346 static void gen_extswsli1(DisasContext *ctx)
2347 {
2348 gen_extswsli(ctx, 1);
2349 }
2350
2351 /* srd & srd. */
2352 static void gen_srd(DisasContext *ctx)
2353 {
2354 TCGv t0, t1;
2355
2356 t0 = tcg_temp_new();
2357 /* AND rS with a mask that is 0 when rB >= 0x40 */
2358 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2359 tcg_gen_sari_tl(t0, t0, 0x3f);
2360 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2361 t1 = tcg_temp_new();
2362 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2363 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2364 tcg_temp_free(t1);
2365 tcg_temp_free(t0);
2366 if (unlikely(Rc(ctx->opcode) != 0)) {
2367 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2368 }
2369 }
2370 #endif
2371
2372 /*** Addressing modes ***/
2373 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2374 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2375 target_long maskl)
2376 {
2377 target_long simm = SIMM(ctx->opcode);
2378
2379 simm &= ~maskl;
2380 if (rA(ctx->opcode) == 0) {
2381 if (NARROW_MODE(ctx)) {
2382 simm = (uint32_t)simm;
2383 }
2384 tcg_gen_movi_tl(EA, simm);
2385 } else if (likely(simm != 0)) {
2386 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2387 if (NARROW_MODE(ctx)) {
2388 tcg_gen_ext32u_tl(EA, EA);
2389 }
2390 } else {
2391 if (NARROW_MODE(ctx)) {
2392 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2393 } else {
2394 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2395 }
2396 }
2397 }
2398
2399 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2400 {
2401 if (rA(ctx->opcode) == 0) {
2402 if (NARROW_MODE(ctx)) {
2403 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2404 } else {
2405 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2406 }
2407 } else {
2408 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2409 if (NARROW_MODE(ctx)) {
2410 tcg_gen_ext32u_tl(EA, EA);
2411 }
2412 }
2413 }
2414
2415 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2416 {
2417 if (rA(ctx->opcode) == 0) {
2418 tcg_gen_movi_tl(EA, 0);
2419 } else if (NARROW_MODE(ctx)) {
2420 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2421 } else {
2422 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2423 }
2424 }
2425
2426 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2427 target_long val)
2428 {
2429 tcg_gen_addi_tl(ret, arg1, val);
2430 if (NARROW_MODE(ctx)) {
2431 tcg_gen_ext32u_tl(ret, ret);
2432 }
2433 }
2434
2435 static inline void gen_align_no_le(DisasContext *ctx)
2436 {
2437 gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
2438 (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
2439 }
2440
2441 /*** Integer load ***/
2442 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2443 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2444
2445 #define GEN_QEMU_LOAD_TL(ldop, op) \
2446 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2447 TCGv val, \
2448 TCGv addr) \
2449 { \
2450 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2451 }
2452
2453 GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB))
2454 GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW))
2455 GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW))
2456 GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL))
2457 GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL))
2458
2459 GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW))
2460 GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL))
2461
2462 #define GEN_QEMU_LOAD_64(ldop, op) \
2463 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2464 TCGv_i64 val, \
2465 TCGv addr) \
2466 { \
2467 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2468 }
2469
2470 GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB))
2471 GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW))
2472 GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
2473 GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
2474 GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
2475
2476 #if defined(TARGET_PPC64)
2477 GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
2478 #endif
2479
2480 #define GEN_QEMU_STORE_TL(stop, op) \
2481 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2482 TCGv val, \
2483 TCGv addr) \
2484 { \
2485 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2486 }
2487
2488 GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
2489 GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
2490 GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
2491
2492 GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW))
2493 GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL))
2494
2495 #define GEN_QEMU_STORE_64(stop, op) \
2496 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2497 TCGv_i64 val, \
2498 TCGv addr) \
2499 { \
2500 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2501 }
2502
2503 GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB))
2504 GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW))
2505 GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
2506 GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q))
2507
2508 #if defined(TARGET_PPC64)
2509 GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q))
2510 #endif
2511
2512 #define GEN_LD(name, ldop, opc, type) \
2513 static void glue(gen_, name)(DisasContext *ctx) \
2514 { \
2515 TCGv EA; \
2516 gen_set_access_type(ctx, ACCESS_INT); \
2517 EA = tcg_temp_new(); \
2518 gen_addr_imm_index(ctx, EA, 0); \
2519 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2520 tcg_temp_free(EA); \
2521 }
2522
2523 #define GEN_LDU(name, ldop, opc, type) \
2524 static void glue(gen_, name##u)(DisasContext *ctx) \
2525 { \
2526 TCGv EA; \
2527 if (unlikely(rA(ctx->opcode) == 0 || \
2528 rA(ctx->opcode) == rD(ctx->opcode))) { \
2529 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2530 return; \
2531 } \
2532 gen_set_access_type(ctx, ACCESS_INT); \
2533 EA = tcg_temp_new(); \
2534 if (type == PPC_64B) \
2535 gen_addr_imm_index(ctx, EA, 0x03); \
2536 else \
2537 gen_addr_imm_index(ctx, EA, 0); \
2538 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2539 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2540 tcg_temp_free(EA); \
2541 }
2542
2543 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2544 static void glue(gen_, name##ux)(DisasContext *ctx) \
2545 { \
2546 TCGv EA; \
2547 if (unlikely(rA(ctx->opcode) == 0 || \
2548 rA(ctx->opcode) == rD(ctx->opcode))) { \
2549 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2550 return; \
2551 } \
2552 gen_set_access_type(ctx, ACCESS_INT); \
2553 EA = tcg_temp_new(); \
2554 gen_addr_reg_index(ctx, EA); \
2555 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2556 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2557 tcg_temp_free(EA); \
2558 }
2559
2560 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2561 static void glue(gen_, name##x)(DisasContext *ctx) \
2562 { \
2563 TCGv EA; \
2564 chk; \
2565 gen_set_access_type(ctx, ACCESS_INT); \
2566 EA = tcg_temp_new(); \
2567 gen_addr_reg_index(ctx, EA); \
2568 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2569 tcg_temp_free(EA); \
2570 }
2571
2572 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2573 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2574
2575 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2576 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2577
2578 #define GEN_LDS(name, ldop, op, type) \
2579 GEN_LD(name, ldop, op | 0x20, type); \
2580 GEN_LDU(name, ldop, op | 0x21, type); \
2581 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2582 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2583
2584 /* lbz lbzu lbzux lbzx */
2585 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2586 /* lha lhau lhaux lhax */
2587 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2588 /* lhz lhzu lhzux lhzx */
2589 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2590 /* lwz lwzu lwzux lwzx */
2591 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2592
2593 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2594 static void glue(gen_, name##epx)(DisasContext *ctx) \
2595 { \
2596 TCGv EA; \
2597 CHK_SV; \
2598 gen_set_access_type(ctx, ACCESS_INT); \
2599 EA = tcg_temp_new(); \
2600 gen_addr_reg_index(ctx, EA); \
2601 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2602 tcg_temp_free(EA); \
2603 }
2604
2605 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
2606 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
2607 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
2608 #if defined(TARGET_PPC64)
2609 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
2610 #endif
2611
2612 #if defined(TARGET_PPC64)
2613 /* lwaux */
2614 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2615 /* lwax */
2616 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2617 /* ldux */
2618 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
2619 /* ldx */
2620 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
2621
2622 /* CI load/store variants */
2623 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
2624 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2625 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2626 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2627
2628 static void gen_ld(DisasContext *ctx)
2629 {
2630 TCGv EA;
2631 if (Rc(ctx->opcode)) {
2632 if (unlikely(rA(ctx->opcode) == 0 ||
2633 rA(ctx->opcode) == rD(ctx->opcode))) {
2634 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2635 return;
2636 }
2637 }
2638 gen_set_access_type(ctx, ACCESS_INT);
2639 EA = tcg_temp_new();
2640 gen_addr_imm_index(ctx, EA, 0x03);
2641 if (ctx->opcode & 0x02) {
2642 /* lwa (lwau is undefined) */
2643 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2644 } else {
2645 /* ld - ldu */
2646 gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2647 }
2648 if (Rc(ctx->opcode)) {
2649 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2650 }
2651 tcg_temp_free(EA);
2652 }
2653
2654 /* lq */
2655 static void gen_lq(DisasContext *ctx)
2656 {
2657 int ra, rd;
2658 TCGv EA, hi, lo;
2659
2660 /* lq is a legal user mode instruction starting in ISA 2.07 */
2661 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2662 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2663
2664 if (!legal_in_user_mode && ctx->pr) {
2665 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2666 return;
2667 }
2668
2669 if (!le_is_supported && ctx->le_mode) {
2670 gen_align_no_le(ctx);
2671 return;
2672 }
2673 ra = rA(ctx->opcode);
2674 rd = rD(ctx->opcode);
2675 if (unlikely((rd & 1) || rd == ra)) {
2676 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2677 return;
2678 }
2679
2680 gen_set_access_type(ctx, ACCESS_INT);
2681 EA = tcg_temp_new();
2682 gen_addr_imm_index(ctx, EA, 0x0F);
2683
2684 /* Note that the low part is always in RD+1, even in LE mode. */
2685 lo = cpu_gpr[rd + 1];
2686 hi = cpu_gpr[rd];
2687
2688 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2689 if (HAVE_ATOMIC128) {
2690 TCGv_i32 oi = tcg_temp_new_i32();
2691 if (ctx->le_mode) {
2692 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2693 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
2694 } else {
2695 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2696 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
2697 }
2698 tcg_temp_free_i32(oi);
2699 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
2700 } else {
2701 /* Restart with exclusive lock. */
2702 gen_helper_exit_atomic(cpu_env);
2703 ctx->base.is_jmp = DISAS_NORETURN;
2704 }
2705 } else if (ctx->le_mode) {
2706 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2707 gen_addr_add(ctx, EA, EA, 8);
2708 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2709 } else {
2710 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2711 gen_addr_add(ctx, EA, EA, 8);
2712 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2713 }
2714 tcg_temp_free(EA);
2715 }
2716 #endif
2717
2718 /*** Integer store ***/
2719 #define GEN_ST(name, stop, opc, type) \
2720 static void glue(gen_, name)(DisasContext *ctx) \
2721 { \
2722 TCGv EA; \
2723 gen_set_access_type(ctx, ACCESS_INT); \
2724 EA = tcg_temp_new(); \
2725 gen_addr_imm_index(ctx, EA, 0); \
2726 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2727 tcg_temp_free(EA); \
2728 }
2729
2730 #define GEN_STU(name, stop, opc, type) \
2731 static void glue(gen_, stop##u)(DisasContext *ctx) \
2732 { \
2733 TCGv EA; \
2734 if (unlikely(rA(ctx->opcode) == 0)) { \
2735 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2736 return; \
2737 } \
2738 gen_set_access_type(ctx, ACCESS_INT); \
2739 EA = tcg_temp_new(); \
2740 if (type == PPC_64B) \
2741 gen_addr_imm_index(ctx, EA, 0x03); \
2742 else \
2743 gen_addr_imm_index(ctx, EA, 0); \
2744 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2745 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2746 tcg_temp_free(EA); \
2747 }
2748
2749 #define GEN_STUX(name, stop, opc2, opc3, type) \
2750 static void glue(gen_, name##ux)(DisasContext *ctx) \
2751 { \
2752 TCGv EA; \
2753 if (unlikely(rA(ctx->opcode) == 0)) { \
2754 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2755 return; \
2756 } \
2757 gen_set_access_type(ctx, ACCESS_INT); \
2758 EA = tcg_temp_new(); \
2759 gen_addr_reg_index(ctx, EA); \
2760 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2762 tcg_temp_free(EA); \
2763 }
2764
2765 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2766 static void glue(gen_, name##x)(DisasContext *ctx) \
2767 { \
2768 TCGv EA; \
2769 chk; \
2770 gen_set_access_type(ctx, ACCESS_INT); \
2771 EA = tcg_temp_new(); \
2772 gen_addr_reg_index(ctx, EA); \
2773 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2774 tcg_temp_free(EA); \
2775 }
2776 #define GEN_STX(name, stop, opc2, opc3, type) \
2777 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2778
2779 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2780 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2781
2782 #define GEN_STS(name, stop, op, type) \
2783 GEN_ST(name, stop, op | 0x20, type); \
2784 GEN_STU(name, stop, op | 0x21, type); \
2785 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2786 GEN_STX(name, stop, 0x17, op | 0x00, type)
2787
2788 /* stb stbu stbux stbx */
2789 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2790 /* sth sthu sthux sthx */
2791 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2792 /* stw stwu stwux stwx */
2793 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2794
2795 #define GEN_STEPX(name, stop, opc2, opc3) \
2796 static void glue(gen_, name##epx)(DisasContext *ctx) \
2797 { \
2798 TCGv EA; \
2799 CHK_SV; \
2800 gen_set_access_type(ctx, ACCESS_INT); \
2801 EA = tcg_temp_new(); \
2802 gen_addr_reg_index(ctx, EA); \
2803 tcg_gen_qemu_st_tl( \
2804 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2805 tcg_temp_free(EA); \
2806 }
2807
2808 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
2809 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
2810 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
2811 #if defined(TARGET_PPC64)
2812 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04)
2813 #endif
2814
2815 #if defined(TARGET_PPC64)
2816 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B);
2817 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B);
2818 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
2819 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2820 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2821 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2822
2823 static void gen_std(DisasContext *ctx)
2824 {
2825 int rs;
2826 TCGv EA;
2827
2828 rs = rS(ctx->opcode);
2829 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2830 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2831 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2832 TCGv hi, lo;
2833
2834 if (!(ctx->insns_flags & PPC_64BX)) {
2835 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2836 }
2837
2838 if (!legal_in_user_mode && ctx->pr) {
2839 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2840 return;
2841 }
2842
2843 if (!le_is_supported && ctx->le_mode) {
2844 gen_align_no_le(ctx);
2845 return;
2846 }
2847
2848 if (unlikely(rs & 1)) {
2849 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2850 return;
2851 }
2852 gen_set_access_type(ctx, ACCESS_INT);
2853 EA = tcg_temp_new();
2854 gen_addr_imm_index(ctx, EA, 0x03);
2855
2856 /* Note that the low part is always in RS+1, even in LE mode. */
2857 lo = cpu_gpr[rs + 1];
2858 hi = cpu_gpr[rs];
2859
2860 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
2861 if (HAVE_ATOMIC128) {
2862 TCGv_i32 oi = tcg_temp_new_i32();
2863 if (ctx->le_mode) {
2864 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx));
2865 gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi);
2866 } else {
2867 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx));
2868 gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi);
2869 }
2870 tcg_temp_free_i32(oi);
2871 } else {
2872 /* Restart with exclusive lock. */
2873 gen_helper_exit_atomic(cpu_env);
2874 ctx->base.is_jmp = DISAS_NORETURN;
2875 }
2876 } else if (ctx->le_mode) {
2877 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ);
2878 gen_addr_add(ctx, EA, EA, 8);
2879 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ);
2880 } else {
2881 tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ);
2882 gen_addr_add(ctx, EA, EA, 8);
2883 tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ);
2884 }
2885 tcg_temp_free(EA);
2886 } else {
2887 /* std / stdu */
2888 if (Rc(ctx->opcode)) {
2889 if (unlikely(rA(ctx->opcode) == 0)) {
2890 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2891 return;
2892 }
2893 }
2894 gen_set_access_type(ctx, ACCESS_INT);
2895 EA = tcg_temp_new();
2896 gen_addr_imm_index(ctx, EA, 0x03);
2897 gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA);
2898 if (Rc(ctx->opcode)) {
2899 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2900 }
2901 tcg_temp_free(EA);
2902 }
2903 }
2904 #endif
2905 /*** Integer load and store with byte reverse ***/
2906
2907 /* lhbrx */
2908 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2909
2910 /* lwbrx */
2911 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2912
2913 #if defined(TARGET_PPC64)
2914 /* ldbrx */
2915 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2916 /* stdbrx */
2917 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2918 #endif /* TARGET_PPC64 */
2919
2920 /* sthbrx */
2921 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2922 /* stwbrx */
2923 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2924
2925 /*** Integer load and store multiple ***/
2926
2927 /* lmw */
2928 static void gen_lmw(DisasContext *ctx)
2929 {
2930 TCGv t0;
2931 TCGv_i32 t1;
2932
2933 if (ctx->le_mode) {
2934 gen_align_no_le(ctx);
2935 return;
2936 }
2937 gen_set_access_type(ctx, ACCESS_INT);
2938 t0 = tcg_temp_new();
2939 t1 = tcg_const_i32(rD(ctx->opcode));
2940 gen_addr_imm_index(ctx, t0, 0);
2941 gen_helper_lmw(cpu_env, t0, t1);
2942 tcg_temp_free(t0);
2943 tcg_temp_free_i32(t1);
2944 }
2945
2946 /* stmw */
2947 static void gen_stmw(DisasContext *ctx)
2948 {
2949 TCGv t0;
2950 TCGv_i32 t1;
2951
2952 if (ctx->le_mode) {
2953 gen_align_no_le(ctx);
2954 return;
2955 }
2956 gen_set_access_type(ctx, ACCESS_INT);
2957 t0 = tcg_temp_new();
2958 t1 = tcg_const_i32(rS(ctx->opcode));
2959 gen_addr_imm_index(ctx, t0, 0);
2960 gen_helper_stmw(cpu_env, t0, t1);
2961 tcg_temp_free(t0);
2962 tcg_temp_free_i32(t1);
2963 }
2964
2965 /*** Integer load and store strings ***/
2966
2967 /* lswi */
2968 /*
2969 * PowerPC32 specification says we must generate an exception if rA is
2970 * in the range of registers to be loaded. In an other hand, IBM says
2971 * this is valid, but rA won't be loaded. For now, I'll follow the
2972 * spec...
2973 */
2974 static void gen_lswi(DisasContext *ctx)
2975 {
2976 TCGv t0;
2977 TCGv_i32 t1, t2;
2978 int nb = NB(ctx->opcode);
2979 int start = rD(ctx->opcode);
2980 int ra = rA(ctx->opcode);
2981 int nr;
2982
2983 if (ctx->le_mode) {
2984 gen_align_no_le(ctx);
2985 return;
2986 }
2987 if (nb == 0) {
2988 nb = 32;
2989 }
2990 nr = DIV_ROUND_UP(nb, 4);
2991 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2992 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2993 return;
2994 }
2995 gen_set_access_type(ctx, ACCESS_INT);
2996 t0 = tcg_temp_new();
2997 gen_addr_register(ctx, t0);
2998 t1 = tcg_const_i32(nb);
2999 t2 = tcg_const_i32(start);
3000 gen_helper_lsw(cpu_env, t0, t1, t2);
3001 tcg_temp_free(t0);
3002 tcg_temp_free_i32(t1);
3003 tcg_temp_free_i32(t2);
3004 }
3005
3006 /* lswx */
3007 static void gen_lswx(DisasContext *ctx)
3008 {
3009 TCGv t0;
3010 TCGv_i32 t1, t2, t3;
3011
3012 if (ctx->le_mode) {
3013 gen_align_no_le(ctx);
3014 return;
3015 }
3016 gen_set_access_type(ctx, ACCESS_INT);
3017 t0 = tcg_temp_new();
3018 gen_addr_reg_index(ctx, t0);
3019 t1 = tcg_const_i32(rD(ctx->opcode));
3020 t2 = tcg_const_i32(rA(ctx->opcode));
3021 t3 = tcg_const_i32(rB(ctx->opcode));
3022 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3023 tcg_temp_free(t0);
3024 tcg_temp_free_i32(t1);
3025 tcg_temp_free_i32(t2);
3026 tcg_temp_free_i32(t3);
3027 }
3028
3029 /* stswi */
3030 static void gen_stswi(DisasContext *ctx)
3031 {
3032 TCGv t0;
3033 TCGv_i32 t1, t2;
3034 int nb = NB(ctx->opcode);
3035
3036 if (ctx->le_mode) {
3037 gen_align_no_le(ctx);
3038 return;
3039 }
3040 gen_set_access_type(ctx, ACCESS_INT);
3041 t0 = tcg_temp_new();
3042 gen_addr_register(ctx, t0);
3043 if (nb == 0) {
3044 nb = 32;
3045 }
3046 t1 = tcg_const_i32(nb);
3047 t2 = tcg_const_i32(rS(ctx->opcode));
3048 gen_helper_stsw(cpu_env, t0, t1, t2);
3049 tcg_temp_free(t0);
3050 tcg_temp_free_i32(t1);
3051 tcg_temp_free_i32(t2);
3052 }
3053
3054 /* stswx */
3055 static void gen_stswx(DisasContext *ctx)
3056 {
3057 TCGv t0;
3058 TCGv_i32 t1, t2;
3059
3060 if (ctx->le_mode) {
3061 gen_align_no_le(ctx);
3062 return;
3063 }
3064 gen_set_access_type(ctx, ACCESS_INT);
3065 t0 = tcg_temp_new();
3066 gen_addr_reg_index(ctx, t0);
3067 t1 = tcg_temp_new_i32();
3068 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3069 tcg_gen_andi_i32(t1, t1, 0x7F);
3070 t2 = tcg_const_i32(rS(ctx->opcode));
3071 gen_helper_stsw(cpu_env, t0, t1, t2);
3072 tcg_temp_free(t0);
3073 tcg_temp_free_i32(t1);
3074 tcg_temp_free_i32(t2);
3075 }
3076
3077 /*** Memory synchronisation ***/
3078 /* eieio */
3079 static void gen_eieio(DisasContext *ctx)
3080 {
3081 TCGBar bar = TCG_MO_LD_ST;
3082
3083 /*
3084 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3085 * tell the CPU it is a store-forwarding barrier.
3086 */
3087 if (ctx->opcode & 0x2000000) {
3088 /*
3089 * ISA says that "Reserved fields in instructions are ignored
3090 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3091 * as this is not an instruction software should be using,
3092 * complain to the user.
3093 */
3094 if (!(ctx->insns_flags2 & PPC2_ISA300)) {
3095 qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
3096 TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
3097 } else {
3098 bar = TCG_MO_ST_LD;
3099 }
3100 }
3101
3102 tcg_gen_mb(bar | TCG_BAR_SC);
3103 }
3104
3105 #if !defined(CONFIG_USER_ONLY)
3106 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global)
3107 {
3108 TCGv_i32 t;
3109 TCGLabel *l;
3110
3111 if (!ctx->lazy_tlb_flush) {
3112 return;
3113 }
3114 l = gen_new_label();
3115 t = tcg_temp_new_i32();
3116 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3117 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3118 if (global) {
3119 gen_helper_check_tlb_flush_global(cpu_env);
3120 } else {
3121 gen_helper_check_tlb_flush_local(cpu_env);
3122 }
3123 gen_set_label(l);
3124 tcg_temp_free_i32(t);
3125 }
3126 #else
3127 static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { }
3128 #endif
3129
3130 /* isync */
3131 static void gen_isync(DisasContext *ctx)
3132 {
3133 /*
3134 * We need to check for a pending TLB flush. This can only happen in
3135 * kernel mode however so check MSR_PR
3136 */
3137 if (!ctx->pr) {
3138 gen_check_tlb_flush(ctx, false);
3139 }
3140 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3141 gen_stop_exception(ctx);
3142 }
3143
3144 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3145
3146 static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
3147 {
3148 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3149 TCGv t0 = tcg_temp_new();
3150
3151 gen_set_access_type(ctx, ACCESS_RES);
3152 gen_addr_reg_index(ctx, t0);
3153 tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
3154 tcg_gen_mov_tl(cpu_reserve, t0);
3155 tcg_gen_mov_tl(cpu_reserve_val, gpr);
3156 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
3157 tcg_temp_free(t0);
3158 }
3159
3160 #define LARX(name, memop) \
3161 static void gen_##name(DisasContext *ctx) \
3162 { \
3163 gen_load_locked(ctx, memop); \
3164 }
3165
3166 /* lwarx */
3167 LARX(lbarx, DEF_MEMOP(MO_UB))
3168 LARX(lharx, DEF_MEMOP(MO_UW))
3169 LARX(lwarx, DEF_MEMOP(MO_UL))
3170
3171 static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop,
3172 TCGv EA, TCGCond cond, int addend)
3173 {
3174 TCGv t = tcg_temp_new();
3175 TCGv t2 = tcg_temp_new();
3176 TCGv u = tcg_temp_new();
3177
3178 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3179 tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop));
3180 tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop);
3181 tcg_gen_addi_tl(u, t, addend);
3182
3183 /* E.g. for fetch and increment bounded... */
3184 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3185 tcg_gen_movcond_tl(cond, u, t, t2, u, t);
3186 tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop);
3187
3188 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3189 tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1));
3190 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u);
3191
3192 tcg_temp_free(t);
3193 tcg_temp_free(t2);
3194 tcg_temp_free(u);
3195 }
3196
3197 static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
3198 {
3199 uint32_t gpr_FC = FC(ctx->opcode);
3200 TCGv EA = tcg_temp_new();
3201 int rt = rD(ctx->opcode);
3202 bool need_serial;
3203 TCGv src, dst;
3204
3205 gen_addr_register(ctx, EA);
3206 dst = cpu_gpr[rt];
3207 src = cpu_gpr[(rt + 1) & 31];
3208
3209 need_serial = false;
3210 memop |= MO_ALIGN;
3211 switch (gpr_FC) {
3212 case 0: /* Fetch and add */
3213 tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
3214 break;
3215 case 1: /* Fetch and xor */
3216 tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
3217 break;
3218 case 2: /* Fetch and or */
3219 tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
3220 break;
3221 case 3: /* Fetch and 'and' */
3222 tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
3223 break;
3224 case 4: /* Fetch and max unsigned */
3225 tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop);
3226 break;
3227 case 5: /* Fetch and max signed */
3228 tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop);
3229 break;
3230 case 6: /* Fetch and min unsigned */
3231 tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop);
3232 break;
3233 case 7: /* Fetch and min signed */
3234 tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop);
3235 break;
3236 case 8: /* Swap */
3237 tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
3238 break;
3239
3240 case 16: /* Compare and swap not equal */
3241 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3242 need_serial = true;
3243 } else {
3244 TCGv t0 = tcg_temp_new();
3245 TCGv t1 = tcg_temp_new();
3246
3247 tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop);
3248 if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) {
3249 tcg_gen_mov_tl(t1, src);
3250 } else {
3251 tcg_gen_ext32u_tl(t1, src);
3252 }
3253 tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1,
3254 cpu_gpr[(rt + 2) & 31], t0);
3255 tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop);
3256 tcg_gen_mov_tl(dst, t0);
3257
3258 tcg_temp_free(t0);
3259 tcg_temp_free(t1);
3260 }
3261 break;
3262
3263 case 24: /* Fetch and increment bounded */
3264 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3265 need_serial = true;
3266 } else {
3267 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1);
3268 }
3269 break;
3270 case 25: /* Fetch and increment equal */
3271 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3272 need_serial = true;
3273 } else {
3274 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1);
3275 }
3276 break;
3277 case 28: /* Fetch and decrement bounded */
3278 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3279 need_serial = true;
3280 } else {
3281 gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1);
3282 }
3283 break;
3284
3285 default:
3286 /* invoke data storage error handler */
3287 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3288 }
3289 tcg_temp_free(EA);
3290
3291 if (need_serial) {
3292 /* Restart with exclusive lock. */
3293 gen_helper_exit_atomic(cpu_env);
3294 ctx->base.is_jmp = DISAS_NORETURN;
3295 }
3296 }
3297
3298 static void gen_lwat(DisasContext *ctx)
3299 {
3300 gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
3301 }
3302
3303 #ifdef TARGET_PPC64
3304 static void gen_ldat(DisasContext *ctx)
3305 {
3306 gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
3307 }
3308 #endif
3309
3310 static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop)
3311 {
3312 uint32_t gpr_FC = FC(ctx->opcode);
3313 TCGv EA = tcg_temp_new();
3314 TCGv src, discard;
3315
3316 gen_addr_register(ctx, EA);
3317 src = cpu_gpr[rD(ctx->opcode)];
3318 discard = tcg_temp_new();
3319
3320 memop |= MO_ALIGN;
3321 switch (gpr_FC) {
3322 case 0: /* add and Store */
3323 tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3324 break;
3325 case 1: /* xor and Store */
3326 tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3327 break;
3328 case 2: /* Or and Store */
3329 tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3330 break;
3331 case 3: /* 'and' and Store */
3332 tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3333 break;
3334 case 4: /* Store max unsigned */
3335 tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3336 break;
3337 case 5: /* Store max signed */
3338 tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3339 break;
3340 case 6: /* Store min unsigned */
3341 tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3342 break;
3343 case 7: /* Store min signed */
3344 tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop);
3345 break;
3346 case 24: /* Store twin */
3347 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3348 /* Restart with exclusive lock. */
3349 gen_helper_exit_atomic(cpu_env);
3350 ctx->base.is_jmp = DISAS_NORETURN;
3351 } else {
3352 TCGv t = tcg_temp_new();
3353 TCGv t2 = tcg_temp_new();
3354 TCGv s = tcg_temp_new();
3355 TCGv s2 = tcg_temp_new();
3356 TCGv ea_plus_s = tcg_temp_new();
3357
3358 tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop);
3359 tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop));
3360 tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop);
3361 tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t);
3362 tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2);
3363 tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop);
3364 tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop);
3365
3366 tcg_temp_free(ea_plus_s);
3367 tcg_temp_free(s2);
3368 tcg_temp_free(s);
3369 tcg_temp_free(t2);
3370 tcg_temp_free(t);
3371 }
3372 break;
3373 default:
3374 /* invoke data storage error handler */
3375 gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
3376 }
3377 tcg_temp_free(discard);
3378 tcg_temp_free(EA);
3379 }
3380
3381 static void gen_stwat(DisasContext *ctx)
3382 {
3383 gen_st_atomic(ctx, DEF_MEMOP(MO_UL));
3384 }
3385
3386 #ifdef TARGET_PPC64
3387 static void gen_stdat(DisasContext *ctx)
3388 {
3389 gen_st_atomic(ctx, DEF_MEMOP(MO_Q));
3390 }
3391 #endif
3392
3393 static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop)
3394 {
3395 TCGLabel *l1 = gen_new_label();
3396 TCGLabel *l2 = gen_new_label();
3397 TCGv t0 = tcg_temp_new();
3398 int reg = rS(ctx->opcode);
3399
3400 gen_set_access_type(ctx, ACCESS_RES);
3401 gen_addr_reg_index(ctx, t0);
3402 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3403 tcg_temp_free(t0);
3404
3405 t0 = tcg_temp_new();
3406 tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
3407 cpu_gpr[reg], ctx->mem_idx,
3408 DEF_MEMOP(memop) | MO_ALIGN);
3409 tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val);
3410 tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT);
3411 tcg_gen_or_tl(t0, t0, cpu_so);
3412 tcg_gen_trunc_tl_i32(cpu_crf[0], t0);
3413 tcg_temp_free(t0);
3414 tcg_gen_br(l2);
3415
3416 gen_set_label(l1);
3417
3418 /*
3419 * Address mismatch implies failure. But we still need to provide
3420 * the memory barrier semantics of the instruction.
3421 */
3422 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
3423 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3424
3425 gen_set_label(l2);
3426 tcg_gen_movi_tl(cpu_reserve, -1);
3427 }
3428
3429 #define STCX(name, memop) \
3430 static void gen_##name(DisasContext *ctx) \
3431 { \
3432 gen_conditional_store(ctx, memop); \
3433 }
3434
3435 STCX(stbcx_, DEF_MEMOP(MO_UB))
3436 STCX(sthcx_, DEF_MEMOP(MO_UW))
3437 STCX(stwcx_, DEF_MEMOP(MO_UL))
3438
3439 #if defined(TARGET_PPC64)
3440 /* ldarx */
3441 LARX(ldarx, DEF_MEMOP(MO_Q))
3442 /* stdcx. */
3443 STCX(stdcx_, DEF_MEMOP(MO_Q))
3444
3445 /* lqarx */
3446 static void gen_lqarx(DisasContext *ctx)
3447 {
3448 int rd = rD(ctx->opcode);
3449 TCGv EA, hi, lo;
3450
3451 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3452 (rd == rB(ctx->opcode)))) {
3453 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3454 return;
3455 }
3456
3457 gen_set_access_type(ctx, ACCESS_RES);
3458 EA = tcg_temp_new();
3459 gen_addr_reg_index(ctx, EA);
3460
3461 /* Note that the low part is always in RD+1, even in LE mode. */
3462 lo = cpu_gpr[rd + 1];
3463 hi = cpu_gpr[rd];
3464
3465 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3466 if (HAVE_ATOMIC128) {
3467 TCGv_i32 oi = tcg_temp_new_i32();
3468 if (ctx->le_mode) {
3469 tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16,
3470 ctx->mem_idx));
3471 gen_helper_lq_le_parallel(lo, cpu_env, EA, oi);
3472 } else {
3473 tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16,
3474 ctx->mem_idx));
3475 gen_helper_lq_be_parallel(lo, cpu_env, EA, oi);
3476 }
3477 tcg_temp_free_i32(oi);
3478 tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh));
3479 } else {
3480 /* Restart with exclusive lock. */
3481 gen_helper_exit_atomic(cpu_env);
3482 ctx->base.is_jmp = DISAS_NORETURN;
3483 tcg_temp_free(EA);
3484 return;
3485 }
3486 } else if (ctx->le_mode) {
3487 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16);
3488 tcg_gen_mov_tl(cpu_reserve, EA);
3489 gen_addr_add(ctx, EA, EA, 8);
3490 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ);
3491 } else {
3492 tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16);
3493 tcg_gen_mov_tl(cpu_reserve, EA);
3494 gen_addr_add(ctx, EA, EA, 8);
3495 tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ);
3496 }
3497 tcg_temp_free(EA);
3498
3499 tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val));
3500 tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2));
3501 }
3502
3503 /* stqcx. */
3504 static void gen_stqcx_(DisasContext *ctx)
3505 {
3506 int rs = rS(ctx->opcode);
3507 TCGv EA, hi, lo;
3508
3509 if (unlikely(rs & 1)) {
3510 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3511 return;
3512 }
3513
3514 gen_set_access_type(ctx, ACCESS_RES);
3515 EA = tcg_temp_new();
3516 gen_addr_reg_index(ctx, EA);
3517
3518 /* Note that the low part is always in RS+1, even in LE mode. */
3519 lo = cpu_gpr[rs + 1];
3520 hi = cpu_gpr[rs];
3521
3522 if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
3523 if (HAVE_CMPXCHG128) {
3524 TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16);
3525 if (ctx->le_mode) {
3526 gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env,
3527 EA, lo, hi, oi);
3528 } else {
3529 gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env,
3530 EA, lo, hi, oi);
3531 }
3532 tcg_temp_free_i32(oi);
3533 } else {
3534 /* Restart with exclusive lock. */
3535 gen_helper_exit_atomic(cpu_env);
3536 ctx->base.is_jmp = DISAS_NORETURN;
3537 }
3538 tcg_temp_free(EA);
3539 } else {
3540 TCGLabel *lab_fail = gen_new_label();
3541 TCGLabel *lab_over = gen_new_label();
3542 TCGv_i64 t0 = tcg_temp_new_i64();
3543 TCGv_i64 t1 = tcg_temp_new_i64();
3544
3545 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail);
3546 tcg_temp_free(EA);
3547
3548 gen_qemu_ld64_i64(ctx, t0, cpu_reserve);
3549 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3550 ? offsetof(CPUPPCState, reserve_val2)
3551 : offsetof(CPUPPCState, reserve_val)));
3552 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3553
3554 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3555 gen_qemu_ld64_i64(ctx, t0, t0);
3556 tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode
3557 ? offsetof(CPUPPCState, reserve_val)
3558 : offsetof(CPUPPCState, reserve_val2)));
3559 tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail);
3560
3561 /* Success */
3562 gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve);
3563 tcg_gen_addi_i64(t0, cpu_reserve, 8);
3564 gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0);
3565
3566 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3567 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
3568 tcg_gen_br(lab_over);
3569
3570 gen_set_label(lab_fail);
3571 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3572
3573 gen_set_label(lab_over);
3574 tcg_gen_movi_tl(cpu_reserve, -1);
3575 tcg_temp_free_i64(t0);
3576 tcg_temp_free_i64(t1);
3577 }
3578 }
3579 #endif /* defined(TARGET_PPC64) */
3580
3581 /* sync */
3582 static void gen_sync(DisasContext *ctx)
3583 {
3584 uint32_t l = (ctx->opcode >> 21) & 3;
3585
3586 /*
3587 * We may need to check for a pending TLB flush.
3588 *
3589 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3590 *
3591 * Additionally, this can only happen in kernel mode however so
3592 * check MSR_PR as well.
3593 */
3594 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3595 gen_check_tlb_flush(ctx, true);
3596 }
3597 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
3598 }
3599
3600 /* wait */
3601 static void gen_wait(DisasContext *ctx)
3602 {
3603 TCGv_i32 t0 = tcg_const_i32(1);
3604 tcg_gen_st_i32(t0, cpu_env,
3605 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3606 tcg_temp_free_i32(t0);
3607 /* Stop translation, as the CPU is supposed to sleep from now */
3608 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3609 }
3610
3611 #if defined(TARGET_PPC64)
3612 static void gen_doze(DisasContext *ctx)
3613 {
3614 #if defined(CONFIG_USER_ONLY)
3615 GEN_PRIV;
3616 #else
3617 TCGv_i32 t;
3618
3619 CHK_HV;
3620 t = tcg_const_i32(PPC_PM_DOZE);
3621 gen_helper_pminsn(cpu_env, t);
3622 tcg_temp_free_i32(t);
3623 /* Stop translation, as the CPU is supposed to sleep from now */
3624 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3625 #endif /* defined(CONFIG_USER_ONLY) */
3626 }
3627
3628 static void gen_nap(DisasContext *ctx)
3629 {
3630 #if defined(CONFIG_USER_ONLY)
3631 GEN_PRIV;
3632 #else
3633 TCGv_i32 t;
3634
3635 CHK_HV;
3636 t = tcg_const_i32(PPC_PM_NAP);
3637 gen_helper_pminsn(cpu_env, t);
3638 tcg_temp_free_i32(t);
3639 /* Stop translation, as the CPU is supposed to sleep from now */
3640 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3641 #endif /* defined(CONFIG_USER_ONLY) */
3642 }
3643
3644 static void gen_stop(DisasContext *ctx)
3645 {
3646 #if defined(CONFIG_USER_ONLY)
3647 GEN_PRIV;
3648 #else
3649 TCGv_i32 t;
3650
3651 CHK_HV;
3652 t = tcg_const_i32(PPC_PM_STOP);
3653 gen_helper_pminsn(cpu_env, t);
3654 tcg_temp_free_i32(t);
3655 /* Stop translation, as the CPU is supposed to sleep from now */
3656 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3657 #endif /* defined(CONFIG_USER_ONLY) */
3658 }
3659
3660 static void gen_sleep(DisasContext *ctx)
3661 {
3662 #if defined(CONFIG_USER_ONLY)
3663 GEN_PRIV;
3664 #else
3665 TCGv_i32 t;
3666
3667 CHK_HV;
3668 t = tcg_const_i32(PPC_PM_SLEEP);
3669 gen_helper_pminsn(cpu_env, t);
3670 tcg_temp_free_i32(t);
3671 /* Stop translation, as the CPU is supposed to sleep from now */
3672 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3673 #endif /* defined(CONFIG_USER_ONLY) */
3674 }
3675
3676 static void gen_rvwinkle(DisasContext *ctx)
3677 {
3678 #if defined(CONFIG_USER_ONLY)
3679 GEN_PRIV;
3680 #else
3681 TCGv_i32 t;
3682
3683 CHK_HV;
3684 t = tcg_const_i32(PPC_PM_RVWINKLE);
3685 gen_helper_pminsn(cpu_env, t);
3686 tcg_temp_free_i32(t);
3687 /* Stop translation, as the CPU is supposed to sleep from now */
3688 gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
3689 #endif /* defined(CONFIG_USER_ONLY) */
3690 }
3691 #endif /* #if defined(TARGET_PPC64) */
3692
3693 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3694 {
3695 #if defined(TARGET_PPC64)
3696 if (ctx->has_cfar) {
3697 tcg_gen_movi_tl(cpu_cfar, nip);
3698 }
3699 #endif
3700 }
3701
3702 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3703 {
3704 if (unlikely(ctx->singlestep_enabled)) {
3705 return false;
3706 }
3707
3708 #ifndef CONFIG_USER_ONLY
3709 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3710 #else
3711 return true;
3712 #endif
3713 }
3714
3715 static void gen_lookup_and_goto_ptr(DisasContext *ctx)
3716 {
3717 int sse = ctx->singlestep_enabled;
3718 if (unlikely(sse)) {
3719 if (sse & GDBSTUB_SINGLE_STEP) {
3720 gen_debug_exception(ctx);
3721 } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
3722 uint32_t excp = gen_prep_dbgex(ctx);
3723 gen_exception(ctx, excp);
3724 }
3725 tcg_gen_exit_tb(NULL, 0);
3726 } else {
3727 tcg_gen_lookup_and_goto_ptr();
3728 }
3729 }
3730
3731 /*** Branch ***/
3732 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3733 {
3734 if (NARROW_MODE(ctx)) {
3735 dest = (uint32_t) dest;
3736 }
3737 if (use_goto_tb(ctx, dest)) {
3738 tcg_gen_goto_tb(n);
3739 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3740 tcg_gen_exit_tb(ctx->base.tb, n);
3741 } else {
3742 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3743 gen_lookup_and_goto_ptr(ctx);
3744 }
3745 }
3746
3747 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3748 {
3749 if (NARROW_MODE(ctx)) {
3750 nip = (uint32_t)nip;
3751 }
3752 tcg_gen_movi_tl(cpu_lr, nip);
3753 }
3754
3755 /* b ba bl bla */
3756 static void gen_b(DisasContext *ctx)
3757 {
3758 target_ulong li, target;
3759
3760 ctx->exception = POWERPC_EXCP_BRANCH;
3761 /* sign extend LI */
3762 li = LI(ctx->opcode);
3763 li = (li ^ 0x02000000) - 0x02000000;
3764 if (likely(AA(ctx->opcode) == 0)) {
3765 target = ctx->base.pc_next + li - 4;
3766 } else {
3767 target = li;
3768 }
3769 if (LK(ctx->opcode)) {
3770 gen_setlr(ctx, ctx->base.pc_next);
3771 }
3772 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3773 gen_goto_tb(ctx, 0, target);
3774 }
3775
3776 #define BCOND_IM 0
3777 #define BCOND_LR 1
3778 #define BCOND_CTR 2
3779 #define BCOND_TAR 3
3780
3781 static void gen_bcond(DisasContext *ctx, int type)
3782 {
3783 uint32_t bo = BO(ctx->opcode);
3784 TCGLabel *l1;
3785 TCGv target;
3786 ctx->exception = POWERPC_EXCP_BRANCH;
3787
3788 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3789 target = tcg_temp_local_new();
3790 if (type == BCOND_CTR) {
3791 tcg_gen_mov_tl(target, cpu_ctr);
3792 } else if (type == BCOND_TAR) {
3793 gen_load_spr(target, SPR_TAR);
3794 } else {
3795 tcg_gen_mov_tl(target, cpu_lr);
3796 }
3797 } else {
3798 target = NULL;
3799 }
3800 if (LK(ctx->opcode)) {
3801 gen_setlr(ctx, ctx->base.pc_next);
3802 }
3803 l1 = gen_new_label();
3804 if ((bo & 0x4) == 0) {
3805 /* Decrement and test CTR */
3806 TCGv temp = tcg_temp_new();
3807
3808 if (type == BCOND_CTR) {
3809 /*
3810 * All ISAs up to v3 describe this form of bcctr as invalid but
3811 * some processors, ie. 64-bit server processors compliant with
3812 * arch 2.x, do implement a "test and decrement" logic instead,
3813 * as described in their respective UMs. This logic involves CTR
3814 * to act as both the branch target and a counter, which makes
3815 * it basically useless and thus never used in real code.
3816 *
3817 * This form was hence chosen to trigger extra micro-architectural
3818 * side-effect on real HW needed for the Spectre v2 workaround.
3819 * It is up to guests that implement such workaround, ie. linux, to
3820 * use this form in a way it just triggers the side-effect without
3821 * doing anything else harmful.
3822 */
3823 if (unlikely(!is_book3s_arch2x(ctx))) {
3824 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3825 tcg_temp_free(temp);
3826 tcg_temp_free(target);
3827 return;
3828 }
3829
3830 if (NARROW_MODE(ctx)) {
3831 tcg_gen_ext32u_tl(temp, cpu_ctr);
3832 } else {
3833 tcg_gen_mov_tl(temp, cpu_ctr);
3834 }
3835 if (bo & 0x2) {
3836 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3837 } else {
3838 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3839 }
3840 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3841 } else {
3842 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3843 if (NARROW_MODE(ctx)) {
3844 tcg_gen_ext32u_tl(temp, cpu_ctr);
3845 } else {
3846 tcg_gen_mov_tl(temp, cpu_ctr);
3847 }
3848 if (bo & 0x2) {
3849 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3850 } else {
3851 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3852 }
3853 }
3854 tcg_temp_free(temp);
3855 }
3856 if ((bo & 0x10) == 0) {
3857 /* Test CR */
3858 uint32_t bi = BI(ctx->opcode);
3859 uint32_t mask = 0x08 >> (bi & 0x03);
3860 TCGv_i32 temp = tcg_temp_new_i32();
3861
3862 if (bo & 0x8) {
3863 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3864 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3865 } else {
3866 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3867 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3868 }
3869 tcg_temp_free_i32(temp);
3870 }
3871 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3872 if (type == BCOND_IM) {
3873 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3874 if (likely(AA(ctx->opcode) == 0)) {
3875 gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4);
3876 } else {
3877 gen_goto_tb(ctx, 0, li);
3878 }
3879 } else {
3880 if (NARROW_MODE(ctx)) {
3881 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3882 } else {
3883 tcg_gen_andi_tl(cpu_nip, target, ~3);
3884 }
3885 gen_lookup_and_goto_ptr(ctx);
3886 tcg_temp_free(target);
3887 }
3888 if ((bo & 0x14) != 0x14) {
3889 /* fallthrough case */
3890 gen_set_label(l1);
3891 gen_goto_tb(ctx, 1, ctx->base.pc_next);
3892 }
3893 }
3894
3895 static void gen_bc(DisasContext *ctx)
3896 {
3897 gen_bcond(ctx, BCOND_IM);
3898 }
3899
3900 static void gen_bcctr(DisasContext *ctx)
3901 {
3902 gen_bcond(ctx, BCOND_CTR);
3903 }
3904
3905 static void gen_bclr(DisasContext *ctx)
3906 {
3907 gen_bcond(ctx, BCOND_LR);
3908 }
3909
3910 static void gen_bctar(DisasContext *ctx)
3911 {
3912 gen_bcond(ctx, BCOND_TAR);
3913 }
3914
3915 /*** Condition register logical ***/
3916 #define GEN_CRLOGIC(name, tcg_op, opc) \
3917 static void glue(gen_, name)(DisasContext *ctx) \
3918 { \
3919 uint8_t bitmask; \
3920 int sh; \
3921 TCGv_i32 t0, t1; \
3922 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3923 t0 = tcg_temp_new_i32(); \
3924 if (sh > 0) \
3925 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3926 else if (sh < 0) \
3927 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3928 else \
3929 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3930 t1 = tcg_temp_new_i32(); \
3931 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3932 if (sh > 0) \
3933 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3934 else if (sh < 0) \
3935 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3936 else \
3937 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3938 tcg_op(t0, t0, t1); \
3939 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3940 tcg_gen_andi_i32(t0, t0, bitmask); \
3941 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3942 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3943 tcg_temp_free_i32(t0); \
3944 tcg_temp_free_i32(t1); \
3945 }
3946
3947 /* crand */
3948 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3949 /* crandc */
3950 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3951 /* creqv */
3952 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3953 /* crnand */
3954 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3955 /* crnor */
3956 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3957 /* cror */
3958 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3959 /* crorc */
3960 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3961 /* crxor */
3962 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3963
3964 /* mcrf */
3965 static void gen_mcrf(DisasContext *ctx)
3966 {
3967 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3968 }
3969
3970 /*** System linkage ***/
3971
3972 /* rfi (supervisor only) */
3973 static void gen_rfi(DisasContext *ctx)
3974 {
3975 #if defined(CONFIG_USER_ONLY)
3976 GEN_PRIV;
3977 #else
3978 /*
3979 * This instruction doesn't exist anymore on 64-bit server
3980 * processors compliant with arch 2.x
3981 */
3982 if (is_book3s_arch2x(ctx)) {
3983 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3984 return;
3985 }
3986 /* Restore CPU state */
3987 CHK_SV;
3988 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
3989 gen_io_start();
3990 }
3991 gen_update_cfar(ctx, ctx->base.pc_next - 4);
3992 gen_helper_rfi(cpu_env);
3993 gen_sync_exception(ctx);
3994 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
3995 gen_io_end();
3996 }
3997 #endif
3998 }
3999
4000 #if defined(TARGET_PPC64)
4001 static void gen_rfid(DisasContext *ctx)
4002 {
4003 #if defined(CONFIG_USER_ONLY)
4004 GEN_PRIV;
4005 #else
4006 /* Restore CPU state */
4007 CHK_SV;
4008 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4009 gen_io_start();
4010 }
4011 gen_update_cfar(ctx, ctx->base.pc_next - 4);
4012 gen_helper_rfid(cpu_env);
4013 gen_sync_exception(ctx);
4014 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4015 gen_io_end();
4016 }
4017 #endif
4018 }
4019
4020 static void gen_hrfid(DisasContext *ctx)
4021 {
4022 #if defined(CONFIG_USER_ONLY)
4023 GEN_PRIV;
4024 #else
4025 /* Restore CPU state */
4026 CHK_HV;
4027 gen_helper_hrfid(cpu_env);
4028 gen_sync_exception(ctx);
4029 #endif
4030 }
4031 #endif
4032
4033 /* sc */
4034 #if defined(CONFIG_USER_ONLY)
4035 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4036 #else
4037 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4038 #endif
4039 static void gen_sc(DisasContext *ctx)
4040 {
4041 uint32_t lev;
4042
4043 lev = (ctx->opcode >> 5) & 0x7F;
4044 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4045 }
4046
4047 /*** Trap ***/
4048
4049 /* Check for unconditional traps (always or never) */
4050 static bool check_unconditional_trap(DisasContext *ctx)
4051 {
4052 /* Trap never */
4053 if (TO(ctx->opcode) == 0) {
4054 return true;
4055 }
4056 /* Trap always */
4057 if (TO(ctx->opcode) == 31) {
4058 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
4059 return true;
4060 }
4061 return false;
4062 }
4063
4064 /* tw */
4065 static void gen_tw(DisasContext *ctx)
4066 {
4067 TCGv_i32 t0;
4068
4069 if (check_unconditional_trap(ctx)) {
4070 return;
4071 }
4072 t0 = tcg_const_i32(TO(ctx->opcode));
4073 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4074 t0);
4075 tcg_temp_free_i32(t0);
4076 }
4077
4078 /* twi */
4079 static void gen_twi(DisasContext *ctx)
4080 {
4081 TCGv t0;
4082 TCGv_i32 t1;
4083
4084 if (check_unconditional_trap(ctx)) {
4085 return;
4086 }
4087 t0 = tcg_const_tl(SIMM(ctx->opcode));
4088 t1 = tcg_const_i32(TO(ctx->opcode));
4089 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4090 tcg_temp_free(t0);
4091 tcg_temp_free_i32(t1);
4092 }
4093
4094 #if defined(TARGET_PPC64)
4095 /* td */
4096 static void gen_td(DisasContext *ctx)
4097 {
4098 TCGv_i32 t0;
4099
4100 if (check_unconditional_trap(ctx)) {
4101 return;
4102 }
4103 t0 = tcg_const_i32(TO(ctx->opcode));
4104 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4105 t0);
4106 tcg_temp_free_i32(t0);
4107 }
4108
4109 /* tdi */
4110 static void gen_tdi(DisasContext *ctx)
4111 {
4112 TCGv t0;
4113 TCGv_i32 t1;
4114
4115 if (check_unconditional_trap(ctx)) {
4116 return;
4117 }
4118 t0 = tcg_const_tl(SIMM(ctx->opcode));
4119 t1 = tcg_const_i32(TO(ctx->opcode));
4120 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4121 tcg_temp_free(t0);
4122 tcg_temp_free_i32(t1);
4123 }
4124 #endif
4125
4126 /*** Processor control ***/
4127
4128 static void gen_read_xer(DisasContext *ctx, TCGv dst)
4129 {
4130 TCGv t0 = tcg_temp_new();
4131 TCGv t1 = tcg_temp_new();
4132 TCGv t2 = tcg_temp_new();
4133 tcg_gen_mov_tl(dst, cpu_xer);
4134 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4135 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4136 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4137 tcg_gen_or_tl(t0, t0, t1);
4138 tcg_gen_or_tl(dst, dst, t2);
4139 tcg_gen_or_tl(dst, dst, t0);
4140 if (is_isa300(ctx)) {
4141 tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
4142 tcg_gen_or_tl(dst, dst, t0);
4143 tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
4144 tcg_gen_or_tl(dst, dst, t0);
4145 }
4146 tcg_temp_free(t0);
4147 tcg_temp_free(t1);
4148 tcg_temp_free(t2);
4149 }
4150
4151 static void gen_write_xer(TCGv src)
4152 {
4153 /* Write all flags, while reading back check for isa300 */
4154 tcg_gen_andi_tl(cpu_xer, src,
4155 ~((1u << XER_SO) |
4156 (1u << XER_OV) | (1u << XER_OV32) |
4157 (1u << XER_CA) | (1u << XER_CA32)));
4158 tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
4159 tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
4160 tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
4161 tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
4162 tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
4163 }
4164
4165 /* mcrxr */
4166 static void gen_mcrxr(DisasContext *ctx)
4167 {
4168 TCGv_i32 t0 = tcg_temp_new_i32();
4169 TCGv_i32 t1 = tcg_temp_new_i32();
4170 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4171
4172 tcg_gen_trunc_tl_i32(t0, cpu_so);
4173 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4174 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4175 tcg_gen_shli_i32(t0, t0, 3);
4176 tcg_gen_shli_i32(t1, t1, 2);
4177 tcg_gen_shli_i32(dst, dst, 1);
4178 tcg_gen_or_i32(dst, dst, t0);
4179 tcg_gen_or_i32(dst, dst, t1);
4180 tcg_temp_free_i32(t0);
4181 tcg_temp_free_i32(t1);
4182
4183 tcg_gen_movi_tl(cpu_so, 0);
4184 tcg_gen_movi_tl(cpu_ov, 0);
4185 tcg_gen_movi_tl(cpu_ca, 0);
4186 }
4187
4188 #ifdef TARGET_PPC64
4189 /* mcrxrx */
4190 static void gen_mcrxrx(DisasContext *ctx)
4191 {
4192 TCGv t0 = tcg_temp_new();
4193 TCGv t1 = tcg_temp_new();
4194 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4195
4196 /* copy OV and OV32 */
4197 tcg_gen_shli_tl(t0, cpu_ov, 1);
4198 tcg_gen_or_tl(t0, t0, cpu_ov32);
4199 tcg_gen_shli_tl(t0, t0, 2);
4200 /* copy CA and CA32 */
4201 tcg_gen_shli_tl(t1, cpu_ca, 1);
4202 tcg_gen_or_tl(t1, t1, cpu_ca32);
4203 tcg_gen_or_tl(t0, t0, t1);
4204 tcg_gen_trunc_tl_i32(dst, t0);
4205 tcg_temp_free(t0);
4206 tcg_temp_free(t1);
4207 }
4208 #endif
4209
4210 /* mfcr mfocrf */
4211 static void gen_mfcr(DisasContext *ctx)
4212 {
4213 uint32_t crm, crn;
4214
4215 if (likely(ctx->opcode & 0x00100000)) {
4216 crm = CRM(ctx->opcode);
4217 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4218 crn = ctz32(crm);
4219 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4220 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4221 cpu_gpr[rD(ctx->opcode)], crn * 4);
4222 }
4223 } else {
4224 TCGv_i32 t0 = tcg_temp_new_i32();
4225 tcg_gen_mov_i32(t0, cpu_crf[0]);
4226 tcg_gen_shli_i32(t0, t0, 4);
4227 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4228 tcg_gen_shli_i32(t0, t0, 4);
4229 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4230 tcg_gen_shli_i32(t0, t0, 4);
4231 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4232 tcg_gen_shli_i32(t0, t0, 4);
4233 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4234 tcg_gen_shli_i32(t0, t0, 4);
4235 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4236 tcg_gen_shli_i32(t0, t0, 4);
4237 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4238 tcg_gen_shli_i32(t0, t0, 4);
4239 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4240 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4241 tcg_temp_free_i32(t0);
4242 }
4243 }
4244
4245 /* mfmsr */
4246 static void gen_mfmsr(DisasContext *ctx)
4247 {
4248 CHK_SV;
4249 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4250 }
4251
4252 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4253 {
4254 #if 0
4255 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4256 printf("ERROR: try to access SPR %d !\n", sprn);
4257 #endif
4258 }
4259 #define SPR_NOACCESS (&spr_noaccess)
4260
4261 /* mfspr */
4262 static inline void gen_op_mfspr(DisasContext *ctx)
4263 {
4264 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4265 uint32_t sprn = SPR(ctx->opcode);
4266
4267 #if defined(CONFIG_USER_ONLY)
4268 read_cb = ctx->spr_cb[sprn].uea_read;
4269 #else
4270 if (ctx->pr) {
4271 read_cb = ctx->spr_cb[sprn].uea_read;
4272 } else if (ctx->hv) {
4273 read_cb = ctx->spr_cb[sprn].hea_read;
4274 } else {
4275 read_cb = ctx->spr_cb[sprn].oea_read;
4276 }
4277 #endif
4278 if (likely(read_cb != NULL)) {
4279 if (likely(read_cb != SPR_NOACCESS)) {
4280 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4281 } else {
4282 /* Privilege exception */
4283 /*
4284 * This is a hack to avoid warnings when running Linux:
4285 * this OS breaks the PowerPC virtualisation model,
4286 * allowing userland application to read the PVR
4287 */
4288 if (sprn != SPR_PVR) {
4289 qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr "
4290 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4291 ctx->base.pc_next - 4);
4292 }
4293 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4294 }
4295 } else {
4296 /* ISA 2.07 defines these as no-ops */
4297 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4298 (sprn >= 808 && sprn <= 811)) {
4299 /* This is a nop */
4300 return;
4301 }
4302 /* Not defined */
4303 qemu_log_mask(LOG_GUEST_ERROR,
4304 "Trying to read invalid spr %d (0x%03x) at "
4305 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4306
4307 /*
4308 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4309 * generate a priv, a hv emu or a no-op
4310 */
4311 if (sprn & 0x10) {
4312 if (ctx->pr) {
4313 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4314 }
4315 } else {
4316 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
4317 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4318 }
4319 }
4320 }
4321 }
4322
4323 static void gen_mfspr(DisasContext *ctx)
4324 {
4325 gen_op_mfspr(ctx);
4326 }
4327
4328 /* mftb */
4329 static void gen_mftb(DisasContext *ctx)
4330 {
4331 gen_op_mfspr(ctx);
4332 }
4333
4334 /* mtcrf mtocrf*/
4335 static void gen_mtcrf(DisasContext *ctx)
4336 {
4337 uint32_t crm, crn;
4338
4339 crm = CRM(ctx->opcode);
4340 if (likely((ctx->opcode & 0x00100000))) {
4341 if (crm && ((crm & (crm - 1)) == 0)) {
4342 TCGv_i32 temp = tcg_temp_new_i32();
4343 crn = ctz32(crm);
4344 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4345 tcg_gen_shri_i32(temp, temp, crn * 4);
4346 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4347 tcg_temp_free_i32(temp);
4348 }
4349 } else {
4350 TCGv_i32 temp = tcg_temp_new_i32();
4351 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4352 for (crn = 0 ; crn < 8 ; crn++) {
4353 if (crm & (1 << crn)) {
4354 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4355 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4356 }
4357 }
4358 tcg_temp_free_i32(temp);
4359 }
4360 }
4361
4362 /* mtmsr */
4363 #if defined(TARGET_PPC64)
4364 static void gen_mtmsrd(DisasContext *ctx)
4365 {
4366 CHK_SV;
4367
4368 #if !defined(CONFIG_USER_ONLY)
4369 if (ctx->opcode & 0x00010000) {
4370 /* Special form that does not need any synchronisation */
4371 TCGv t0 = tcg_temp_new();
4372 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
4373 (1 << MSR_RI) | (1 << MSR_EE));
4374 tcg_gen_andi_tl(cpu_msr, cpu_msr,
4375 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4376 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4377 tcg_temp_free(t0);
4378 } else {
4379 /*
4380 * XXX: we need to update nip before the store if we enter
4381 * power saving mode, we will exit the loop directly from
4382 * ppc_store_msr
4383 */
4384 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4385 gen_io_start();
4386 }
4387 gen_update_nip(ctx, ctx->base.pc_next);
4388 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4389 /* Must stop the translation as machine state (may have) changed */
4390 /* Note that mtmsr is not always defined as context-synchronizing */
4391 gen_stop_exception(ctx);
4392 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4393 gen_io_end();
4394 }
4395 }
4396 #endif /* !defined(CONFIG_USER_ONLY) */
4397 }
4398 #endif /* defined(TARGET_PPC64) */
4399
4400 static void gen_mtmsr(DisasContext *ctx)
4401 {
4402 CHK_SV;
4403
4404 #if !defined(CONFIG_USER_ONLY)
4405 if (ctx->opcode & 0x00010000) {
4406 /* Special form that does not need any synchronisation */
4407 TCGv t0 = tcg_temp_new();
4408 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)],
4409 (1 << MSR_RI) | (1 << MSR_EE));
4410 tcg_gen_andi_tl(cpu_msr, cpu_msr,
4411 ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4412 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4413 tcg_temp_free(t0);
4414 } else {
4415 TCGv msr = tcg_temp_new();
4416
4417 /*
4418 * XXX: we need to update nip before the store if we enter
4419 * power saving mode, we will exit the loop directly from
4420 * ppc_store_msr
4421 */
4422 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4423 gen_io_start();
4424 }
4425 gen_update_nip(ctx, ctx->base.pc_next);
4426 #if defined(TARGET_PPC64)
4427 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4428 #else
4429 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4430 #endif
4431 gen_helper_store_msr(cpu_env, msr);
4432 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
4433 gen_io_end();
4434 }
4435 tcg_temp_free(msr);
4436 /* Must stop the translation as machine state (may have) changed */
4437 /* Note that mtmsr is not always defined as context-synchronizing */
4438 gen_stop_exception(ctx);
4439 }
4440 #endif
4441 }
4442
4443 /* mtspr */
4444 static void gen_mtspr(DisasContext *ctx)
4445 {
4446 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4447 uint32_t sprn = SPR(ctx->opcode);
4448
4449 #if defined(CONFIG_USER_ONLY)
4450 write_cb = ctx->spr_cb[sprn].uea_write;
4451 #else
4452 if (ctx->pr) {
4453 write_cb = ctx->spr_cb[sprn].uea_write;
4454 } else if (ctx->hv) {
4455 write_cb = ctx->spr_cb[sprn].hea_write;
4456 } else {
4457 write_cb = ctx->spr_cb[sprn].oea_write;
4458 }
4459 #endif
4460 if (likely(write_cb != NULL)) {
4461 if (likely(write_cb != SPR_NOACCESS)) {
4462 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4463 } else {
4464 /* Privilege exception */
4465 qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr "
4466 "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn,
4467 ctx->base.pc_next - 4);
4468 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
4469 }
4470 } else {
4471 /* ISA 2.07 defines these as no-ops */
4472 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
4473 (sprn >= 808 && sprn <= 811)) {
4474 /* This is a nop */
4475 return;
4476 }
4477
4478 /* Not defined */
4479 qemu_log_mask(LOG_GUEST_ERROR,
4480 "Trying to write invalid spr %d (0x%03x) at "
4481 TARGET_FMT_lx "\n", sprn, sprn, ctx->base.pc_next - 4);
4482
4483
4484 /*
4485 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4486 * generate a priv, a hv emu or a no-op
4487 */
4488 if (sprn & 0x10) {
4489 if (ctx->pr) {
4490 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4491 }
4492 } else {
4493 if (ctx->pr || sprn == 0) {
4494 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4495 }
4496 }
4497 }
4498 }
4499
4500 #if defined(TARGET_PPC64)
4501 /* setb */
4502 static void gen_setb(DisasContext *ctx)
4503 {
4504 TCGv_i32 t0 = tcg_temp_new_i32();
4505 TCGv_i32 t8 = tcg_temp_new_i32();
4506 TCGv_i32 tm1 = tcg_temp_new_i32();
4507 int crf = crfS(ctx->opcode);
4508
4509 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
4510 tcg_gen_movi_i32(t8, 8);
4511 tcg_gen_movi_i32(tm1, -1);
4512 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
4513 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4514
4515 tcg_temp_free_i32(t0);
4516 tcg_temp_free_i32(t8);
4517 tcg_temp_free_i32(tm1);
4518 }
4519 #endif
4520
4521 /*** Cache management ***/
4522
4523 /* dcbf */
4524 static void gen_dcbf(DisasContext *ctx)
4525 {
4526 /* XXX: specification says this is treated as a load by the MMU */
4527 TCGv t0;
4528 gen_set_access_type(ctx, ACCESS_CACHE);
4529 t0 = tcg_temp_new();
4530 gen_addr_reg_index(ctx, t0);
4531 gen_qemu_ld8u(ctx, t0, t0);
4532 tcg_temp_free(t0);
4533 }
4534
4535 /* dcbfep (external PID dcbf) */
4536 static void gen_dcbfep(DisasContext *ctx)
4537 {
4538 /* XXX: specification says this is treated as a load by the MMU */
4539 TCGv t0;
4540 CHK_SV;
4541 gen_set_access_type(ctx, ACCESS_CACHE);
4542 t0 = tcg_temp_new();
4543 gen_addr_reg_index(ctx, t0);
4544 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4545 tcg_temp_free(t0);
4546 }
4547
4548 /* dcbi (Supervisor only) */
4549 static void gen_dcbi(DisasContext *ctx)
4550 {
4551 #if defined(CONFIG_USER_ONLY)
4552 GEN_PRIV;
4553 #else
4554 TCGv EA, val;
4555
4556 CHK_SV;
4557 EA = tcg_temp_new();
4558 gen_set_access_type(ctx, ACCESS_CACHE);
4559 gen_addr_reg_index(ctx, EA);
4560 val = tcg_temp_new();
4561 /* XXX: specification says this should be treated as a store by the MMU */
4562 gen_qemu_ld8u(ctx, val, EA);
4563 gen_qemu_st8(ctx, val, EA);
4564 tcg_temp_free(val);
4565 tcg_temp_free(EA);
4566 #endif /* defined(CONFIG_USER_ONLY) */
4567 }
4568
4569 /* dcdst */
4570 static void gen_dcbst(DisasContext *ctx)
4571 {
4572 /* XXX: specification say this is treated as a load by the MMU */
4573 TCGv t0;
4574 gen_set_access_type(ctx, ACCESS_CACHE);
4575 t0 = tcg_temp_new();
4576 gen_addr_reg_index(ctx, t0);
4577 gen_qemu_ld8u(ctx, t0, t0);
4578 tcg_temp_free(t0);
4579 }
4580
4581 /* dcbstep (dcbstep External PID version) */
4582 static void gen_dcbstep(DisasContext *ctx)
4583 {
4584 /* XXX: specification say this is treated as a load by the MMU */
4585 TCGv t0;
4586 gen_set_access_type(ctx, ACCESS_CACHE);
4587 t0 = tcg_temp_new();
4588 gen_addr_reg_index(ctx, t0);
4589 tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB));
4590 tcg_temp_free(t0);
4591 }
4592
4593 /* dcbt */
4594 static void gen_dcbt(DisasContext *ctx)
4595 {
4596 /*
4597 * interpreted as no-op
4598 * XXX: specification say this is treated as a load by the MMU but
4599 * does not generate any exception
4600 */
4601 }
4602
4603 /* dcbtep */
4604 static void gen_dcbtep(DisasContext *ctx)
4605 {
4606 /*
4607 * interpreted as no-op
4608 * XXX: specification say this is treated as a load by the MMU but
4609 * does not generate any exception
4610 */
4611 }
4612
4613 /* dcbtst */
4614 static void gen_dcbtst(DisasContext *ctx)
4615 {
4616 /*
4617 * interpreted as no-op
4618 * XXX: specification say this is treated as a load by the MMU but
4619 * does not generate any exception
4620 */
4621 }
4622
4623 /* dcbtstep */
4624 static void gen_dcbtstep(DisasContext *ctx)
4625 {
4626 /*
4627 * interpreted as no-op
4628 * XXX: specification say this is treated as a load by the MMU but
4629 * does not generate any exception
4630 */
4631 }
4632
4633 /* dcbtls */
4634 static void gen_dcbtls(DisasContext *ctx)
4635 {
4636 /* Always fails locking the cache */
4637 TCGv t0 = tcg_temp_new();
4638 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4639 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4640 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4641 tcg_temp_free(t0);
4642 }
4643
4644 /* dcbz */
4645 static void gen_dcbz(DisasContext *ctx)
4646 {
4647 TCGv tcgv_addr;
4648 TCGv_i32 tcgv_op;
4649
4650 gen_set_access_type(ctx, ACCESS_CACHE);
4651 tcgv_addr = tcg_temp_new();
4652 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4653 gen_addr_reg_index(ctx, tcgv_addr);
4654 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
4655 tcg_temp_free(tcgv_addr);
4656 tcg_temp_free_i32(tcgv_op);
4657 }
4658
4659 /* dcbzep */
4660 static void gen_dcbzep(DisasContext *ctx)
4661 {
4662 TCGv tcgv_addr;
4663 TCGv_i32 tcgv_op;
4664
4665 gen_set_access_type(ctx, ACCESS_CACHE);
4666 tcgv_addr = tcg_temp_new();
4667 tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
4668 gen_addr_reg_index(ctx, tcgv_addr);
4669 gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
4670 tcg_temp_free(tcgv_addr);
4671 tcg_temp_free_i32(tcgv_op);
4672 }
4673
4674 /* dst / dstt */
4675 static void gen_dst(DisasContext *ctx)
4676 {
4677 if (rA(ctx->opcode) == 0) {
4678 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4679 } else {
4680 /* interpreted as no-op */
4681 }
4682 }
4683
4684 /* dstst /dststt */
4685 static void gen_dstst(DisasContext *ctx)
4686 {
4687 if (rA(ctx->opcode) == 0) {
4688 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4689 } else {
4690 /* interpreted as no-op */
4691 }
4692
4693 }
4694
4695 /* dss / dssall */
4696 static void gen_dss(DisasContext *ctx)
4697 {
4698 /* interpreted as no-op */
4699 }
4700
4701 /* icbi */
4702 static void gen_icbi(DisasContext *ctx)
4703 {
4704 TCGv t0;
4705 gen_set_access_type(ctx, ACCESS_CACHE);
4706 t0 = tcg_temp_new();
4707 gen_addr_reg_index(ctx, t0);
4708 gen_helper_icbi(cpu_env, t0);
4709 tcg_temp_free(t0);
4710 }
4711
4712 /* icbiep */
4713 static void gen_icbiep(DisasContext *ctx)
4714 {
4715 TCGv t0;
4716 gen_set_access_type(ctx, ACCESS_CACHE);
4717 t0 = tcg_temp_new();
4718 gen_addr_reg_index(ctx, t0);
4719 gen_helper_icbiep(cpu_env, t0);
4720 tcg_temp_free(t0);
4721 }
4722
4723 /* Optional: */
4724 /* dcba */
4725 static void gen_dcba(DisasContext *ctx)
4726 {
4727 /*
4728 * interpreted as no-op
4729 * XXX: specification say this is treated as a store by the MMU
4730 * but does not generate any exception
4731 */
4732 }
4733
4734 /*** Segment register manipulation ***/
4735 /* Supervisor only: */
4736
4737 /* mfsr */
4738 static void gen_mfsr(DisasContext *ctx)
4739 {
4740 #if defined(CONFIG_USER_ONLY)
4741 GEN_PRIV;
4742 #else
4743 TCGv t0;
4744
4745 CHK_SV;
4746 t0 = tcg_const_tl(SR(ctx->opcode));
4747 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4748 tcg_temp_free(t0);
4749 #endif /* defined(CONFIG_USER_ONLY) */
4750 }
4751
4752 /* mfsrin */
4753 static void gen_mfsrin(DisasContext *ctx)
4754 {
4755 #if defined(CONFIG_USER_ONLY)
4756 GEN_PRIV;
4757 #else
4758 TCGv t0;
4759
4760 CHK_SV;
4761 t0 = tcg_temp_new();
4762 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4763 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4764 tcg_temp_free(t0);
4765 #endif /* defined(CONFIG_USER_ONLY) */
4766 }
4767
4768 /* mtsr */
4769 static void gen_mtsr(DisasContext *ctx)
4770 {
4771 #if defined(CONFIG_USER_ONLY)
4772 GEN_PRIV;
4773 #else
4774 TCGv t0;
4775
4776 CHK_SV;
4777 t0 = tcg_const_tl(SR(ctx->opcode));
4778 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4779 tcg_temp_free(t0);
4780 #endif /* defined(CONFIG_USER_ONLY) */
4781 }
4782
4783 /* mtsrin */
4784 static void gen_mtsrin(DisasContext *ctx)
4785 {
4786 #if defined(CONFIG_USER_ONLY)
4787 GEN_PRIV;
4788 #else
4789 TCGv t0;
4790 CHK_SV;
4791
4792 t0 = tcg_temp_new();
4793 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4794 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4795 tcg_temp_free(t0);
4796 #endif /* defined(CONFIG_USER_ONLY) */
4797 }
4798
4799 #if defined(TARGET_PPC64)
4800 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4801
4802 /* mfsr */
4803 static void gen_mfsr_64b(DisasContext *ctx)
4804 {
4805 #if defined(CONFIG_USER_ONLY)
4806 GEN_PRIV;
4807 #else
4808 TCGv t0;
4809
4810 CHK_SV;
4811 t0 = tcg_const_tl(SR(ctx->opcode));
4812 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4813 tcg_temp_free(t0);
4814 #endif /* defined(CONFIG_USER_ONLY) */
4815 }
4816
4817 /* mfsrin */
4818 static void gen_mfsrin_64b(DisasContext *ctx)
4819 {
4820 #if defined(CONFIG_USER_ONLY)
4821 GEN_PRIV;
4822 #else
4823 TCGv t0;
4824
4825 CHK_SV;
4826 t0 = tcg_temp_new();
4827 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4828 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4829 tcg_temp_free(t0);
4830 #endif /* defined(CONFIG_USER_ONLY) */
4831 }
4832
4833 /* mtsr */
4834 static void gen_mtsr_64b(DisasContext *ctx)
4835 {
4836 #if defined(CONFIG_USER_ONLY)
4837 GEN_PRIV;
4838 #else
4839 TCGv t0;
4840
4841 CHK_SV;
4842 t0 = tcg_const_tl(SR(ctx->opcode));
4843 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4844 tcg_temp_free(t0);
4845 #endif /* defined(CONFIG_USER_ONLY) */
4846 }
4847
4848 /* mtsrin */
4849 static void gen_mtsrin_64b(DisasContext *ctx)
4850 {
4851 #if defined(CONFIG_USER_ONLY)
4852 GEN_PRIV;
4853 #else
4854 TCGv t0;
4855
4856 CHK_SV;
4857 t0 = tcg_temp_new();
4858 tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
4859 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4860 tcg_temp_free(t0);
4861 #endif /* defined(CONFIG_USER_ONLY) */
4862 }
4863
4864 /* slbmte */
4865 static void gen_slbmte(DisasContext *ctx)
4866 {
4867 #if defined(CONFIG_USER_ONLY)
4868 GEN_PRIV;
4869 #else
4870 CHK_SV;
4871
4872 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4873 cpu_gpr[rS(ctx->opcode)]);
4874 #endif /* defined(CONFIG_USER_ONLY) */
4875 }
4876
4877 static void gen_slbmfee(DisasContext *ctx)
4878 {
4879 #if defined(CONFIG_USER_ONLY)
4880 GEN_PRIV;
4881 #else
4882 CHK_SV;
4883
4884 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4885 cpu_gpr[rB(ctx->opcode)]);
4886 #endif /* defined(CONFIG_USER_ONLY) */
4887 }
4888
4889 static void gen_slbmfev(DisasContext *ctx)
4890 {
4891 #if defined(CONFIG_USER_ONLY)
4892 GEN_PRIV;
4893 #else
4894 CHK_SV;
4895
4896 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4897 cpu_gpr[rB(ctx->opcode)]);
4898 #endif /* defined(CONFIG_USER_ONLY) */
4899 }
4900
4901 static void gen_slbfee_(DisasContext *ctx)
4902 {
4903 #if defined(CONFIG_USER_ONLY)
4904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4905 #else
4906 TCGLabel *l1, *l2;
4907
4908 if (unlikely(ctx->pr)) {
4909 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4910 return;
4911 }
4912 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4913 cpu_gpr[rB(ctx->opcode)]);
4914 l1 = gen_new_label();
4915 l2 = gen_new_label();
4916 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4917 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4918 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
4919 tcg_gen_br(l2);
4920 gen_set_label(l1);
4921 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4922 gen_set_label(l2);
4923 #endif
4924 }
4925 #endif /* defined(TARGET_PPC64) */
4926
4927 /*** Lookaside buffer management ***/
4928 /* Optional & supervisor only: */
4929
4930 /* tlbia */
4931 static void gen_tlbia(DisasContext *ctx)
4932 {
4933 #if defined(CONFIG_USER_ONLY)
4934 GEN_PRIV;
4935 #else
4936 CHK_HV;
4937
4938 gen_helper_tlbia(cpu_env);
4939 #endif /* defined(CONFIG_USER_ONLY) */
4940 }
4941
4942 /* tlbiel */
4943 static void gen_tlbiel(DisasContext *ctx)
4944 {
4945 #if defined(CONFIG_USER_ONLY)
4946 GEN_PRIV;
4947 #else
4948 CHK_SV;
4949
4950 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4951 #endif /* defined(CONFIG_USER_ONLY) */
4952 }
4953
4954 /* tlbie */
4955 static void gen_tlbie(DisasContext *ctx)
4956 {
4957 #if defined(CONFIG_USER_ONLY)
4958 GEN_PRIV;
4959 #else
4960 TCGv_i32 t1;
4961
4962 if (ctx->gtse) {
4963 CHK_SV; /* If gtse is set then tlbie is supervisor privileged */
4964 } else {
4965 CHK_HV; /* Else hypervisor privileged */
4966 }
4967
4968 if (NARROW_MODE(ctx)) {
4969 TCGv t0 = tcg_temp_new();
4970 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4971 gen_helper_tlbie(cpu_env, t0);
4972 tcg_temp_free(t0);
4973 } else {
4974 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4975 }
4976 t1 = tcg_temp_new_i32();
4977 tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4978 tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
4979 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
4980 tcg_temp_free_i32(t1);
4981 #endif /* defined(CONFIG_USER_ONLY) */
4982 }
4983
4984 /* tlbsync */
4985 static void gen_tlbsync(DisasContext *ctx)
4986 {
4987 #if defined(CONFIG_USER_ONLY)
4988 GEN_PRIV;
4989 #else
4990
4991 if (ctx->gtse) {
4992 CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
4993 } else {
4994 CHK_HV; /* Else hypervisor privileged */
4995 }
4996
4997 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4998 if (ctx->insns_flags & PPC_BOOKE) {
4999 gen_check_tlb_flush(ctx, true);
5000 }
5001 #endif /* defined(CONFIG_USER_ONLY) */
5002 }
5003
5004 #if defined(TARGET_PPC64)
5005 /* slbia */
5006 static void gen_slbia(DisasContext *ctx)
5007 {
5008 #if defined(CONFIG_USER_ONLY)
5009 GEN_PRIV;
5010 #else
5011 CHK_SV;
5012
5013 gen_helper_slbia(cpu_env);
5014 #endif /* defined(CONFIG_USER_ONLY) */
5015 }
5016
5017 /* slbie */
5018 static void gen_slbie(DisasContext *ctx)
5019 {
5020 #if defined(CONFIG_USER_ONLY)
5021 GEN_PRIV;
5022 #else
5023 CHK_SV;
5024
5025 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5026 #endif /* defined(CONFIG_USER_ONLY) */
5027 }
5028
5029 /* slbieg */
5030 static void gen_slbieg(DisasContext *ctx)
5031 {
5032 #if defined(CONFIG_USER_ONLY)
5033 GEN_PRIV;
5034 #else
5035 CHK_SV;
5036
5037 gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5038 #endif /* defined(CONFIG_USER_ONLY) */
5039 }
5040
5041 /* slbsync */
5042 static void gen_slbsync(DisasContext *ctx)
5043 {
5044 #if defined(CONFIG_USER_ONLY)
5045 GEN_PRIV;
5046 #else
5047 CHK_SV;
5048 gen_check_tlb_flush(ctx, true);
5049 #endif /* defined(CONFIG_USER_ONLY) */
5050 }
5051
5052 #endif /* defined(TARGET_PPC64) */
5053
5054 /*** External control ***/
5055 /* Optional: */
5056
5057 /* eciwx */
5058 static void gen_eciwx(DisasContext *ctx)
5059 {
5060 TCGv t0;
5061 /* Should check EAR[E] ! */
5062 gen_set_access_type(ctx, ACCESS_EXT);
5063 t0 = tcg_temp_new();
5064 gen_addr_reg_index(ctx, t0);
5065 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5066 DEF_MEMOP(MO_UL | MO_ALIGN));
5067 tcg_temp_free(t0);
5068 }
5069
5070 /* ecowx */
5071 static void gen_ecowx(DisasContext *ctx)
5072 {
5073 TCGv t0;
5074 /* Should check EAR[E] ! */
5075 gen_set_access_type(ctx, ACCESS_EXT);
5076 t0 = tcg_temp_new();
5077 gen_addr_reg_index(ctx, t0);
5078 tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
5079 DEF_MEMOP(MO_UL | MO_ALIGN));
5080 tcg_temp_free(t0);
5081 }
5082
5083 /* PowerPC 601 specific instructions */
5084
5085 /* abs - abs. */
5086 static void gen_abs(DisasContext *ctx)
5087 {
5088 TCGv d = cpu_gpr[rD(ctx->opcode)];
5089 TCGv a = cpu_gpr[rA(ctx->opcode)];
5090
5091 tcg_gen_abs_tl(d, a);
5092 if (unlikely(Rc(ctx->opcode) != 0)) {
5093 gen_set_Rc0(ctx, d);
5094 }
5095 }
5096
5097 /* abso - abso. */
5098 static void gen_abso(DisasContext *ctx)
5099 {
5100 TCGv d = cpu_gpr[rD(ctx->opcode)];
5101 TCGv a = cpu_gpr[rA(ctx->opcode)];
5102
5103 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000);
5104 tcg_gen_abs_tl(d, a);
5105 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
5106 if (unlikely(Rc(ctx->opcode) != 0)) {
5107 gen_set_Rc0(ctx, d);
5108 }
5109 }
5110
5111 /* clcs */
5112 static void gen_clcs(DisasContext *ctx)
5113 {
5114 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5115 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5116 tcg_temp_free_i32(t0);
5117 /* Rc=1 sets CR0 to an undefined state */
5118 }
5119
5120 /* div - div. */
5121 static void gen_div(DisasContext *ctx)
5122 {
5123 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5124 cpu_gpr[rB(ctx->opcode)]);
5125 if (unlikely(Rc(ctx->opcode) != 0)) {
5126 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5127 }
5128 }
5129
5130 /* divo - divo. */
5131 static void gen_divo(DisasContext *ctx)
5132 {
5133 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5134 cpu_gpr[rB(ctx->opcode)]);
5135 if (unlikely(Rc(ctx->opcode) != 0)) {
5136 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5137 }
5138 }
5139
5140 /* divs - divs. */
5141 static void gen_divs(DisasContext *ctx)
5142 {
5143 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5144 cpu_gpr[rB(ctx->opcode)]);
5145 if (unlikely(Rc(ctx->opcode) != 0)) {
5146 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5147 }
5148 }
5149
5150 /* divso - divso. */
5151 static void gen_divso(DisasContext *ctx)
5152 {
5153 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5154 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5155 if (unlikely(Rc(ctx->opcode) != 0)) {
5156 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5157 }
5158 }
5159
5160 /* doz - doz. */
5161 static void gen_doz(DisasContext *ctx)
5162 {
5163 TCGLabel *l1 = gen_new_label();
5164 TCGLabel *l2 = gen_new_label();
5165 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
5166 cpu_gpr[rA(ctx->opcode)], l1);
5167 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
5168 cpu_gpr[rA(ctx->opcode)]);
5169 tcg_gen_br(l2);
5170 gen_set_label(l1);
5171 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5172 gen_set_label(l2);
5173 if (unlikely(Rc(ctx->opcode) != 0)) {
5174 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5175 }
5176 }
5177
5178 /* dozo - dozo. */
5179 static void gen_dozo(DisasContext *ctx)
5180 {
5181 TCGLabel *l1 = gen_new_label();
5182 TCGLabel *l2 = gen_new_label();
5183 TCGv t0 = tcg_temp_new();
5184 TCGv t1 = tcg_temp_new();
5185 TCGv t2 = tcg_temp_new();
5186 /* Start with XER OV disabled, the most likely case */
5187 tcg_gen_movi_tl(cpu_ov, 0);
5188 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)],
5189 cpu_gpr[rA(ctx->opcode)], l1);
5190 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5191 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5192 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5193 tcg_gen_andc_tl(t1, t1, t2);
5194 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5195 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5196 tcg_gen_movi_tl(cpu_ov, 1);
5197 tcg_gen_movi_tl(cpu_so, 1);
5198 tcg_gen_br(l2);
5199 gen_set_label(l1);
5200 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5201 gen_set_label(l2);
5202 tcg_temp_free(t0);
5203 tcg_temp_free(t1);
5204 tcg_temp_free(t2);
5205 if (unlikely(Rc(ctx->opcode) != 0)) {
5206 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5207 }
5208 }
5209
5210 /* dozi */
5211 static void gen_dozi(DisasContext *ctx)
5212 {
5213 target_long simm = SIMM(ctx->opcode);
5214 TCGLabel *l1 = gen_new_label();
5215 TCGLabel *l2 = gen_new_label();
5216 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5217 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5218 tcg_gen_br(l2);
5219 gen_set_label(l1);
5220 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5221 gen_set_label(l2);
5222 if (unlikely(Rc(ctx->opcode) != 0)) {
5223 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5224 }
5225 }
5226
5227 /* lscbx - lscbx. */
5228 static void gen_lscbx(DisasContext *ctx)
5229 {
5230 TCGv t0 = tcg_temp_new();
5231 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5232 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5233 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5234
5235 gen_addr_reg_index(ctx, t0);
5236 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5237 tcg_temp_free_i32(t1);
5238 tcg_temp_free_i32(t2);
5239 tcg_temp_free_i32(t3);
5240 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5241 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5242 if (unlikely(Rc(ctx->opcode) != 0)) {
5243 gen_set_Rc0(ctx, t0);
5244 }
5245 tcg_temp_free(t0);
5246 }
5247
5248 /* maskg - maskg. */
5249 static void gen_maskg(DisasContext *ctx)
5250 {
5251 TCGLabel *l1 = gen_new_label();
5252 TCGv t0 = tcg_temp_new();
5253 TCGv t1 = tcg_temp_new();
5254 TCGv t2 = tcg_temp_new();
5255 TCGv t3 = tcg_temp_new();
5256 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5257 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5258 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5259 tcg_gen_addi_tl(t2, t0, 1);
5260 tcg_gen_shr_tl(t2, t3, t2);
5261 tcg_gen_shr_tl(t3, t3, t1);
5262 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5263 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5264 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5265 gen_set_label(l1);
5266 tcg_temp_free(t0);
5267 tcg_temp_free(t1);
5268 tcg_temp_free(t2);
5269 tcg_temp_free(t3);
5270 if (unlikely(Rc(ctx->opcode) != 0)) {
5271 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5272 }
5273 }
5274
5275 /* maskir - maskir. */
5276 static void gen_maskir(DisasContext *ctx)
5277 {
5278 TCGv t0 = tcg_temp_new();
5279 TCGv t1 = tcg_temp_new();
5280 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5281 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5282 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5283 tcg_temp_free(t0);
5284 tcg_temp_free(t1);
5285 if (unlikely(Rc(ctx->opcode) != 0)) {
5286 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5287 }
5288 }
5289
5290 /* mul - mul. */
5291 static void gen_mul(DisasContext *ctx)
5292 {
5293 TCGv_i64 t0 = tcg_temp_new_i64();
5294 TCGv_i64 t1 = tcg_temp_new_i64();
5295 TCGv t2 = tcg_temp_new();
5296 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5297 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5298 tcg_gen_mul_i64(t0, t0, t1);
5299 tcg_gen_trunc_i64_tl(t2, t0);
5300 gen_store_spr(SPR_MQ, t2);
5301 tcg_gen_shri_i64(t1, t0, 32);
5302 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5303 tcg_temp_free_i64(t0);
5304 tcg_temp_free_i64(t1);
5305 tcg_temp_free(t2);
5306 if (unlikely(Rc(ctx->opcode) != 0)) {
5307 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5308 }
5309 }
5310
5311 /* mulo - mulo. */
5312 static void gen_mulo(DisasContext *ctx)
5313 {
5314 TCGLabel *l1 = gen_new_label();
5315 TCGv_i64 t0 = tcg_temp_new_i64();
5316 TCGv_i64 t1 = tcg_temp_new_i64();
5317 TCGv t2 = tcg_temp_new();
5318 /* Start with XER OV disabled, the most likely case */
5319 tcg_gen_movi_tl(cpu_ov, 0);
5320 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5321 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5322 tcg_gen_mul_i64(t0, t0, t1);
5323 tcg_gen_trunc_i64_tl(t2, t0);
5324 gen_store_spr(SPR_MQ, t2);
5325 tcg_gen_shri_i64(t1, t0, 32);
5326 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5327 tcg_gen_ext32s_i64(t1, t0);
5328 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5329 tcg_gen_movi_tl(cpu_ov, 1);
5330 tcg_gen_movi_tl(cpu_so, 1);
5331 gen_set_label(l1);
5332 tcg_temp_free_i64(t0);
5333 tcg_temp_free_i64(t1);
5334 tcg_temp_free(t2);
5335 if (unlikely(Rc(ctx->opcode) != 0)) {
5336 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5337 }
5338 }
5339
5340 /* nabs - nabs. */
5341 static void gen_nabs(DisasContext *ctx)
5342 {
5343 TCGv d = cpu_gpr[rD(ctx->opcode)];
5344 TCGv a = cpu_gpr[rA(ctx->opcode)];
5345
5346 tcg_gen_abs_tl(d, a);
5347 tcg_gen_neg_tl(d, d);
5348 if (unlikely(Rc(ctx->opcode) != 0)) {
5349 gen_set_Rc0(ctx, d);
5350 }
5351 }
5352
5353 /* nabso - nabso. */
5354 static void gen_nabso(DisasContext *ctx)
5355 {
5356 TCGv d = cpu_gpr[rD(ctx->opcode)];
5357 TCGv a = cpu_gpr[rA(ctx->opcode)];
5358
5359 tcg_gen_abs_tl(d, a);
5360 tcg_gen_neg_tl(d, d);
5361 /* nabs never overflows */
5362 tcg_gen_movi_tl(cpu_ov, 0);
5363 if (unlikely(Rc(ctx->opcode) != 0)) {
5364 gen_set_Rc0(ctx, d);
5365 }
5366 }
5367
5368 /* rlmi - rlmi. */
5369 static void gen_rlmi(DisasContext *ctx)
5370 {
5371 uint32_t mb = MB(ctx->opcode);
5372 uint32_t me = ME(ctx->opcode);
5373 TCGv t0 = tcg_temp_new();
5374 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5375 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5376 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5377 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
5378 ~MASK(mb, me));
5379 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5380 tcg_temp_free(t0);
5381 if (unlikely(Rc(ctx->opcode) != 0)) {
5382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5383 }
5384 }
5385
5386 /* rrib - rrib. */
5387 static void gen_rrib(DisasContext *ctx)
5388 {
5389 TCGv t0 = tcg_temp_new();
5390 TCGv t1 = tcg_temp_new();
5391 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5392 tcg_gen_movi_tl(t1, 0x80000000);
5393 tcg_gen_shr_tl(t1, t1, t0);
5394 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5395 tcg_gen_and_tl(t0, t0, t1);
5396 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5397 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5398 tcg_temp_free(t0);
5399 tcg_temp_free(t1);
5400 if (unlikely(Rc(ctx->opcode) != 0)) {
5401 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5402 }
5403 }
5404
5405 /* sle - sle. */
5406 static void gen_sle(DisasContext *ctx)
5407 {
5408 TCGv t0 = tcg_temp_new();
5409 TCGv t1 = tcg_temp_new();
5410 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5411 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5412 tcg_gen_subfi_tl(t1, 32, t1);
5413 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5414 tcg_gen_or_tl(t1, t0, t1);
5415 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5416 gen_store_spr(SPR_MQ, t1);
5417 tcg_temp_free(t0);
5418 tcg_temp_free(t1);
5419 if (unlikely(Rc(ctx->opcode) != 0)) {
5420 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5421 }
5422 }
5423
5424 /* sleq - sleq. */
5425 static void gen_sleq(DisasContext *ctx)
5426 {
5427 TCGv t0 = tcg_temp_new();
5428 TCGv t1 = tcg_temp_new();
5429 TCGv t2 = tcg_temp_new();
5430 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5431 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5432 tcg_gen_shl_tl(t2, t2, t0);
5433 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5434 gen_load_spr(t1, SPR_MQ);
5435 gen_store_spr(SPR_MQ, t0);
5436 tcg_gen_and_tl(t0, t0, t2);
5437 tcg_gen_andc_tl(t1, t1, t2);
5438 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5439 tcg_temp_free(t0);
5440 tcg_temp_free(t1);
5441 tcg_temp_free(t2);
5442 if (unlikely(Rc(ctx->opcode) != 0)) {
5443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5444 }
5445 }
5446
5447 /* sliq - sliq. */
5448 static void gen_sliq(DisasContext *ctx)
5449 {
5450 int sh = SH(ctx->opcode);
5451 TCGv t0 = tcg_temp_new();
5452 TCGv t1 = tcg_temp_new();
5453 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5454 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5455 tcg_gen_or_tl(t1, t0, t1);
5456 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5457 gen_store_spr(SPR_MQ, t1);
5458 tcg_temp_free(t0);
5459 tcg_temp_free(t1);
5460 if (unlikely(Rc(ctx->opcode) != 0)) {
5461 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5462 }
5463 }
5464
5465 /* slliq - slliq. */
5466 static void gen_slliq(DisasContext *ctx)
5467 {
5468 int sh = SH(ctx->opcode);
5469 TCGv t0 = tcg_temp_new();
5470 TCGv t1 = tcg_temp_new();
5471 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5472 gen_load_spr(t1, SPR_MQ);
5473 gen_store_spr(SPR_MQ, t0);
5474 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5475 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5476 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5477 tcg_temp_free(t0);
5478 tcg_temp_free(t1);
5479 if (unlikely(Rc(ctx->opcode) != 0)) {
5480 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5481 }
5482 }
5483
5484 /* sllq - sllq. */
5485 static void gen_sllq(DisasContext *ctx)
5486 {
5487 TCGLabel *l1 = gen_new_label();
5488 TCGLabel *l2 = gen_new_label();
5489 TCGv t0 = tcg_temp_local_new();
5490 TCGv t1 = tcg_temp_local_new();
5491 TCGv t2 = tcg_temp_local_new();
5492 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5493 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5494 tcg_gen_shl_tl(t1, t1, t2);
5495 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5496 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5497 gen_load_spr(t0, SPR_MQ);
5498 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5499 tcg_gen_br(l2);
5500 gen_set_label(l1);
5501 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5502 gen_load_spr(t2, SPR_MQ);
5503 tcg_gen_andc_tl(t1, t2, t1);
5504 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5505 gen_set_label(l2);
5506 tcg_temp_free(t0);
5507 tcg_temp_free(t1);
5508 tcg_temp_free(t2);
5509 if (unlikely(Rc(ctx->opcode) != 0)) {
5510 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5511 }
5512 }
5513
5514 /* slq - slq. */
5515 static void gen_slq(DisasContext *ctx)
5516 {
5517 TCGLabel *l1 = gen_new_label();
5518 TCGv t0 = tcg_temp_new();
5519 TCGv t1 = tcg_temp_new();
5520 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5521 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5522 tcg_gen_subfi_tl(t1, 32, t1);
5523 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5524 tcg_gen_or_tl(t1, t0, t1);
5525 gen_store_spr(SPR_MQ, t1);
5526 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5527 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5528 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5529 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5530 gen_set_label(l1);
5531 tcg_temp_free(t0);
5532 tcg_temp_free(t1);
5533 if (unlikely(Rc(ctx->opcode) != 0)) {
5534 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5535 }
5536 }
5537
5538 /* sraiq - sraiq. */
5539 static void gen_sraiq(DisasContext *ctx)
5540 {
5541 int sh = SH(ctx->opcode);
5542 TCGLabel *l1 = gen_new_label();
5543 TCGv t0 = tcg_temp_new();
5544 TCGv t1 = tcg_temp_new();
5545 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5546 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5547 tcg_gen_or_tl(t0, t0, t1);
5548 gen_store_spr(SPR_MQ, t0);
5549 tcg_gen_movi_tl(cpu_ca, 0);
5550 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5551 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5552 tcg_gen_movi_tl(cpu_ca, 1);
5553 gen_set_label(l1);
5554 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5555 tcg_temp_free(t0);
5556 tcg_temp_free(t1);
5557 if (unlikely(Rc(ctx->opcode) != 0)) {
5558 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5559 }
5560 }
5561
5562 /* sraq - sraq. */
5563 static void gen_sraq(DisasContext *ctx)
5564 {
5565 TCGLabel *l1 = gen_new_label();
5566 TCGLabel *l2 = gen_new_label();
5567 TCGv t0 = tcg_temp_new();
5568 TCGv t1 = tcg_temp_local_new();
5569 TCGv t2 = tcg_temp_local_new();
5570 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5571 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5572 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5573 tcg_gen_subfi_tl(t2, 32, t2);
5574 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5575 tcg_gen_or_tl(t0, t0, t2);
5576 gen_store_spr(SPR_MQ, t0);
5577 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5578 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5579 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5580 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5581 gen_set_label(l1);
5582 tcg_temp_free(t0);
5583 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5584 tcg_gen_movi_tl(cpu_ca, 0);
5585 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5586 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5587 tcg_gen_movi_tl(cpu_ca, 1);
5588 gen_set_label(l2);
5589 tcg_temp_free(t1);
5590 tcg_temp_free(t2);
5591 if (unlikely(Rc(ctx->opcode) != 0)) {
5592 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5593 }
5594 }
5595
5596 /* sre - sre. */
5597 static void gen_sre(DisasContext *ctx)
5598 {
5599 TCGv t0 = tcg_temp_new();
5600 TCGv t1 = tcg_temp_new();
5601 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5602 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5603 tcg_gen_subfi_tl(t1, 32, t1);
5604 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5605 tcg_gen_or_tl(t1, t0, t1);
5606 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5607 gen_store_spr(SPR_MQ, t1);
5608 tcg_temp_free(t0);
5609 tcg_temp_free(t1);
5610 if (unlikely(Rc(ctx->opcode) != 0)) {
5611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5612 }
5613 }
5614
5615 /* srea - srea. */
5616 static void gen_srea(DisasContext *ctx)
5617 {
5618 TCGv t0 = tcg_temp_new();
5619 TCGv t1 = tcg_temp_new();
5620 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5621 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5622 gen_store_spr(SPR_MQ, t0);
5623 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5624 tcg_temp_free(t0);
5625 tcg_temp_free(t1);
5626 if (unlikely(Rc(ctx->opcode) != 0)) {
5627 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5628 }
5629 }
5630
5631 /* sreq */
5632 static void gen_sreq(DisasContext *ctx)
5633 {
5634 TCGv t0 = tcg_temp_new();
5635 TCGv t1 = tcg_temp_new();
5636 TCGv t2 = tcg_temp_new();
5637 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5638 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5639 tcg_gen_shr_tl(t1, t1, t0);
5640 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5641 gen_load_spr(t2, SPR_MQ);
5642 gen_store_spr(SPR_MQ, t0);
5643 tcg_gen_and_tl(t0, t0, t1);
5644 tcg_gen_andc_tl(t2, t2, t1);
5645 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5646 tcg_temp_free(t0);
5647 tcg_temp_free(t1);
5648 tcg_temp_free(t2);
5649 if (unlikely(Rc(ctx->opcode) != 0)) {
5650 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5651 }
5652 }
5653
5654 /* sriq */
5655 static void gen_sriq(DisasContext *ctx)
5656 {
5657 int sh = SH(ctx->opcode);
5658 TCGv t0 = tcg_temp_new();
5659 TCGv t1 = tcg_temp_new();
5660 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5661 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5662 tcg_gen_or_tl(t1, t0, t1);
5663 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5664 gen_store_spr(SPR_MQ, t1);
5665 tcg_temp_free(t0);
5666 tcg_temp_free(t1);
5667 if (unlikely(Rc(ctx->opcode) != 0)) {
5668 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5669 }
5670 }
5671
5672 /* srliq */
5673 static void gen_srliq(DisasContext *ctx)
5674 {
5675 int sh = SH(ctx->opcode);
5676 TCGv t0 = tcg_temp_new();
5677 TCGv t1 = tcg_temp_new();
5678 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5679 gen_load_spr(t1, SPR_MQ);
5680 gen_store_spr(SPR_MQ, t0);
5681 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5682 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5683 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5684 tcg_temp_free(t0);
5685 tcg_temp_free(t1);
5686 if (unlikely(Rc(ctx->opcode) != 0)) {
5687 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5688 }
5689 }
5690
5691 /* srlq */
5692 static void gen_srlq(DisasContext *ctx)
5693 {
5694 TCGLabel *l1 = gen_new_label();
5695 TCGLabel *l2 = gen_new_label();
5696 TCGv t0 = tcg_temp_local_new();
5697 TCGv t1 = tcg_temp_local_new();
5698 TCGv t2 = tcg_temp_local_new();
5699 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5700 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5701 tcg_gen_shr_tl(t2, t1, t2);
5702 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5703 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5704 gen_load_spr(t0, SPR_MQ);
5705 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5706 tcg_gen_br(l2);
5707 gen_set_label(l1);
5708 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5709 tcg_gen_and_tl(t0, t0, t2);
5710 gen_load_spr(t1, SPR_MQ);
5711 tcg_gen_andc_tl(t1, t1, t2);
5712 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5713 gen_set_label(l2);
5714 tcg_temp_free(t0);
5715 tcg_temp_free(t1);
5716 tcg_temp_free(t2);
5717 if (unlikely(Rc(ctx->opcode) != 0)) {
5718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5719 }
5720 }
5721
5722 /* srq */
5723 static void gen_srq(DisasContext *ctx)
5724 {
5725 TCGLabel *l1 = gen_new_label();
5726 TCGv t0 = tcg_temp_new();
5727 TCGv t1 = tcg_temp_new();
5728 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5729 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5730 tcg_gen_subfi_tl(t1, 32, t1);
5731 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5732 tcg_gen_or_tl(t1, t0, t1);
5733 gen_store_spr(SPR_MQ, t1);
5734 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5736 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5737 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5738 gen_set_label(l1);
5739 tcg_temp_free(t0);
5740 tcg_temp_free(t1);
5741 if (unlikely(Rc(ctx->opcode) != 0)) {
5742 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5743 }
5744 }
5745
5746 /* PowerPC 602 specific instructions */
5747
5748 /* dsa */
5749 static void gen_dsa(DisasContext *ctx)
5750 {
5751 /* XXX: TODO */
5752 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5753 }
5754
5755 /* esa */
5756 static void gen_esa(DisasContext *ctx)
5757 {
5758 /* XXX: TODO */
5759 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5760 }
5761
5762 /* mfrom */
5763 static void gen_mfrom(DisasContext *ctx)
5764 {
5765 #if defined(CONFIG_USER_ONLY)
5766 GEN_PRIV;
5767 #else
5768 CHK_SV;
5769 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5770 #endif /* defined(CONFIG_USER_ONLY) */
5771 }
5772
5773 /* 602 - 603 - G2 TLB management */
5774
5775 /* tlbld */
5776 static void gen_tlbld_6xx(DisasContext *ctx)
5777 {
5778 #if defined(CONFIG_USER_ONLY)
5779 GEN_PRIV;
5780 #else
5781 CHK_SV;
5782 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5783 #endif /* defined(CONFIG_USER_ONLY) */
5784 }
5785
5786 /* tlbli */
5787 static void gen_tlbli_6xx(DisasContext *ctx)
5788 {
5789 #if defined(CONFIG_USER_ONLY)
5790 GEN_PRIV;
5791 #else
5792 CHK_SV;
5793 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5794 #endif /* defined(CONFIG_USER_ONLY) */
5795 }
5796
5797 /* 74xx TLB management */
5798
5799 /* tlbld */
5800 static void gen_tlbld_74xx(DisasContext *ctx)
5801 {
5802 #if defined(CONFIG_USER_ONLY)
5803 GEN_PRIV;
5804 #else
5805 CHK_SV;
5806 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5807 #endif /* defined(CONFIG_USER_ONLY) */
5808 }
5809
5810 /* tlbli */
5811 static void gen_tlbli_74xx(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814 GEN_PRIV;
5815 #else
5816 CHK_SV;
5817 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5818 #endif /* defined(CONFIG_USER_ONLY) */
5819 }
5820
5821 /* POWER instructions not in PowerPC 601 */
5822
5823 /* clf */
5824 static void gen_clf(DisasContext *ctx)
5825 {
5826 /* Cache line flush: implemented as no-op */
5827 }
5828
5829 /* cli */
5830 static void gen_cli(DisasContext *ctx)
5831 {
5832 #if defined(CONFIG_USER_ONLY)
5833 GEN_PRIV;
5834 #else
5835 /* Cache line invalidate: privileged and treated as no-op */
5836 CHK_SV;
5837 #endif /* defined(CONFIG_USER_ONLY) */
5838 }
5839
5840 /* dclst */
5841 static void gen_dclst(DisasContext *ctx)
5842 {
5843 /* Data cache line store: treated as no-op */
5844 }
5845
5846 static void gen_mfsri(DisasContext *ctx)
5847 {
5848 #if defined(CONFIG_USER_ONLY)
5849 GEN_PRIV;
5850 #else
5851 int ra = rA(ctx->opcode);
5852 int rd = rD(ctx->opcode);
5853 TCGv t0;
5854
5855 CHK_SV;
5856 t0 = tcg_temp_new();
5857 gen_addr_reg_index(ctx, t0);
5858 tcg_gen_extract_tl(t0, t0, 28, 4);
5859 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5860 tcg_temp_free(t0);
5861 if (ra != 0 && ra != rd) {
5862 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5863 }
5864 #endif /* defined(CONFIG_USER_ONLY) */
5865 }
5866
5867 static void gen_rac(DisasContext *ctx)
5868 {
5869 #if defined(CONFIG_USER_ONLY)
5870 GEN_PRIV;
5871 #else
5872 TCGv t0;
5873
5874 CHK_SV;
5875 t0 = tcg_temp_new();
5876 gen_addr_reg_index(ctx, t0);
5877 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5878 tcg_temp_free(t0);
5879 #endif /* defined(CONFIG_USER_ONLY) */
5880 }
5881
5882 static void gen_rfsvc(DisasContext *ctx)
5883 {
5884 #if defined(CONFIG_USER_ONLY)
5885 GEN_PRIV;
5886 #else
5887 CHK_SV;
5888
5889 gen_helper_rfsvc(cpu_env);
5890 gen_sync_exception(ctx);
5891 #endif /* defined(CONFIG_USER_ONLY) */
5892 }
5893
5894 /* svc is not implemented for now */
5895
5896 /* BookE specific instructions */
5897
5898 /* XXX: not implemented on 440 ? */
5899 static void gen_mfapidi(DisasContext *ctx)
5900 {
5901 /* XXX: TODO */
5902 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5903 }
5904
5905 /* XXX: not implemented on 440 ? */
5906 static void gen_tlbiva(DisasContext *ctx)
5907 {
5908 #if defined(CONFIG_USER_ONLY)
5909 GEN_PRIV;
5910 #else
5911 TCGv t0;
5912
5913 CHK_SV;
5914 t0 = tcg_temp_new();
5915 gen_addr_reg_index(ctx, t0);
5916 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5917 tcg_temp_free(t0);
5918 #endif /* defined(CONFIG_USER_ONLY) */
5919 }
5920
5921 /* All 405 MAC instructions are translated here */
5922 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5923 int ra, int rb, int rt, int Rc)
5924 {
5925 TCGv t0, t1;
5926
5927 t0 = tcg_temp_local_new();
5928 t1 = tcg_temp_local_new();
5929
5930 switch (opc3 & 0x0D) {
5931 case 0x05:
5932 /* macchw - macchw. - macchwo - macchwo. */
5933 /* macchws - macchws. - macchwso - macchwso. */
5934 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5935 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5936 /* mulchw - mulchw. */
5937 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5938 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5939 tcg_gen_ext16s_tl(t1, t1);
5940 break;
5941 case 0x04:
5942 /* macchwu - macchwu. - macchwuo - macchwuo. */
5943 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5944 /* mulchwu - mulchwu. */
5945 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5946 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5947 tcg_gen_ext16u_tl(t1, t1);
5948 break;
5949 case 0x01:
5950 /* machhw - machhw. - machhwo - machhwo. */
5951 /* machhws - machhws. - machhwso - machhwso. */
5952 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5953 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5954 /* mulhhw - mulhhw. */
5955 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5956 tcg_gen_ext16s_tl(t0, t0);
5957 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5958 tcg_gen_ext16s_tl(t1, t1);
5959 break;
5960 case 0x00:
5961 /* machhwu - machhwu. - machhwuo - machhwuo. */
5962 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5963 /* mulhhwu - mulhhwu. */
5964 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5965 tcg_gen_ext16u_tl(t0, t0);
5966 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5967 tcg_gen_ext16u_tl(t1, t1);
5968 break;
5969 case 0x0D:
5970 /* maclhw - maclhw. - maclhwo - maclhwo. */
5971 /* maclhws - maclhws. - maclhwso - maclhwso. */
5972 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5973 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5974 /* mullhw - mullhw. */
5975 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5976 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5977 break;
5978 case 0x0C:
5979 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5980 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5981 /* mullhwu - mullhwu. */
5982 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5983 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5984 break;
5985 }
5986 if (opc2 & 0x04) {
5987 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5988 tcg_gen_mul_tl(t1, t0, t1);
5989 if (opc2 & 0x02) {
5990 /* nmultiply-and-accumulate (0x0E) */
5991 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5992 } else {
5993 /* multiply-and-accumulate (0x0C) */
5994 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5995 }
5996
5997 if (opc3 & 0x12) {
5998 /* Check overflow and/or saturate */
5999 TCGLabel *l1 = gen_new_label();
6000
6001 if (opc3 & 0x10) {
6002 /* Start with XER OV disabled, the most likely case */
6003 tcg_gen_movi_tl(cpu_ov, 0);
6004 }
6005 if (opc3 & 0x01) {
6006 /* Signed */
6007 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6008 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6009 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6010 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6011 if (opc3 & 0x02) {
6012 /* Saturate */
6013 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6014 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6015 }
6016 } else {
6017 /* Unsigned */
6018 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6019 if (opc3 & 0x02) {
6020 /* Saturate */
6021 tcg_gen_movi_tl(t0, UINT32_MAX);
6022 }
6023 }
6024 if (opc3 & 0x10) {
6025 /* Check overflow */
6026 tcg_gen_movi_tl(cpu_ov, 1);
6027 tcg_gen_movi_tl(cpu_so, 1);
6028 }
6029 gen_set_label(l1);
6030 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6031 }
6032 } else {
6033 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6034 }
6035 tcg_temp_free(t0);
6036 tcg_temp_free(t1);
6037 if (unlikely(Rc) != 0) {
6038 /* Update Rc0 */
6039 gen_set_Rc0(ctx, cpu_gpr[rt]);
6040 }
6041 }
6042
6043 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6044 static void glue(gen_, name)(DisasContext *ctx) \
6045 { \
6046 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6047 rD(ctx->opcode), Rc(ctx->opcode)); \
6048 }
6049
6050 /* macchw - macchw. */
6051 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6052 /* macchwo - macchwo. */
6053 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6054 /* macchws - macchws. */
6055 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6056 /* macchwso - macchwso. */
6057 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6058 /* macchwsu - macchwsu. */
6059 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6060 /* macchwsuo - macchwsuo. */
6061 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6062 /* macchwu - macchwu. */
6063 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6064 /* macchwuo - macchwuo. */
6065 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6066 /* machhw - machhw. */
6067 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6068 /* machhwo - machhwo. */
6069 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6070 /* machhws - machhws. */
6071 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6072 /* machhwso - machhwso. */
6073 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6074 /* machhwsu - machhwsu. */
6075 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6076 /* machhwsuo - machhwsuo. */
6077 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6078 /* machhwu - machhwu. */
6079 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6080 /* machhwuo - machhwuo. */
6081 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6082 /* maclhw - maclhw. */
6083 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6084 /* maclhwo - maclhwo. */
6085 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6086 /* maclhws - maclhws. */
6087 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6088 /* maclhwso - maclhwso. */
6089 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6090 /* maclhwu - maclhwu. */
6091 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6092 /* maclhwuo - maclhwuo. */
6093 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6094 /* maclhwsu - maclhwsu. */
6095 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6096 /* maclhwsuo - maclhwsuo. */
6097 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6098 /* nmacchw - nmacchw. */
6099 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6100 /* nmacchwo - nmacchwo. */
6101 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6102 /* nmacchws - nmacchws. */
6103 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6104 /* nmacchwso - nmacchwso. */
6105 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6106 /* nmachhw - nmachhw. */
6107 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6108 /* nmachhwo - nmachhwo. */
6109 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6110 /* nmachhws - nmachhws. */
6111 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6112 /* nmachhwso - nmachhwso. */
6113 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6114 /* nmaclhw - nmaclhw. */
6115 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6116 /* nmaclhwo - nmaclhwo. */
6117 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6118 /* nmaclhws - nmaclhws. */
6119 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6120 /* nmaclhwso - nmaclhwso. */
6121 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6122
6123 /* mulchw - mulchw. */
6124 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6125 /* mulchwu - mulchwu. */
6126 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6127 /* mulhhw - mulhhw. */
6128 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6129 /* mulhhwu - mulhhwu. */
6130 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6131 /* mullhw - mullhw. */
6132 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6133 /* mullhwu - mullhwu. */
6134 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6135
6136 /* mfdcr */
6137 static void gen_mfdcr(DisasContext *ctx)
6138 {
6139 #if defined(CONFIG_USER_ONLY)
6140 GEN_PRIV;
6141 #else
6142 TCGv dcrn;
6143
6144 CHK_SV;
6145 dcrn = tcg_const_tl(SPR(ctx->opcode));
6146 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6147 tcg_temp_free(dcrn);
6148 #endif /* defined(CONFIG_USER_ONLY) */
6149 }
6150
6151 /* mtdcr */
6152 static void gen_mtdcr(DisasContext *ctx)
6153 {
6154 #if defined(CONFIG_USER_ONLY)
6155 GEN_PRIV;
6156 #else
6157 TCGv dcrn;
6158
6159 CHK_SV;
6160 dcrn = tcg_const_tl(SPR(ctx->opcode));
6161 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6162 tcg_temp_free(dcrn);
6163 #endif /* defined(CONFIG_USER_ONLY) */
6164 }
6165
6166 /* mfdcrx */
6167 /* XXX: not implemented on 440 ? */
6168 static void gen_mfdcrx(DisasContext *ctx)
6169 {
6170 #if defined(CONFIG_USER_ONLY)
6171 GEN_PRIV;
6172 #else
6173 CHK_SV;
6174 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6175 cpu_gpr[rA(ctx->opcode)]);
6176 /* Note: Rc update flag set leads to undefined state of Rc0 */
6177 #endif /* defined(CONFIG_USER_ONLY) */
6178 }
6179
6180 /* mtdcrx */
6181 /* XXX: not implemented on 440 ? */
6182 static void gen_mtdcrx(DisasContext *ctx)
6183 {
6184 #if defined(CONFIG_USER_ONLY)
6185 GEN_PRIV;
6186 #else
6187 CHK_SV;
6188 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6189 cpu_gpr[rS(ctx->opcode)]);
6190 /* Note: Rc update flag set leads to undefined state of Rc0 */
6191 #endif /* defined(CONFIG_USER_ONLY) */
6192 }
6193
6194 /* mfdcrux (PPC 460) : user-mode access to DCR */
6195 static void gen_mfdcrux(DisasContext *ctx)
6196 {
6197 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6198 cpu_gpr[rA(ctx->opcode)]);
6199 /* Note: Rc update flag set leads to undefined state of Rc0 */
6200 }
6201
6202 /* mtdcrux (PPC 460) : user-mode access to DCR */
6203 static void gen_mtdcrux(DisasContext *ctx)
6204 {
6205 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6206 cpu_gpr[rS(ctx->opcode)]);
6207 /* Note: Rc update flag set leads to undefined state of Rc0 */
6208 }
6209
6210 /* dccci */
6211 static void gen_dccci(DisasContext *ctx)
6212 {
6213 CHK_SV;
6214 /* interpreted as no-op */
6215 }
6216
6217 /* dcread */
6218 static void gen_dcread(DisasContext *ctx)
6219 {
6220 #if defined(CONFIG_USER_ONLY)
6221 GEN_PRIV;
6222 #else
6223 TCGv EA, val;
6224
6225 CHK_SV;
6226 gen_set_access_type(ctx, ACCESS_CACHE);
6227 EA = tcg_temp_new();
6228 gen_addr_reg_index(ctx, EA);
6229 val = tcg_temp_new();
6230 gen_qemu_ld32u(ctx, val, EA);
6231 tcg_temp_free(val);
6232 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6233 tcg_temp_free(EA);
6234 #endif /* defined(CONFIG_USER_ONLY) */
6235 }
6236
6237 /* icbt */
6238 static void gen_icbt_40x(DisasContext *ctx)
6239 {
6240 /*
6241 * interpreted as no-op
6242 * XXX: specification say this is treated as a load by the MMU but
6243 * does not generate any exception
6244 */
6245 }
6246
6247 /* iccci */
6248 static void gen_iccci(DisasContext *ctx)
6249 {
6250 CHK_SV;
6251 /* interpreted as no-op */
6252 }
6253
6254 /* icread */
6255 static void gen_icread(DisasContext *ctx)
6256 {
6257 CHK_SV;
6258 /* interpreted as no-op */
6259 }
6260
6261 /* rfci (supervisor only) */
6262 static void gen_rfci_40x(DisasContext *ctx)
6263 {
6264 #if defined(CONFIG_USER_ONLY)
6265 GEN_PRIV;
6266 #else
6267 CHK_SV;
6268 /* Restore CPU state */
6269 gen_helper_40x_rfci(cpu_env);
6270 gen_sync_exception(ctx);
6271 #endif /* defined(CONFIG_USER_ONLY) */
6272 }
6273
6274 static void gen_rfci(DisasContext *ctx)
6275 {
6276 #if defined(CONFIG_USER_ONLY)
6277 GEN_PRIV;
6278 #else
6279 CHK_SV;
6280 /* Restore CPU state */
6281 gen_helper_rfci(cpu_env);
6282 gen_sync_exception(ctx);
6283 #endif /* defined(CONFIG_USER_ONLY) */
6284 }
6285
6286 /* BookE specific */
6287
6288 /* XXX: not implemented on 440 ? */
6289 static void gen_rfdi(DisasContext *ctx)
6290 {
6291 #if defined(CONFIG_USER_ONLY)
6292 GEN_PRIV;
6293 #else
6294 CHK_SV;
6295 /* Restore CPU state */
6296 gen_helper_rfdi(cpu_env);
6297 gen_sync_exception(ctx);
6298 #endif /* defined(CONFIG_USER_ONLY) */
6299 }
6300
6301 /* XXX: not implemented on 440 ? */
6302 static void gen_rfmci(DisasContext *ctx)
6303 {
6304 #if defined(CONFIG_USER_ONLY)
6305 GEN_PRIV;
6306 #else
6307 CHK_SV;
6308 /* Restore CPU state */
6309 gen_helper_rfmci(cpu_env);
6310 gen_sync_exception(ctx);
6311 #endif /* defined(CONFIG_USER_ONLY) */
6312 }
6313
6314 /* TLB management - PowerPC 405 implementation */
6315
6316 /* tlbre */
6317 static void gen_tlbre_40x(DisasContext *ctx)
6318 {
6319 #if defined(CONFIG_USER_ONLY)
6320 GEN_PRIV;
6321 #else
6322 CHK_SV;
6323 switch (rB(ctx->opcode)) {
6324 case 0:
6325 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6326 cpu_gpr[rA(ctx->opcode)]);
6327 break;
6328 case 1:
6329 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6330 cpu_gpr[rA(ctx->opcode)]);
6331 break;
6332 default:
6333 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6334 break;
6335 }
6336 #endif /* defined(CONFIG_USER_ONLY) */
6337 }
6338
6339 /* tlbsx - tlbsx. */
6340 static void gen_tlbsx_40x(DisasContext *ctx)
6341 {
6342 #if defined(CONFIG_USER_ONLY)
6343 GEN_PRIV;
6344 #else
6345 TCGv t0;
6346
6347 CHK_SV;
6348 t0 = tcg_temp_new();
6349 gen_addr_reg_index(ctx, t0);
6350 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6351 tcg_temp_free(t0);
6352 if (Rc(ctx->opcode)) {
6353 TCGLabel *l1 = gen_new_label();
6354 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6355 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6356 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6357 gen_set_label(l1);
6358 }
6359 #endif /* defined(CONFIG_USER_ONLY) */
6360 }
6361
6362 /* tlbwe */
6363 static void gen_tlbwe_40x(DisasContext *ctx)
6364 {
6365 #if defined(CONFIG_USER_ONLY)
6366 GEN_PRIV;
6367 #else
6368 CHK_SV;
6369
6370 switch (rB(ctx->opcode)) {
6371 case 0:
6372 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6373 cpu_gpr[rS(ctx->opcode)]);
6374 break;
6375 case 1:
6376 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6377 cpu_gpr[rS(ctx->opcode)]);
6378 break;
6379 default:
6380 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6381 break;
6382 }
6383 #endif /* defined(CONFIG_USER_ONLY) */
6384 }
6385
6386 /* TLB management - PowerPC 440 implementation */
6387
6388 /* tlbre */
6389 static void gen_tlbre_440(DisasContext *ctx)
6390 {
6391 #if defined(CONFIG_USER_ONLY)
6392 GEN_PRIV;
6393 #else
6394 CHK_SV;
6395
6396 switch (rB(ctx->opcode)) {
6397 case 0:
6398 case 1:
6399 case 2:
6400 {
6401 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6402 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6403 t0, cpu_gpr[rA(ctx->opcode)]);
6404 tcg_temp_free_i32(t0);
6405 }
6406 break;
6407 default:
6408 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6409 break;
6410 }
6411 #endif /* defined(CONFIG_USER_ONLY) */
6412 }
6413
6414 /* tlbsx - tlbsx. */
6415 static void gen_tlbsx_440(DisasContext *ctx)
6416 {
6417 #if defined(CONFIG_USER_ONLY)
6418 GEN_PRIV;
6419 #else
6420 TCGv t0;
6421
6422 CHK_SV;
6423 t0 = tcg_temp_new();
6424 gen_addr_reg_index(ctx, t0);
6425 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6426 tcg_temp_free(t0);
6427 if (Rc(ctx->opcode)) {
6428 TCGLabel *l1 = gen_new_label();
6429 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6430 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6431 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6432 gen_set_label(l1);
6433 }
6434 #endif /* defined(CONFIG_USER_ONLY) */
6435 }
6436
6437 /* tlbwe */
6438 static void gen_tlbwe_440(DisasContext *ctx)
6439 {
6440 #if defined(CONFIG_USER_ONLY)
6441 GEN_PRIV;
6442 #else
6443 CHK_SV;
6444 switch (rB(ctx->opcode)) {
6445 case 0:
6446 case 1:
6447 case 2:
6448 {
6449 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6450 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6451 cpu_gpr[rS(ctx->opcode)]);
6452 tcg_temp_free_i32(t0);
6453 }
6454 break;
6455 default:
6456 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6457 break;
6458 }
6459 #endif /* defined(CONFIG_USER_ONLY) */
6460 }
6461
6462 /* TLB management - PowerPC BookE 2.06 implementation */
6463
6464 /* tlbre */
6465 static void gen_tlbre_booke206(DisasContext *ctx)
6466 {
6467 #if defined(CONFIG_USER_ONLY)
6468 GEN_PRIV;
6469 #else
6470 CHK_SV;
6471 gen_helper_booke206_tlbre(cpu_env);
6472 #endif /* defined(CONFIG_USER_ONLY) */
6473 }
6474
6475 /* tlbsx - tlbsx. */
6476 static void gen_tlbsx_booke206(DisasContext *ctx)
6477 {
6478 #if defined(CONFIG_USER_ONLY)
6479 GEN_PRIV;
6480 #else
6481 TCGv t0;
6482
6483 CHK_SV;
6484 if (rA(ctx->opcode)) {
6485 t0 = tcg_temp_new();
6486 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6487 } else {
6488 t0 = tcg_const_tl(0);
6489 }
6490
6491 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6492 gen_helper_booke206_tlbsx(cpu_env, t0);
6493 tcg_temp_free(t0);
6494 #endif /* defined(CONFIG_USER_ONLY) */
6495 }
6496
6497 /* tlbwe */
6498 static void gen_tlbwe_booke206(DisasContext *ctx)
6499 {
6500 #if defined(CONFIG_USER_ONLY)
6501 GEN_PRIV;
6502 #else
6503 CHK_SV;
6504 gen_helper_booke206_tlbwe(cpu_env);
6505 #endif /* defined(CONFIG_USER_ONLY) */
6506 }
6507
6508 static void gen_tlbivax_booke206(DisasContext *ctx)
6509 {
6510 #if defined(CONFIG_USER_ONLY)
6511 GEN_PRIV;
6512 #else
6513 TCGv t0;
6514
6515 CHK_SV;
6516 t0 = tcg_temp_new();
6517 gen_addr_reg_index(ctx, t0);
6518 gen_helper_booke206_tlbivax(cpu_env, t0);
6519 tcg_temp_free(t0);
6520 #endif /* defined(CONFIG_USER_ONLY) */
6521 }
6522
6523 static void gen_tlbilx_booke206(DisasContext *ctx)
6524 {
6525 #if defined(CONFIG_USER_ONLY)
6526 GEN_PRIV;
6527 #else
6528 TCGv t0;
6529
6530 CHK_SV;
6531 t0 = tcg_temp_new();
6532 gen_addr_reg_index(ctx, t0);
6533
6534 switch ((ctx->opcode >> 21) & 0x3) {
6535 case 0:
6536 gen_helper_booke206_tlbilx0(cpu_env, t0);
6537 break;
6538 case 1:
6539 gen_helper_booke206_tlbilx1(cpu_env, t0);
6540 break;
6541 case 3:
6542 gen_helper_booke206_tlbilx3(cpu_env, t0);
6543 break;
6544 default:
6545 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6546 break;
6547 }
6548
6549 tcg_temp_free(t0);
6550 #endif /* defined(CONFIG_USER_ONLY) */
6551 }
6552
6553
6554 /* wrtee */
6555 static void gen_wrtee(DisasContext *ctx)
6556 {
6557 #if defined(CONFIG_USER_ONLY)
6558 GEN_PRIV;
6559 #else
6560 TCGv t0;
6561
6562 CHK_SV;
6563 t0 = tcg_temp_new();
6564 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6565 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6566 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6567 tcg_temp_free(t0);
6568 /*
6569 * Stop translation to have a chance to raise an exception if we
6570 * just set msr_ee to 1
6571 */
6572 gen_stop_exception(ctx);
6573 #endif /* defined(CONFIG_USER_ONLY) */
6574 }
6575
6576 /* wrteei */
6577 static void gen_wrteei(DisasContext *ctx)
6578 {
6579 #if defined(CONFIG_USER_ONLY)
6580 GEN_PRIV;
6581 #else
6582 CHK_SV;
6583 if (ctx->opcode & 0x00008000) {
6584 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6585 /* Stop translation to have a chance to raise an exception */
6586 gen_stop_exception(ctx);
6587 } else {
6588 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6589 }
6590 #endif /* defined(CONFIG_USER_ONLY) */
6591 }
6592
6593 /* PowerPC 440 specific instructions */
6594
6595 /* dlmzb */
6596 static void gen_dlmzb(DisasContext *ctx)
6597 {
6598 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6599 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6600 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6601 tcg_temp_free_i32(t0);
6602 }
6603
6604 /* mbar replaces eieio on 440 */
6605 static void gen_mbar(DisasContext *ctx)
6606 {
6607 /* interpreted as no-op */
6608 }
6609
6610 /* msync replaces sync on 440 */
6611 static void gen_msync_4xx(DisasContext *ctx)
6612 {
6613 /* Only e500 seems to treat reserved bits as invalid */
6614 if ((ctx->insns_flags2 & PPC2_BOOKE206) &&
6615 (ctx->opcode & 0x03FFF801)) {
6616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6617 }
6618 /* otherwise interpreted as no-op */
6619 }
6620
6621 /* icbt */
6622 static void gen_icbt_440(DisasContext *ctx)
6623 {
6624 /*
6625 * interpreted as no-op
6626 * XXX: specification say this is treated as a load by the MMU but
6627 * does not generate any exception
6628 */
6629 }
6630
6631 /* Embedded.Processor Control */
6632
6633 static void gen_msgclr(DisasContext *ctx)
6634 {
6635 #if defined(CONFIG_USER_ONLY)
6636 GEN_PRIV;
6637 #else
6638 CHK_HV;
6639 if (is_book3s_arch2x(ctx)) {
6640 gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6641 } else {
6642 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6643 }
6644 #endif /* defined(CONFIG_USER_ONLY) */
6645 }
6646
6647 static void gen_msgsnd(DisasContext *ctx)
6648 {
6649 #if defined(CONFIG_USER_ONLY)
6650 GEN_PRIV;
6651 #else
6652 CHK_HV;
6653 if (is_book3s_arch2x(ctx)) {
6654 gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6655 } else {
6656 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6657 }
6658 #endif /* defined(CONFIG_USER_ONLY) */
6659 }
6660
6661 static void gen_msgsync(DisasContext *ctx)
6662 {
6663 #if defined(CONFIG_USER_ONLY)
6664 GEN_PRIV;
6665 #else
6666 CHK_HV;
6667 #endif /* defined(CONFIG_USER_ONLY) */
6668 /* interpreted as no-op */
6669 }
6670
6671 #if defined(TARGET_PPC64)
6672 static void gen_maddld(DisasContext *ctx)
6673 {
6674 TCGv_i64 t1 = tcg_temp_new_i64();
6675
6676 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6677 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
6678 tcg_temp_free_i64(t1);
6679 }
6680
6681 /* maddhd maddhdu */
6682 static void gen_maddhd_maddhdu(DisasContext *ctx)
6683 {
6684 TCGv_i64 lo = tcg_temp_new_i64();
6685 TCGv_i64 hi = tcg_temp_new_i64();
6686 TCGv_i64 t1 = tcg_temp_new_i64();
6687
6688 if (Rc(ctx->opcode)) {
6689 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6690 cpu_gpr[rB(ctx->opcode)]);
6691 tcg_gen_movi_i64(t1, 0);
6692 } else {
6693 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6694 cpu_gpr[rB(ctx->opcode)]);
6695 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6696 }
6697 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6698 cpu_gpr[rC(ctx->opcode)], t1);
6699 tcg_temp_free_i64(lo);
6700 tcg_temp_free_i64(hi);
6701 tcg_temp_free_i64(t1);
6702 }
6703 #endif /* defined(TARGET_PPC64) */
6704
6705 static void gen_tbegin(DisasContext *ctx)
6706 {
6707 if (unlikely(!ctx->tm_enabled)) {
6708 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6709 return;
6710 }
6711 gen_helper_tbegin(cpu_env);
6712 }
6713
6714 #define GEN_TM_NOOP(name) \
6715 static inline void gen_##name(DisasContext *ctx) \
6716 { \
6717 if (unlikely(!ctx->tm_enabled)) { \
6718 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6719 return; \
6720 } \
6721 /* \
6722 * Because tbegin always fails in QEMU, these user \
6723 * space instructions all have a simple implementation: \
6724 * \
6725 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6726 * = 0b0 || 0b00 || 0b0 \
6727 */ \
6728 tcg_gen_movi_i32(cpu_crf[0], 0); \
6729 }
6730
6731 GEN_TM_NOOP(tend);
6732 GEN_TM_NOOP(tabort);
6733 GEN_TM_NOOP(tabortwc);
6734 GEN_TM_NOOP(tabortwci);
6735 GEN_TM_NOOP(tabortdc);
6736 GEN_TM_NOOP(tabortdci);
6737 GEN_TM_NOOP(tsr);
6738
6739 static inline void gen_cp_abort(DisasContext *ctx)
6740 {
6741 /* Do Nothing */
6742 }
6743
6744 #define GEN_CP_PASTE_NOOP(name) \
6745 static inline void gen_##name(DisasContext *ctx) \
6746 { \
6747 /* \
6748 * Generate invalid exception until we have an \
6749 * implementation of the copy paste facility \
6750 */ \
6751 gen_invalid(ctx); \
6752 }
6753
6754 GEN_CP_PASTE_NOOP(copy)
6755 GEN_CP_PASTE_NOOP(paste)
6756
6757 static void gen_tcheck(DisasContext *ctx)
6758 {
6759 if (unlikely(!ctx->tm_enabled)) {
6760 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6761 return;
6762 }
6763 /*
6764 * Because tbegin always fails, the tcheck implementation is
6765 * simple:
6766 *
6767 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6768 * = 0b1 || 0b00 || 0b0
6769 */
6770 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6771 }
6772
6773 #if defined(CONFIG_USER_ONLY)
6774 #define GEN_TM_PRIV_NOOP(name) \
6775 static inline void gen_##name(DisasContext *ctx) \
6776 { \
6777 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6778 }
6779
6780 #else
6781
6782 #define GEN_TM_PRIV_NOOP(name) \
6783 static inline void gen_##name(DisasContext *ctx) \
6784 { \
6785 CHK_SV; \
6786 if (unlikely(!ctx->tm_enabled)) { \
6787 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6788 return; \
6789 } \
6790 /* \
6791 * Because tbegin always fails, the implementation is \
6792 * simple: \
6793 * \
6794 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6795 * = 0b0 || 0b00 | 0b0 \
6796 */ \
6797 tcg_gen_movi_i32(cpu_crf[0], 0); \
6798 }
6799
6800 #endif
6801
6802 GEN_TM_PRIV_NOOP(treclaim);
6803 GEN_TM_PRIV_NOOP(trechkpt);
6804
6805 static inline void get_fpr(TCGv_i64 dst, int regno)
6806 {
6807 tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
6808 }
6809
6810 static inline void set_fpr(int regno, TCGv_i64 src)
6811 {
6812 tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
6813 }
6814
6815 static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
6816 {
6817 tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high));
6818 }
6819
6820 static inline void set_avr64(int regno, TCGv_i64 src, bool high)
6821 {
6822 tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
6823 }
6824
6825 #include "translate/fp-impl.inc.c"
6826
6827 #include "translate/vmx-impl.inc.c"
6828
6829 #include "translate/vsx-impl.inc.c"
6830
6831 #include "translate/dfp-impl.inc.c"
6832
6833 #include "translate/spe-impl.inc.c"
6834
6835 /* Handles lfdp, lxsd, lxssp */
6836 static void gen_dform39(DisasContext *ctx)
6837 {
6838 switch (ctx->opcode & 0x3) {
6839 case 0: /* lfdp */
6840 if (ctx->insns_flags2 & PPC2_ISA205) {
6841 return gen_lfdp(ctx);
6842 }
6843 break;
6844 case 2: /* lxsd */
6845 if (ctx->insns_flags2 & PPC2_ISA300) {
6846 return gen_lxsd(ctx);
6847 }
6848 break;
6849 case 3: /* lxssp */
6850 if (ctx->insns_flags2 & PPC2_ISA300) {
6851 return gen_lxssp(ctx);
6852 }
6853 break;
6854 }
6855 return gen_invalid(ctx);
6856 }
6857
6858 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6859 static void gen_dform3D(DisasContext *ctx)
6860 {
6861 if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
6862 switch (ctx->opcode & 0x7) {
6863 case 1: /* lxv */
6864 if (ctx->insns_flags2 & PPC2_ISA300) {
6865 return gen_lxv(ctx);
6866 }
6867 break;
6868 case 5: /* stxv */
6869 if (ctx->insns_flags2 & PPC2_ISA300) {
6870 return gen_stxv(ctx);
6871 }
6872 break;
6873 }
6874 } else { /* DS-FORM */
6875 switch (ctx->opcode & 0x3) {
6876 case 0: /* stfdp */
6877 if (ctx->insns_flags2 & PPC2_ISA205) {
6878 return gen_stfdp(ctx);
6879 }
6880 break;
6881 case 2: /* stxsd */
6882 if (ctx->insns_flags2 & PPC2_ISA300) {
6883 return gen_stxsd(ctx);
6884 }
6885 break;
6886 case 3: /* stxssp */
6887 if (ctx->insns_flags2 & PPC2_ISA300) {
6888 return gen_stxssp(ctx);
6889 }
6890 break;
6891 }
6892 }
6893 return gen_invalid(ctx);
6894 }
6895
6896 static opcode_t opcodes[] = {
6897 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6898 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6899 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6900 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
6901 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6902 #if defined(TARGET_PPC64)
6903 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6904 #endif
6905 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6906 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6907 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6908 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6909 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6910 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6911 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6912 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6913 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6914 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6915 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6916 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6917 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6918 #if defined(TARGET_PPC64)
6919 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6920 #endif
6921 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6922 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6923 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6924 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6925 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6926 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6927 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6928 GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300),
6929 GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
6930 GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300),
6931 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6932 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6933 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6934 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6935 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6936 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6937 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6938 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6939 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6940 #if defined(TARGET_PPC64)
6941 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6942 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6943 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6944 GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300),
6945 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6946 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6947 #endif
6948 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6949 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6950 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6951 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6952 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6953 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6954 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6955 #if defined(TARGET_PPC64)
6956 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6957 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6958 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6959 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6960 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6961 GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6962 PPC_NONE, PPC2_ISA300),
6963 GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6964 PPC_NONE, PPC2_ISA300),
6965 #endif
6966 #if defined(TARGET_PPC64)
6967 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6968 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6969 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6970 #endif
6971 /* handles lfdp, lxsd, lxssp */
6972 GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6973 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6974 GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
6975 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6976 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6977 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6978 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6979 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6980 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6981 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
6982 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6983 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6984 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6985 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6986 GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
6987 GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
6988 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6989 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6990 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6991 #if defined(TARGET_PPC64)
6992 GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
6993 GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
6994 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6995 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6996 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6997 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6998 #endif
6999 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
7000 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
7001 GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300),
7002 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7003 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7004 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
7005 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
7006 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207),
7007 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
7008 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
7009 #if defined(TARGET_PPC64)
7010 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
7011 GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
7012 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7013 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7014 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7015 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
7016 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
7017 #endif
7018 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
7019 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
7020 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
7021 #if defined(TARGET_PPC64)
7022 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
7023 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
7024 #endif
7025 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
7026 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
7027 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
7028 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
7029 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
7030 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
7031 #if defined(TARGET_PPC64)
7032 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
7033 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
7034 GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
7035 #endif
7036 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
7037 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
7038 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
7039 GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
7040 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
7041 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
7042 GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
7043 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
7044 GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
7045 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
7046 GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
7047 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
7048 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
7049 GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
7050 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
7051 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC),
7052 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
7053 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
7054 GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206),
7055 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
7056 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
7057 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
7058 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
7059 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
7060 #if defined(TARGET_PPC64)
7061 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
7062 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
7063 PPC_SEGMENT_64B),
7064 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
7065 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
7066 PPC_SEGMENT_64B),
7067 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
7068 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
7069 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
7070 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
7071 #endif
7072 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
7073 /*
7074 * XXX Those instructions will need to be handled differently for
7075 * different ISA versions
7076 */
7077 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
7078 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
7079 GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
7080 GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
7081 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
7082 #if defined(TARGET_PPC64)
7083 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
7084 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
7085 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
7086 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
7087 #endif
7088 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
7089 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
7090 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
7091 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
7092 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
7093 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
7094 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
7095 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
7096 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
7097 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
7098 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
7099 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
7100 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
7101 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
7102 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
7103 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
7104 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
7105 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
7106 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
7107 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
7108 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
7109 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
7110 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
7111 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
7112 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
7113 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
7114 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
7115 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
7116 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
7117 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
7118 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
7119 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
7120 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
7121 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
7122 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
7123 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
7124 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
7125 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
7126 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
7127 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
7128 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
7129 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
7130 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
7131 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
7132 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
7133 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
7134 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
7135 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
7136 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
7137 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7138 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7139 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
7140 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
7141 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7142 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
7143 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
7144 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
7145 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
7146 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
7147 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
7148 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
7149 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
7150 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
7151 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
7152 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
7153 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
7154 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
7155 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
7156 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
7157 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
7158 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
7159 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
7160 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
7161 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
7162 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
7163 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
7164 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
7165 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
7166 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
7167 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
7168 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7169 PPC_NONE, PPC2_BOOKE206),
7170 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7171 PPC_NONE, PPC2_BOOKE206),
7172 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7173 PPC_NONE, PPC2_BOOKE206),
7174 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7175 PPC_NONE, PPC2_BOOKE206),
7176 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7177 PPC_NONE, PPC2_BOOKE206),
7178 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7179 PPC_NONE, PPC2_PRCNTL),
7180 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7181 PPC_NONE, PPC2_PRCNTL),
7182 GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7183 PPC_NONE, PPC2_PRCNTL),
7184 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
7185 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
7186 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
7187 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
7188 PPC_BOOKE, PPC2_BOOKE206),
7189 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE),
7190 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7191 PPC_BOOKE, PPC2_BOOKE206),
7192 GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7193 PPC_440_SPEC),
7194 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
7195 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
7196 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
7197 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
7198 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
7199 #if defined(TARGET_PPC64)
7200 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
7201 PPC2_ISA300),
7202 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
7203 #endif
7204
7205 #undef GEN_INT_ARITH_ADD
7206 #undef GEN_INT_ARITH_ADD_CONST
7207 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7208 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7209 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7210 add_ca, compute_ca, compute_ov) \
7211 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7212 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
7213 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
7214 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
7215 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
7216 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
7217 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
7218 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
7219 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
7220 GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300),
7221 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
7222 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
7223
7224 #undef GEN_INT_ARITH_DIVW
7225 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7226 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7227 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
7228 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
7229 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
7230 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
7231 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7232 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7233 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7234 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7235 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7236 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7237
7238 #if defined(TARGET_PPC64)
7239 #undef GEN_INT_ARITH_DIVD
7240 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7241 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7242 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
7243 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
7244 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
7245 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
7246
7247 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7248 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
7249 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7250 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
7251 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
7252 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
7253
7254 #undef GEN_INT_ARITH_MUL_HELPER
7255 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7256 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7257 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
7258 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
7259 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
7260 #endif
7261
7262 #undef GEN_INT_ARITH_SUBF
7263 #undef GEN_INT_ARITH_SUBF_CONST
7264 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7265 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7266 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7267 add_ca, compute_ca, compute_ov) \
7268 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7269 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
7270 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
7271 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
7272 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
7273 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
7274 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
7275 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
7276 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
7277 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
7278 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
7279
7280 #undef GEN_LOGICAL1
7281 #undef GEN_LOGICAL2
7282 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7283 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7284 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7285 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7286 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
7287 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
7288 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
7289 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
7290 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
7291 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
7292 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
7293 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
7294 #if defined(TARGET_PPC64)
7295 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
7296 #endif
7297
7298 #if defined(TARGET_PPC64)
7299 #undef GEN_PPC64_R2
7300 #undef GEN_PPC64_R4
7301 #define GEN_PPC64_R2(name, opc1, opc2) \
7302 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7303 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7304 PPC_64B)
7305 #define GEN_PPC64_R4(name, opc1, opc2) \
7306 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7307 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7308 PPC_64B), \
7309 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7310 PPC_64B), \
7311 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7312 PPC_64B)
7313 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
7314 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
7315 GEN_PPC64_R4(rldic, 0x1E, 0x04),
7316 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
7317 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
7318 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
7319 #endif
7320
7321 #undef GEN_LD
7322 #undef GEN_LDU
7323 #undef GEN_LDUX
7324 #undef GEN_LDX_E
7325 #undef GEN_LDS
7326 #define GEN_LD(name, ldop, opc, type) \
7327 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7328 #define GEN_LDU(name, ldop, opc, type) \
7329 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7330 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7331 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7332 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7333 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7334 #define GEN_LDS(name, ldop, op, type) \
7335 GEN_LD(name, ldop, op | 0x20, type) \
7336 GEN_LDU(name, ldop, op | 0x21, type) \
7337 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7338 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7339
7340 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
7341 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
7342 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
7343 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
7344 #if defined(TARGET_PPC64)
7345 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
7346 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
7347 GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
7348 GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
7349 GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
7350
7351 /* HV/P7 and later only */
7352 GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
7353 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
7354 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
7355 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
7356 #endif
7357 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
7358 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
7359
7360 /* External PID based load */
7361 #undef GEN_LDEPX
7362 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7363 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7364 0x00000001, PPC_NONE, PPC2_BOOKE206),
7365
7366 GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02)
7367 GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08)
7368 GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00)
7369 #if defined(TARGET_PPC64)
7370 GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00)
7371 #endif
7372
7373 #undef GEN_ST
7374 #undef GEN_STU
7375 #undef GEN_STUX
7376 #undef GEN_STX_E
7377 #undef GEN_STS
7378 #define GEN_ST(name, stop, opc, type) \
7379 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7380 #define GEN_STU(name, stop, opc, type) \
7381 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7382 #define GEN_STUX(name, stop, opc2, opc3, type) \
7383 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7384 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7385 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7386 #define GEN_STS(name, stop, op, type) \
7387 GEN_ST(name, stop, op | 0x20, type) \
7388 GEN_STU(name, stop, op | 0x21, type) \
7389 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7390 GEN_STX(name, stop, 0x17, op | 0x00, type)
7391
7392 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
7393 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
7394 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
7395 #if defined(TARGET_PPC64)
7396 GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B)
7397 GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B)
7398 GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
7399 GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST)
7400 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
7401 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
7402 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
7403 #endif
7404 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
7405 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
7406
7407 #undef GEN_STEPX
7408 #define GEN_STEPX(name, ldop, opc2, opc3) \
7409 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7410 0x00000001, PPC_NONE, PPC2_BOOKE206),
7411
7412 GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06)
7413 GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C)
7414 GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04)
7415 #if defined(TARGET_PPC64)
7416 GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04)
7417 #endif
7418
7419 #undef GEN_CRLOGIC
7420 #define GEN_CRLOGIC(name, tcg_op, opc) \
7421 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7422 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
7423 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
7424 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
7425 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
7426 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
7427 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
7428 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
7429 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
7430
7431 #undef GEN_MAC_HANDLER
7432 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7433 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7434 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
7435 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
7436 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
7437 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
7438 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
7439 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
7440 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
7441 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
7442 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
7443 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
7444 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
7445 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
7446 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
7447 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
7448 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
7449 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
7450 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
7451 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
7452 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
7453 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
7454 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
7455 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
7456 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
7457 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
7458 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
7459 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
7460 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
7461 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
7462 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
7463 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
7464 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
7465 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
7466 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
7467 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
7468 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
7469 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
7470 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
7471 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
7472 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
7473 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
7474 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
7475 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
7476
7477 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7478 PPC_NONE, PPC2_TM),
7479 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7480 PPC_NONE, PPC2_TM),
7481 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7482 PPC_NONE, PPC2_TM),
7483 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7484 PPC_NONE, PPC2_TM),
7485 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7486 PPC_NONE, PPC2_TM),
7487 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7488 PPC_NONE, PPC2_TM),
7489 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7490 PPC_NONE, PPC2_TM),
7491 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7492 PPC_NONE, PPC2_TM),
7493 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7494 PPC_NONE, PPC2_TM),
7495 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7496 PPC_NONE, PPC2_TM),
7497 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7498 PPC_NONE, PPC2_TM),
7499
7500 #include "translate/fp-ops.inc.c"
7501
7502 #include "translate/vmx-ops.inc.c"
7503
7504 #include "translate/vsx-ops.inc.c"
7505
7506 #include "translate/dfp-ops.inc.c"
7507
7508 #include "translate/spe-ops.inc.c"
7509 };
7510
7511 #include "helper_regs.h"
7512 #include "translate_init.inc.c"
7513
7514 /*****************************************************************************/
7515 /* Misc PowerPC helpers */
7516 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7517 {
7518 #define RGPL 4
7519 #define RFPL 4
7520
7521 PowerPCCPU *cpu = POWERPC_CPU(cs);
7522 CPUPPCState *env = &cpu->env;
7523 int i;
7524
7525 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7526 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7527 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7528 cs->cpu_index);
7529 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7530 TARGET_FMT_lx " iidx %d didx %d\n",
7531 env->msr, env->spr[SPR_HID0],
7532 env->hflags, env->immu_idx, env->dmmu_idx);
7533 #if !defined(NO_TIMER_DUMP)
7534 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7535 #if !defined(CONFIG_USER_ONLY)
7536 " DECR " TARGET_FMT_lu
7537 #endif
7538 "\n",
7539 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
7540 #if !defined(CONFIG_USER_ONLY)
7541 , cpu_ppc_load_decr(env)
7542 #endif
7543 );
7544 #endif
7545 for (i = 0; i < 32; i++) {
7546 if ((i & (RGPL - 1)) == 0) {
7547 qemu_fprintf(f, "GPR%02d", i);
7548 }
7549 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7550 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7551 qemu_fprintf(f, "\n");
7552 }
7553 }
7554 qemu_fprintf(f, "CR ");
7555 for (i = 0; i < 8; i++)
7556 qemu_fprintf(f, "%01x", env->crf[i]);
7557 qemu_fprintf(f, " [");
7558 for (i = 0; i < 8; i++) {
7559 char a = '-';
7560 if (env->crf[i] & 0x08) {
7561 a = 'L';
7562 } else if (env->crf[i] & 0x04) {
7563 a = 'G';
7564 } else if (env->crf[i] & 0x02) {
7565 a = 'E';
7566 }
7567 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7568 }
7569 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7570 env->reserve_addr);
7571
7572 if (flags & CPU_DUMP_FPU) {
7573 for (i = 0; i < 32; i++) {
7574 if ((i & (RFPL - 1)) == 0) {
7575 qemu_fprintf(f, "FPR%02d", i);
7576 }
7577 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7578 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7579 qemu_fprintf(f, "\n");
7580 }
7581 }
7582 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7583 }
7584
7585 #if !defined(CONFIG_USER_ONLY)
7586 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7587 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7588 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7589 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7590
7591 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7592 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7593 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7594 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7595
7596 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7597 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7598 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7599 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7600
7601 #if defined(TARGET_PPC64)
7602 if (env->excp_model == POWERPC_EXCP_POWER7 ||
7603 env->excp_model == POWERPC_EXCP_POWER8 ||
7604 env->excp_model == POWERPC_EXCP_POWER9) {
7605 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7606 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7607 }
7608 #endif
7609 if (env->excp_model == POWERPC_EXCP_BOOKE) {
7610 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7611 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7612 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7613 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7614
7615 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7616 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7617 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7618 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7619
7620 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7621 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7622 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7623 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7624
7625 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7626 " EPR " TARGET_FMT_lx "\n",
7627 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7628 env->spr[SPR_BOOKE_EPR]);
7629
7630 /* FSL-specific */
7631 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7632 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7633 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7634 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7635
7636 /*
7637 * IVORs are left out as they are large and do not change often --
7638 * they can be read with "p $ivor0", "p $ivor1", etc.
7639 */
7640 }
7641
7642 #if defined(TARGET_PPC64)
7643 if (env->flags & POWERPC_FLAG_CFAR) {
7644 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7645 }
7646 #endif
7647
7648 if (env->spr_cb[SPR_LPCR].name) {
7649 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7650 }
7651
7652 switch (env->mmu_model) {
7653 case POWERPC_MMU_32B:
7654 case POWERPC_MMU_601:
7655 case POWERPC_MMU_SOFT_6xx:
7656 case POWERPC_MMU_SOFT_74xx:
7657 #if defined(TARGET_PPC64)
7658 case POWERPC_MMU_64B:
7659 case POWERPC_MMU_2_03:
7660 case POWERPC_MMU_2_06:
7661 case POWERPC_MMU_2_07:
7662 case POWERPC_MMU_3_00:
7663 #endif
7664 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7665 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7666 }
7667 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7668 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7669 }
7670 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7671 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7672 break;
7673 case POWERPC_MMU_BOOKE206:
7674 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7675 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7676 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7677 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7678
7679 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7680 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7681 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7682 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7683
7684 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7685 " TLB1CFG " TARGET_FMT_lx "\n",
7686 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7687 env->spr[SPR_BOOKE_TLB1CFG]);
7688 break;
7689 default:
7690 break;
7691 }
7692 #endif
7693
7694 #undef RGPL
7695 #undef RFPL
7696 }
7697
7698 void ppc_cpu_dump_statistics(CPUState *cs, int flags)
7699 {
7700 #if defined(DO_PPC_STATISTICS)
7701 PowerPCCPU *cpu = POWERPC_CPU(cs);
7702 opc_handler_t **t1, **t2, **t3, *handler;
7703 int op1, op2, op3;
7704
7705 t1 = cpu->env.opcodes;
7706 for (op1 = 0; op1 < 64; op1++) {
7707 handler = t1[op1];
7708 if (is_indirect_opcode(handler)) {
7709 t2 = ind_table(handler);
7710 for (op2 = 0; op2 < 32; op2++) {
7711 handler = t2[op2];
7712 if (is_indirect_opcode(handler)) {
7713 t3 = ind_table(handler);
7714 for (op3 = 0; op3 < 32; op3++) {
7715 handler = t3[op3];
7716 if (handler->count == 0) {
7717 continue;
7718 }
7719 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
7720 "%016" PRIx64 " %" PRId64 "\n",
7721 op1, op2, op3, op1, (op3 << 5) | op2,
7722 handler->oname,
7723 handler->count, handler->count);
7724 }
7725 } else {
7726 if (handler->count == 0) {
7727 continue;
7728 }
7729 qemu_printf("%02x %02x (%02x %04d) %16s: "
7730 "%016" PRIx64 " %" PRId64 "\n",
7731 op1, op2, op1, op2, handler->oname,
7732 handler->count, handler->count);
7733 }
7734 }
7735 } else {
7736 if (handler->count == 0) {
7737 continue;
7738 }
7739 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
7740 " %" PRId64 "\n",
7741 op1, op1, handler->oname,
7742 handler->count, handler->count);
7743 }
7744 }
7745 #endif
7746 }
7747
7748 static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
7749 {
7750 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7751 CPUPPCState *env = cs->env_ptr;
7752 int bound;
7753
7754 ctx->exception = POWERPC_EXCP_NONE;
7755 ctx->spr_cb = env->spr_cb;
7756 ctx->pr = msr_pr;
7757 ctx->mem_idx = env->dmmu_idx;
7758 ctx->dr = msr_dr;
7759 #if !defined(CONFIG_USER_ONLY)
7760 ctx->hv = msr_hv || !env->has_hv_mode;
7761 #endif
7762 ctx->insns_flags = env->insns_flags;
7763 ctx->insns_flags2 = env->insns_flags2;
7764 ctx->access_type = -1;
7765 ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B);
7766 ctx->le_mode = !!(env->hflags & (1 << MSR_LE));
7767 ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE;
7768 ctx->flags = env->flags;
7769 #if defined(TARGET_PPC64)
7770 ctx->sf_mode = msr_is_64bit(env, env->msr);
7771 ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
7772 #endif
7773 ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B
7774 || env->mmu_model == POWERPC_MMU_601
7775 || (env->mmu_model & POWERPC_MMU_64B);
7776
7777 ctx->fpu_enabled = !!msr_fp;
7778 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) {
7779 ctx->spe_enabled = !!msr_spe;
7780 } else {
7781 ctx->spe_enabled = false;
7782 }
7783 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) {
7784 ctx->altivec_enabled = !!msr_vr;
7785 } else {
7786 ctx->altivec_enabled = false;
7787 }
7788 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
7789 ctx->vsx_enabled = !!msr_vsx;
7790 } else {
7791 ctx->vsx_enabled = false;
7792 }
7793 #if defined(TARGET_PPC64)
7794 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
7795 ctx->tm_enabled = !!msr_tm;
7796 } else {
7797 ctx->tm_enabled = false;
7798 }
7799 #endif
7800 ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
7801 if ((env->flags & POWERPC_FLAG_SE) && msr_se) {
7802 ctx->singlestep_enabled = CPU_SINGLE_STEP;
7803 } else {
7804 ctx->singlestep_enabled = 0;
7805 }
7806 if ((env->flags & POWERPC_FLAG_BE) && msr_be) {
7807 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7808 }
7809 if ((env->flags & POWERPC_FLAG_DE) && msr_de) {
7810 ctx->singlestep_enabled = 0;
7811 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
7812 if (dbcr0 & DBCR0_ICMP) {
7813 ctx->singlestep_enabled |= CPU_SINGLE_STEP;
7814 }
7815 if (dbcr0 & DBCR0_BRT) {
7816 ctx->singlestep_enabled |= CPU_BRANCH_STEP;
7817 }
7818
7819 }
7820 if (unlikely(ctx->base.singlestep_enabled)) {
7821 ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
7822 }
7823 #if defined(DO_SINGLE_STEP) && 0
7824 /* Single step trace mode */
7825 msr_se = 1;
7826 #endif
7827
7828 bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
7829 ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
7830 }
7831
7832 static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
7833 {
7834 }
7835
7836 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
7837 {
7838 tcg_gen_insn_start(dcbase->pc_next);
7839 }
7840
7841 static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
7842 const CPUBreakpoint *bp)
7843 {
7844 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7845
7846 gen_debug_exception(ctx);
7847 dcbase->is_jmp = DISAS_NORETURN;
7848 /*
7849 * The address covered by the breakpoint must be included in
7850 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
7851 * cleared -- thus we increment the PC here so that the logic
7852 * setting tb->size below does the right thing.
7853 */
7854 ctx->base.pc_next += 4;
7855 return true;
7856 }
7857
7858 static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
7859 {
7860 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7861 CPUPPCState *env = cs->env_ptr;
7862 opc_handler_t **table, *handler;
7863
7864 LOG_DISAS("----------------\n");
7865 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
7866 ctx->base.pc_next, ctx->mem_idx, (int)msr_ir);
7867
7868 if (unlikely(need_byteswap(ctx))) {
7869 ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next));
7870 } else {
7871 ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
7872 }
7873 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7874 ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode),
7875 opc3(ctx->opcode), opc4(ctx->opcode),
7876 ctx->le_mode ? "little" : "big");
7877 ctx->base.pc_next += 4;
7878 table = env->opcodes;
7879 handler = table[opc1(ctx->opcode)];
7880 if (is_indirect_opcode(handler)) {
7881 table = ind_table(handler);
7882 handler = table[opc2(ctx->opcode)];
7883 if (is_indirect_opcode(handler)) {
7884 table = ind_table(handler);
7885 handler = table[opc3(ctx->opcode)];
7886 if (is_indirect_opcode(handler)) {
7887 table = ind_table(handler);
7888 handler = table[opc4(ctx->opcode)];
7889 }
7890 }
7891 }
7892 /* Is opcode *REALLY* valid ? */
7893 if (unlikely(handler->handler == &gen_invalid)) {
7894 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7895 "%02x - %02x - %02x - %02x (%08x) "
7896 TARGET_FMT_lx " %d\n",
7897 opc1(ctx->opcode), opc2(ctx->opcode),
7898 opc3(ctx->opcode), opc4(ctx->opcode),
7899 ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir);
7900 } else {
7901 uint32_t inval;
7902
7903 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE)
7904 && Rc(ctx->opcode))) {
7905 inval = handler->inval2;
7906 } else {
7907 inval = handler->inval1;
7908 }
7909
7910 if (unlikely((ctx->opcode & inval) != 0)) {
7911 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7912 "%02x - %02x - %02x - %02x (%08x) "
7913 TARGET_FMT_lx "\n", ctx->opcode & inval,
7914 opc1(ctx->opcode), opc2(ctx->opcode),
7915 opc3(ctx->opcode), opc4(ctx->opcode),
7916 ctx->opcode, ctx->base.pc_next - 4);
7917 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7918 ctx->base.is_jmp = DISAS_NORETURN;
7919 return;
7920 }
7921 }
7922 (*(handler->handler))(ctx);
7923 #if defined(DO_PPC_STATISTICS)
7924 handler->count++;
7925 #endif
7926 /* Check trace mode exceptions */
7927 if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP &&
7928 (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) &&
7929 ctx->exception != POWERPC_SYSCALL &&
7930 ctx->exception != POWERPC_EXCP_TRAP &&
7931 ctx->exception != POWERPC_EXCP_BRANCH)) {
7932 uint32_t excp = gen_prep_dbgex(ctx);
7933 gen_exception_nip(ctx, excp, ctx->base.pc_next);
7934 }
7935
7936 if (tcg_check_temp_count()) {
7937 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7938 "temporaries\n", opc1(ctx->opcode), opc2(ctx->opcode),
7939 opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode);
7940 }
7941
7942 ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ?
7943 DISAS_NEXT : DISAS_NORETURN;
7944 }
7945
7946 static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
7947 {
7948 DisasContext *ctx = container_of(dcbase, DisasContext, base);
7949
7950 if (ctx->exception == POWERPC_EXCP_NONE) {
7951 gen_goto_tb(ctx, 0, ctx->base.pc_next);
7952 } else if (ctx->exception != POWERPC_EXCP_BRANCH) {
7953 if (unlikely(ctx->base.singlestep_enabled)) {
7954 gen_debug_exception(ctx);
7955 }
7956 /* Generate the return instruction */
7957 tcg_gen_exit_tb(NULL, 0);
7958 }
7959 }
7960
7961 static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
7962 {
7963 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
7964 log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
7965 }
7966
7967 static const TranslatorOps ppc_tr_ops = {
7968 .init_disas_context = ppc_tr_init_disas_context,
7969 .tb_start = ppc_tr_tb_start,
7970 .insn_start = ppc_tr_insn_start,
7971 .breakpoint_check = ppc_tr_breakpoint_check,
7972 .translate_insn = ppc_tr_translate_insn,
7973 .tb_stop = ppc_tr_tb_stop,
7974 .disas_log = ppc_tr_disas_log,
7975 };
7976
7977 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
7978 {
7979 DisasContext ctx;
7980
7981 translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
7982 }
7983
7984 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7985 target_ulong *data)
7986 {
7987 env->nip = data[0];
7988 }
armbru's QEMU hackery