target-avr32/cpu.h

   1 /*
   2  * AVR32 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Rabin Vincent
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #ifndef CPU_AVR32_H
  21 #define CPU_AVR32_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUState struct CPUAVR32State
  26
  27 #include "cpu-defs.h"
  28
  29 #define TARGET_HAS_ICE 1
  30
  31 #define EXCP_UNRECOVER           1 /* Unrecoverable exception */
  32 #define EXCP_TLB_MULTIPLE_HIT    2 /* TLB multiple hit */
  33 #define EXCP_BUS_ERROR_DATA      3 /* Bus error data fetch */
  34 #define EXCP_BUS_ERROR_INSN      4 /* Bus error instruction fetch */
  35 #define EXCP_NMI                 5 /* NMI */
  36 #define EXCP_INT3                6 /* Interrupt 3 request */
  37 #define EXCP_INT2                7 /* Interrupt 2 request */
  38 #define EXCP_INT1                8 /* Interrupt 1 request */
  39 #define EXCP_INT0                9 /* Interrupt 0 request */
  40 #define EXCP_INSN_ADDR          10 /* Instruction Address */
  41 #define EXCP_ITLB_MISS          11 /* ITLB Miss */
  42 #define EXCP_ITLB_PROTECT       12 /* ITLB Protection */
  43 #define EXCP_BKPT               13 /* Breakpoint */
  44 #define EXCP_ILLEGAL            14 /* Illegal Opcode */
  45 #define EXCP_UNIMP              15 /* Unimplemented instruction */
  46 #define EXCP_PRIVILEGE i        16 /* Privilege violation */
  47 #define EXCP_FP                 17 /* Floating-point */
  48 #define EXCP_COPROC             18 /* Coprocessor absent */
  49 #define EXCP_SVC_CALL           19 /* Supervisor call */
  50 #define EXCP_DTLB_READ_MISS     24
  51 #define EXCP_DTLB_WRITE_MISS    25
  52 #define EXCP_DTLB_READ_PROTECT  26
  53 #define EXCP_DTLB_WRITE_PROTECT 27
  54 #define EXCP_DTLB_MODIFIED      28
  55
  56 #ifdef CONFIG_USER_ONLY
  57 #define EXCP_SYSCALL            99
  58 #endif
  59
  60 #define ELF_MACHINE     EM_AVR32
  61
  62 #define NB_MMU_MODES 2
  63
  64 typedef struct AVR32Counter AVR32Counter;
  65
  66 typedef struct AVR32Tlb {
  67     uint32_t tlbehi;
  68     uint32_t tlbelo;
  69 } AVR32Tlb;
  70
  71 typedef struct CPUAVR32State {
  72     uint32_t regs[16];
  73     uint32_t sp_usr;
  74     uint32_t sp_sys;
  75     uint32_t sysreg[255];
  76
  77     uint32_t autovector[4];
  78     AVR32Tlb tlb[32];
  79     AVR32Counter *counter;
  80
  81         CPU_COMMON
  82 } CPUAVR32State;
  83
  84 #define SYSREG_SR       0   /* Status Register */
  85 #define SYSREG_EVBA     1   /* Exception Vector Base Address */
  86 #define SYSREG_ACBA     2   /* Application Call Base Address */
  87 #define SYSREG_CPUCR    3   /* CPU Control Register */
  88 #define SYSREG_ECR      4   /* Exception Cause Register */
  89 #define SYSREG_RSR_SUP  5   /* Return Status Register for Supervisor context */
  90 #define SYSREG_RSR_INT0 6   /* Return Status Register for INT 0 context */
  91 #define SYSREG_RSR_INT1 7   /* Return Status Register for INT 1 context */
  92 #define SYSREG_RSR_INT2 8   /* Return Status Register for INT 2 context */
  93 #define SYSREG_RSR_INT3 9   /* Return Status Register for INT 3 context */
  94 #define SYSREG_RSR_EX   10  /* Return Status Register for Exception context */
  95 #define SYSREG_RSR_NMI  11  /* Return Status Register for NMI context */
  96 #define SYSREG_RSR_DBG  12  /* Return Status Register for Debug Mode */
  97 #define SYSREG_RAR_SUP  13  /* Return Address Register for Supervisor context */
  98 #define SYSREG_RAR_INT0 14  /* Return Address Register for INT 0 context */
  99 #define SYSREG_RAR_INT1 15  /* Return Address Register for INT 1 context */
 100 #define SYSREG_RAR_INT2 16  /* Return Address Register for INT 2 context */
 101 #define SYSREG_RAR_INT3 17  /* Return Address Register for INT 3 context */
 102 #define SYSREG_RAR_EX   18  /* Return Address Register for Exception context */
 103 #define SYSREG_RAR_NMI  19  /* Return Address Register for NMI context */
 104 #define SYSREG_RAR_DBG  20  /* Return Address Register for Debug Mode */
 105 #define SYSREG_JECR     21  /* Java Exception Cause Register */
 106 #define SYSREG_JOSP     22  /* Java Operand Stack Pointer */
 107 #define SYSREG_JAVA_LV0 23  /* Java Local Variable 0 */
 108 #define SYSREG_JAVA_LV1 24  /* Java Local Variable 1 */
 109 #define SYSREG_JAVA_LV2 25  /* Java Local Variable 2 */
 110 #define SYSREG_JAVA_LV3 26  /* Java Local Variable 3 */
 111 #define SYSREG_JAVA_LV4 27  /* Java Local Variable 4 */
 112 #define SYSREG_JAVA_LV5 28  /* Java Local Variable 5 */
 113 #define SYSREG_JAVA_LV6 29  /* Java Local Variable 6 */
 114 #define SYSREG_JAVA_LV7 30  /* Java Local Variable 7 */
 115 #define SYSREG_JTBA     31  /* Java Trap Base Address */
 116 #define SYSREG_JBCR     32  /* Java Write Barrier Control Register */
 117 #define SYSREG_CONFIG0  64  /* Configuration register 0 */
 118 #define SYSREG_CONFIG1  65  /* Configuration register 1 */
 119 #define SYSREG_COUNT    66  /* Cycle Counter register */
 120 #define SYSREG_COMPARE  67  /* Compare register */
 121 #define SYSREG_TLBEHI   68  /* MMU TLB Entry High */
 122 #define SYSREG_TLBELO   69  /* MMU TLB Entry Low */
 123 #define SYSREG_PTBR     70  /* MMU Page Table Base Register */
 124 #define SYSREG_TLBEAR   71  /* MMU TLB Exception Address Register */
 125 #define SYSREG_MMUCR    72  /* MMU Control Register */
 126 #define SYSREG_TLBARLO  73  /* MMU TLB Accessed Register Low */
 127 #define SYSREG_TLBARHI  74  /* MMU TLB Accessed Register High */
 128 #define SYSREG_PCCNT    75  /* Performance Clock Counter */
 129 #define SYSREG_PCNT0    76  /* Performance Counter 0 */
 130 #define SYSREG_PCNT1    77  /* Performance Counter 1 */
 131 #define SYSREG_PCCR     78  /* Performance Counter Control Register */
 132 #define SYSREG_BEAR     79  /* Bus Error Address Register */
 133 #define SYSREG_MPUAR0   80  /* MPU Address Register region 0 */
 134 #define SYSREG_MPUAR1   81  /* MPU Address Register region 1 */
 135 #define SYSREG_MPUAR2   82  /* MPU Address Register region 2 */
 136 #define SYSREG_MPUAR3   83  /* MPU Address Register region 3 */
 137 #define SYSREG_MPUAR4   84  /* MPU Address Register region 4 */
 138 #define SYSREG_MPUAR5   85  /* MPU Address Register region 5 */
 139 #define SYSREG_MPUAR6   86  /* MPU Address Register region 6 */
 140 #define SYSREG_MPUAR7   87  /* MPU Address Register region 7 */
 141 #define SYSREG_MPUPSR0  88  /* MPU Privilege Select Register region 0 */
 142 #define SYSREG_MPUPSR1  89  /* MPU Privilege Select Register region 1 */
 143 #define SYSREG_MPUPSR2  90  /* MPU Privilege Select Register region 2 */
 144 #define SYSREG_MPUPSR3  91  /* MPU Privilege Select Register region 3 */
 145 #define SYSREG_MPUPSR4  92  /* MPU Privilege Select Register region 4 */
 146 #define SYSREG_MPUPSR5  93  /* MPU Privilege Select Register region 5 */
 147 #define SYSREG_MPUPSR6  94  /* MPU Privilege Select Register region 6 */
 148 #define SYSREG_MPUPSR7  95  /* MPU Privilege Select Register region 7 */
 149 #define SYSREG_MPUCRA   96  /* MPU Cacheable Register A */
 150 #define SYSREG_MPUCRB   97  /* MPU Cacheable Register B */
 151 #define SYSREG_MPUBRA   98  /* MPU Bufferable Register A */
 152 #define SYSREG_MPUBRB   99  /* MPU Bufferable Register B */
 153 #define SYSREG_MPUAPRA  100 /* MPU Access Permission Register A */
 154 #define SYSREG_MPUAPRB  101 /* MPU Access Permission Register B */
 155 #define SYSREG_MPUCR    102 /* MPU Control Register SYSREG_define   */
 156
 157 #define SR_C    (1 << 0)
 158 #define SR_Z    (1 << 1)
 159 #define SR_N    (1 << 2)
 160 #define SR_V    (1 << 3)
 161 #define SR_Q    (1 << 4)
 162 #define SR_L    (1 << 5)
 163 #define SR_T    (1 << 14)
 164 #define SR_R    (1 << 15)
 165 #define SR_GM   (1 << 16)
 166 #define SR_I0M  (1 << 17)
 167 #define SR_I1M  (1 << 18)
 168 #define SR_I2M  (1 << 19)
 169 #define SR_I3M  (1 << 20)
 170 #define SR_EM   (1 << 21)
 171 #define SR_M0   (1 << 22)
 172 #define SR_M1   (1 << 23)
 173 #define SR_M2   (1 << 24)
 174 #define SR_D    (1 << 26)
 175 #define SR_DM   (1 << 27)
 176 #define SR_J    (1 << 28)
 177 #define SR_H    (1 << 29)
 178
 179 #define SR_M        (0x7 << 22)
 180 #define SR_M_NMI    (SR_M2 | SR_M1 | SR_M0)
 181 #define SR_M_EXP    (SR_M2 | SR_M1 | 0)
 182 #define SR_M_INT3   (SR_M2 | 0     | SR_M0)
 183 #define SR_M_INT2   (SR_M2 | 0     | 0)
 184 #define SR_M_INT1   (0     | SR_M1 | SR_M0)
 185 #define SR_M_INT0   (0     | SR_M1 | 0)
 186 #define SR_M_SUP    (0     | 0     | SR_M0)
 187 #define SR_M_APP    (0     | 0     | 0)
 188
 189 #define TLBEHI_I            (1 << 8)
 190 #define TLBEHI_VALID        (1 << 9)
 191
 192 #define TLBELO_D            (1 << 1)
 193 #define TLBELO_AP_0         (1 << 4)
 194 #define TLBELO_AP_1         (1 << 5)
 195 #define TLBELO_AP_2         (1 << 6)
 196 #define TLBELO_G            (1 << 8)
 197
 198 #define MMUCR_ENABLE        (1 << 0)
 199 #define MMUCR_MODE_SHARED   (1 << 1)
 200 #define MMUCR_INVALIDATE    (1 << 2)
 201 #define MMUCR_NOT_FOUND     (1 << 3)
 202 #define MMUCR_SEGMENT_EN    (1 << 4)
 203 #define MMUCR_DLA_SHIFT     8
 204 #define MMUCR_DRP_SHIFT     14
 205 #define MMUCR_ILA_SHIFT     20
 206 #define MMUCR_IRP_SHIFT     26
 207
 208 #define MMUCR_DLA           (0x3f << 8)
 209 #define MMUCR_DRP           (0x3f << 14)
 210 #define MMUCR_ILA           (0x3f << 20)
 211 #define MMUCR_IRP           (0x3f << 26)
 212
 213 /* MMU modes definitions */
 214 #define MMU_MODE0_SUFFIX _kernel
 215 #define MMU_MODE1_SUFFIX _user
 216 #define MMU_USER_IDX 1
 217 static inline int cpu_mmu_index (CPUState *env)
 218 {
 219         return 0;
 220 }
 221
 222 #define TARGET_PAGE_BITS 12
 223
 224 #define cpu_init cpu_avr32_init
 225 #define cpu_exec cpu_avr32_exec
 226 #define cpu_gen_code cpu_avr32_gen_code
 227 #define cpu_signal_handler cpu_avr32_signal_handler
 228
 229 #include "cpu-all.h"
 230 #include "exec-all.h"
 231
 232 extern int cpu_avr32_signal_handler(int host_signum, void *pinfo, void *puc);
 233 extern int cpu_avr32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 234                                       int mmu_idx, int is_softmmu);
 235 #define cpu_handle_mmu_fault cpu_avr32_handle_mmu_fault
 236
 237 extern CPUAVR32State *cpu_avr32_init(const char *cpu_model);
 238
 239 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 240 {
 241     env->regs[15] = tb->pc;
 242 }
 243
 244 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 245                                         target_ulong *cs_base, int *flags)
 246 {
 247     *pc = env->regs[15];
 248 }
 249
 250 int cpu_avr32_exec(CPUAVR32State *s);
 251 void raise_exception(int tt);
 252 void avr32_tcg_init(void);
 253 void do_interrupt(CPUState *env);
 254
 255 uint32_t avr32_read_counter(void);
 256 void avr32_write_compare(uint32_t value);
 257
 258 #if defined(CONFIG_USER_ONLY)
 259 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 260 {
 261     if (newsp)
 262         env->regs[13] = newsp;
 263     env->regs[12] = 0;
 264 }
 265 #endif
 266
 267 #endif