target-avr32/helper.c

   1 /*
   2  *  AVR32 op helpers
   3  *
   4  *  Copyright (c) 2009 Rabin Vincent
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20
  21 #include <stdio.h>
  22 #include <stdlib.h>
  23 #include <string.h>
  24
  25 #include "cpu.h"
  26 #include "exec-all.h"
  27 #include "gdbstub.h"
  28 #include "qemu-common.h"
  29
  30 #ifdef DEBUG
  31 #define dbg(format...) fprintf(stderr, format)
  32 #else
  33 static inline int dbg(const char *format, ...)
  34 {
  35     return 0;
  36 }
  37 #endif
  38
  39 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
  40 {
  41     return addr;
  42 }
  43
  44 void cpu_reset(CPUAVR32State *env)
  45 {
  46     env->regs[15] = 0;
  47     env->sysreg[SYSREG_SR] = SR_M_SUP | SR_EM | SR_GM;
  48     env->sysreg[SYSREG_CONFIG0] = 0x01012510;
  49     env->sysreg[SYSREG_CONFIG1] = 0x00118020;
  50     env->sysreg[SYSREG_MMUCR] = MMUCR_SEGMENT_EN;
  51     env->sysreg[SYSREG_TLBARLO] = ~0u;
  52     env->sysreg[SYSREG_TLBARHI] = ~0u;
  53
  54     tlb_flush(env, 1);
  55 }
  56
  57 void do_interrupt(CPUState *env)
  58 {
  59     uint32_t offset;
  60     uint32_t mask;
  61     uint32_t value;
  62     int rar;
  63     int rsr;
  64
  65     dbg("$$ %s [0x%#x]\n", __func__, env->sysreg[SYSREG_SR]);
  66     dbg("%s, exception_index=%d\n", __func__, env->exception_index);
  67
  68     /* FIXME handled banked registers */
  69
  70     switch (env->exception_index) {
  71     case EXCP_ILLEGAL:
  72         offset = 0x20;
  73
  74         mask = SR_M | SR_J | SR_R | SR_EM | SR_GM;
  75         value = SR_M_EXP | SR_EM | SR_GM;
  76         rar = SYSREG_RAR_EX;
  77         rsr = SYSREG_RSR_EX;
  78         break;
  79
  80     case EXCP_DTLB_WRITE_PROTECT:
  81         offset = 0x40;
  82
  83         mask = SR_M | SR_J | SR_R | SR_EM | SR_GM;
  84         value = SR_M_EXP | SR_EM | SR_GM;
  85         rar = SYSREG_RAR_EX;
  86         rsr = SYSREG_RSR_EX;
  87         break;
  88
  89     case EXCP_DTLB_READ_MISS:
  90         offset = 0x60;
  91
  92         mask = SR_M | SR_J | SR_R | SR_EM | SR_GM;
  93         value = SR_M_EXP | SR_EM | SR_GM;
  94         rar = SYSREG_RAR_EX;
  95         rsr = SYSREG_RSR_EX;
  96         break;
  97
  98     case EXCP_DTLB_WRITE_MISS:
  99         offset = 0x70;
 100
 101         mask = SR_M | SR_J | SR_R | SR_EM | SR_GM;
 102         value = SR_M_EXP | SR_EM | SR_GM;
 103         rar = SYSREG_RAR_EX;
 104         rsr = SYSREG_RSR_EX;
 105         break;
 106
 107     case EXCP_ITLB_MISS:
 108         offset = 0x50;
 109
 110         mask = SR_M | SR_J | SR_R | SR_EM | SR_GM;
 111         value = SR_M_EXP | SR_EM | SR_GM;
 112         rar = SYSREG_RAR_EX;
 113         rsr = SYSREG_RSR_EX;
 114         break;
 115
 116     case EXCP_INT0:
 117         offset = env->autovector[0];
 118         mask = SR_M | SR_J | SR_R | SR_I0M;
 119         value = SR_M_INT0 | SR_I0M;
 120
 121         rar = SYSREG_RAR_INT0;
 122         rsr = SYSREG_RSR_INT0;
 123         break;
 124
 125     default:
 126         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
 127     }
 128
 129     env->sysreg[rsr] = env->sysreg[SYSREG_SR];
 130     env->sysreg[rar] = env->regs[15];
 131     env->sysreg[SYSREG_ECR] = offset >> 2;
 132
 133     if ((env->sysreg[SYSREG_SR] & SR_M) == SR_M_APP) {
 134         env->sp_usr = env->regs[13];
 135         env->regs[13] = env->sp_sys;
 136     }
 137
 138
 139     dbg("%s: offset: %x\n", __func__, offset);
 140     dbg("%s: rar: %x\n", __func__, env->sysreg[rar]);
 141     dbg("%s: SYSREG_RAR_EX: %x\n", __func__, env->sysreg[SYSREG_RAR_EX]);
 142
 143     env->sysreg[SYSREG_SR] = (env->sysreg[SYSREG_SR] &~ mask) | value;
 144     env->regs[15] = env->sysreg[SYSREG_EVBA] + offset;
 145
 146     env->exception_index = 0;
 147
 148     {
 149         int i;
 150
 151         for (i = 0; i < 16; i++)
 152             dbg("env->regs[%d] = 0x%08x\n", i, env->regs[i]);
 153         dbg("env->sp_usr = 0x%08x\n", env->sp_usr);
 154         dbg("env->sp_sys = 0x%08x\n", env->sp_sys);
 155         dbg("env->sysreg[SYSREG_SR] = 0x%08x\n", env->sysreg[SYSREG_SR]);
 156     }
 157 }
 158