hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pci.h"
  27
  28 #define VERBOSE
  29 #define EMBED_STDVGA
  30 #undef DIRECT_VRAM
  31 #define HW_RECT_ACCEL
  32 #define HW_FILL_ACCEL
  33 #define HW_MOUSE_ACCEL
  34
  35 #ifdef EMBED_STDVGA
  36 # include "vga_int.h"
  37 #endif
  38
  39 struct vmsvga_state_s {
  40 #ifdef EMBED_STDVGA
  41     VGA_STATE_COMMON
  42 #endif
  43
  44     int width;
  45     int height;
  46     int invalidated;
  47     int depth;
  48     int bypp;
  49     int enable;
  50     int config;
  51     struct {
  52         int id;
  53         int x;
  54         int y;
  55         int on;
  56     } cursor;
  57
  58 #ifndef EMBED_STDVGA
  59     DisplayState *ds;
  60     int vram_size;
  61     ram_addr_t vram_offset;
  62 #endif
  63     uint8_t *vram;
  64     target_phys_addr_t vram_base;
  65
  66     int index;
  67     int scratch_size;
  68     uint32_t *scratch;
  69     int new_width;
  70     int new_height;
  71     uint32_t guest;
  72     uint32_t svgaid;
  73     uint32_t wred;
  74     uint32_t wgreen;
  75     uint32_t wblue;
  76     int syncing;
  77     int fb_size;
  78
  79     union {
  80         uint32_t *fifo;
  81         struct __attribute__((__packed__)) {
  82             uint32_t min;
  83             uint32_t max;
  84             uint32_t next_cmd;
  85             uint32_t stop;
  86             /* Add registers here when adding capabilities.  */
  87             uint32_t fifo[0];
  88         } *cmd;
  89     };
  90
  91 #define REDRAW_FIFO_LEN 512
  92     struct vmsvga_rect_s {
  93         int x, y, w, h;
  94     } redraw_fifo[REDRAW_FIFO_LEN];
  95     int redraw_fifo_first, redraw_fifo_last;
  96 };
  97
  98 struct pci_vmsvga_state_s {
  99     PCIDevice card;
 100     struct vmsvga_state_s chip;
 101 };
 102
 103 #define SVGA_MAGIC              0x900000UL
 104 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 105 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 106 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 107 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 108
 109 #define SVGA_LEGACY_BASE_PORT   0x4560
 110 #define SVGA_INDEX_PORT         0x0
 111 #define SVGA_VALUE_PORT         0x1
 112 #define SVGA_BIOS_PORT          0x2
 113
 114 #define SVGA_VERSION_2
 115
 116 #ifdef SVGA_VERSION_2
 117 # define SVGA_ID                SVGA_ID_2
 118 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 119 # define SVGA_IO_MUL            1
 120 # define SVGA_FIFO_SIZE         0x10000
 121 # define SVGA_MEM_BASE          0xe0000000
 122 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 123 #else
 124 # define SVGA_ID                SVGA_ID_1
 125 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 126 # define SVGA_IO_MUL            4
 127 # define SVGA_FIFO_SIZE         0x10000
 128 # define SVGA_MEM_BASE          0xe0000000
 129 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 130 #endif
 131
 132 enum {
 133     /* ID 0, 1 and 2 registers */
 134     SVGA_REG_ID = 0,
 135     SVGA_REG_ENABLE = 1,
 136     SVGA_REG_WIDTH = 2,
 137     SVGA_REG_HEIGHT = 3,
 138     SVGA_REG_MAX_WIDTH = 4,
 139     SVGA_REG_MAX_HEIGHT = 5,
 140     SVGA_REG_DEPTH = 6,
 141     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 142     SVGA_REG_PSEUDOCOLOR = 8,
 143     SVGA_REG_RED_MASK = 9,
 144     SVGA_REG_GREEN_MASK = 10,
 145     SVGA_REG_BLUE_MASK = 11,
 146     SVGA_REG_BYTES_PER_LINE = 12,
 147     SVGA_REG_FB_START = 13,
 148     SVGA_REG_FB_OFFSET = 14,
 149     SVGA_REG_VRAM_SIZE = 15,
 150     SVGA_REG_FB_SIZE = 16,
 151
 152     /* ID 1 and 2 registers */
 153     SVGA_REG_CAPABILITIES = 17,
 154     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 155     SVGA_REG_MEM_SIZE = 19,
 156     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 157     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 158     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 159     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 160     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 161     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 162     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 163     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 164     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 165     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 166     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 167     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 168     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 169
 170     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 171     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 172     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 173 };
 174
 175 #define SVGA_CAP_NONE                   0
 176 #define SVGA_CAP_RECT_FILL              (1 << 0)
 177 #define SVGA_CAP_RECT_COPY              (1 << 1)
 178 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 179 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 180 #define SVGA_CAP_RASTER_OP              (1 << 4)
 181 #define SVGA_CAP_CURSOR                 (1 << 5)
 182 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 183 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 184 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 185 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 186 #define SVGA_CAP_GLYPH                  (1 << 10)
 187 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 188 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 189 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 190 #define SVGA_CAP_3D                     (1 << 14)
 191 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 192 #define SVGA_CAP_MULTIMON               (1 << 16)
 193 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 194
 195 /*
 196  * FIFO offsets (seen as an array of 32-bit words)
 197  */
 198 enum {
 199     /*
 200      * The original defined FIFO offsets
 201      */
 202     SVGA_FIFO_MIN = 0,
 203     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 204     SVGA_FIFO_NEXT_CMD,
 205     SVGA_FIFO_STOP,
 206
 207     /*
 208      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 209      */
 210     SVGA_FIFO_CAPABILITIES = 4,
 211     SVGA_FIFO_FLAGS,
 212     SVGA_FIFO_FENCE,
 213     SVGA_FIFO_3D_HWVERSION,
 214     SVGA_FIFO_PITCHLOCK,
 215 };
 216
 217 #define SVGA_FIFO_CAP_NONE              0
 218 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 219 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 220 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 221
 222 #define SVGA_FIFO_FLAG_NONE             0
 223 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 224
 225 /* These values can probably be changed arbitrarily.  */
 226 #define SVGA_SCRATCH_SIZE               0x8000
 227 #define SVGA_MAX_WIDTH                  2360
 228 #define SVGA_MAX_HEIGHT                 1770
 229
 230 #ifdef VERBOSE
 231 # define GUEST_OS_BASE          0x5001
 232 static const char *vmsvga_guest_id[] = {
 233     [0x00] = "Dos",
 234     [0x01] = "Windows 3.1",
 235     [0x02] = "Windows 95",
 236     [0x03] = "Windows 98",
 237     [0x04] = "Windows ME",
 238     [0x05] = "Windows NT",
 239     [0x06] = "Windows 2000",
 240     [0x07] = "Linux",
 241     [0x08] = "OS/2",
 242     [0x09] = "an unknown OS",
 243     [0x0a] = "BSD",
 244     [0x0b] = "Whistler",
 245     [0x0c] = "an unknown OS",
 246     [0x0d] = "an unknown OS",
 247     [0x0e] = "an unknown OS",
 248     [0x0f] = "an unknown OS",
 249     [0x10] = "an unknown OS",
 250     [0x11] = "an unknown OS",
 251     [0x12] = "an unknown OS",
 252     [0x13] = "an unknown OS",
 253     [0x14] = "an unknown OS",
 254     [0x15] = "Windows 2003",
 255 };
 256 #endif
 257
 258 enum {
 259     SVGA_CMD_INVALID_CMD = 0,
 260     SVGA_CMD_UPDATE = 1,
 261     SVGA_CMD_RECT_FILL = 2,
 262     SVGA_CMD_RECT_COPY = 3,
 263     SVGA_CMD_DEFINE_BITMAP = 4,
 264     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 265     SVGA_CMD_DEFINE_PIXMAP = 6,
 266     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 267     SVGA_CMD_RECT_BITMAP_FILL = 8,
 268     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 269     SVGA_CMD_RECT_BITMAP_COPY = 10,
 270     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 271     SVGA_CMD_FREE_OBJECT = 12,
 272     SVGA_CMD_RECT_ROP_FILL = 13,
 273     SVGA_CMD_RECT_ROP_COPY = 14,
 274     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 275     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 276     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 277     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 278     SVGA_CMD_DEFINE_CURSOR = 19,
 279     SVGA_CMD_DISPLAY_CURSOR = 20,
 280     SVGA_CMD_MOVE_CURSOR = 21,
 281     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 282     SVGA_CMD_DRAW_GLYPH = 23,
 283     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 284     SVGA_CMD_UPDATE_VERBOSE = 25,
 285     SVGA_CMD_SURFACE_FILL = 26,
 286     SVGA_CMD_SURFACE_COPY = 27,
 287     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 288     SVGA_CMD_FRONT_ROP_FILL = 29,
 289     SVGA_CMD_FENCE = 30,
 290 };
 291
 292 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 293 enum {
 294     SVGA_CURSOR_ON_HIDE = 0,
 295     SVGA_CURSOR_ON_SHOW = 1,
 296     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 297     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 298 };
 299
 300 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 301                 int x, int y, int w, int h)
 302 {
 303 #ifndef DIRECT_VRAM
 304     int line;
 305     int bypl;
 306     int width;
 307     int start;
 308     uint8_t *src;
 309     uint8_t *dst;
 310
 311     if (x + w > s->width) {
 312         fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
 313                         __FUNCTION__, x, w);
 314         x = MIN(x, s->width);
 315         w = s->width - x;
 316     }
 317
 318     if (y + h > s->height) {
 319         fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
 320                         __FUNCTION__, y, h);
 321         y = MIN(y, s->height);
 322         h = s->height - y;
 323     }
 324
 325     line = h;
 326     bypl = s->bypp * s->width;
 327     width = s->bypp * w;
 328     start = s->bypp * x + bypl * y;
 329     src = s->vram + start;
 330     dst = ds_get_data(s->ds) + start;
 331
 332     for (; line > 0; line --, src += bypl, dst += bypl)
 333         memcpy(dst, src, width);
 334 #endif
 335
 336     dpy_update(s->ds, x, y, w, h);
 337 }
 338
 339 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 340 {
 341 #ifndef DIRECT_VRAM
 342     memcpy(ds_get_data(s->ds), s->vram, s->bypp * s->width * s->height);
 343 #endif
 344
 345     dpy_update(s->ds, 0, 0, s->width, s->height);
 346 }
 347
 348 #ifdef DIRECT_VRAM
 349 # define vmsvga_update_rect_delayed     vmsvga_update_rect
 350 #else
 351 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 352                 int x, int y, int w, int h)
 353 {
 354     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 355     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 356     rect->x = x;
 357     rect->y = y;
 358     rect->w = w;
 359     rect->h = h;
 360 }
 361 #endif
 362
 363 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 364 {
 365     struct vmsvga_rect_s *rect;
 366     if (s->invalidated) {
 367         s->redraw_fifo_first = s->redraw_fifo_last;
 368         return;
 369     }
 370     /* Overlapping region updates can be optimised out here - if someone
 371      * knows a smart algorithm to do that, please share.  */
 372     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 373         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 374         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 375         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 376     }
 377 }
 378
 379 #ifdef HW_RECT_ACCEL
 380 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 381                 int x0, int y0, int x1, int y1, int w, int h)
 382 {
 383 # ifdef DIRECT_VRAM
 384     uint8_t *vram = ds_get_data(s->ds);
 385 # else
 386     uint8_t *vram = s->vram;
 387 # endif
 388     int bypl = s->bypp * s->width;
 389     int width = s->bypp * w;
 390     int line = h;
 391     uint8_t *ptr[2];
 392
 393 # ifdef DIRECT_VRAM
 394     if (s->ds->dpy_copy)
 395         qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
 396     else
 397 # endif
 398     {
 399         if (y1 > y0) {
 400             ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 401             ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 402             for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
 403                 memmove(ptr[1], ptr[0], width);
 404         } else {
 405             ptr[0] = vram + s->bypp * x0 + bypl * y0;
 406             ptr[1] = vram + s->bypp * x1 + bypl * y1;
 407             for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
 408                 memmove(ptr[1], ptr[0], width);
 409         }
 410     }
 411
 412     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 413 }
 414 #endif
 415
 416 #ifdef HW_FILL_ACCEL
 417 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 418                 uint32_t c, int x, int y, int w, int h)
 419 {
 420 # ifdef DIRECT_VRAM
 421     uint8_t *vram = ds_get_data(s->ds);
 422 # else
 423     uint8_t *vram = s->vram;
 424 # endif
 425     int bypp = s->bypp;
 426     int bypl = bypp * s->width;
 427     int width = bypp * w;
 428     int line = h;
 429     int column;
 430     uint8_t *fst = vram + bypp * x + bypl * y;
 431     uint8_t *dst;
 432     uint8_t *src;
 433     uint8_t col[4];
 434
 435 # ifdef DIRECT_VRAM
 436     if (s->ds->dpy_fill)
 437         s->ds->dpy_fill(s->ds, x, y, w, h, c);
 438     else
 439 # endif
 440     {
 441         col[0] = c;
 442         col[1] = c >> 8;
 443         col[2] = c >> 16;
 444         col[3] = c >> 24;
 445
 446         if (line --) {
 447             dst = fst;
 448             src = col;
 449             for (column = width; column > 0; column --) {
 450                 *(dst ++) = *(src ++);
 451                 if (src - col == bypp)
 452                     src = col;
 453             }
 454             dst = fst;
 455             for (; line > 0; line --) {
 456                 dst += bypl;
 457                 memcpy(dst, fst, width);
 458             }
 459         }
 460     }
 461
 462     vmsvga_update_rect_delayed(s, x, y, w, h);
 463 }
 464 #endif
 465
 466 struct vmsvga_cursor_definition_s {
 467     int width;
 468     int height;
 469     int id;
 470     int bpp;
 471     int hot_x;
 472     int hot_y;
 473     uint32_t mask[1024];
 474     uint32_t image[1024];
 475 };
 476
 477 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 478 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 479
 480 #ifdef HW_MOUSE_ACCEL
 481 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 482                 struct vmsvga_cursor_definition_s *c)
 483 {
 484     int i;
 485     for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
 486         c->mask[i] = ~c->mask[i];
 487
 488     if (s->ds->cursor_define)
 489         s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
 490                         (uint8_t *) c->image, (uint8_t *) c->mask);
 491 }
 492 #endif
 493
 494 #define CMD(f)  le32_to_cpu(s->cmd->f)
 495
 496 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
 497 {
 498     if (!s->config || !s->enable)
 499         return 1;
 500     return (s->cmd->next_cmd == s->cmd->stop);
 501 }
 502
 503 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
 504 {
 505     uint32_t cmd = s->fifo[CMD(stop) >> 2];
 506     s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
 507     if (CMD(stop) >= CMD(max))
 508         s->cmd->stop = s->cmd->min;
 509     return cmd;
 510 }
 511
 512 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 513 {
 514     return le32_to_cpu(vmsvga_fifo_read_raw(s));
 515 }
 516
 517 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 518 {
 519     uint32_t cmd, colour;
 520     int args = 0;
 521     int x, y, dx, dy, width, height;
 522     struct vmsvga_cursor_definition_s cursor;
 523     while (!vmsvga_fifo_empty(s))
 524         switch (cmd = vmsvga_fifo_read(s)) {
 525         case SVGA_CMD_UPDATE:
 526         case SVGA_CMD_UPDATE_VERBOSE:
 527             x = vmsvga_fifo_read(s);
 528             y = vmsvga_fifo_read(s);
 529             width = vmsvga_fifo_read(s);
 530             height = vmsvga_fifo_read(s);
 531             vmsvga_update_rect_delayed(s, x, y, width, height);
 532             break;
 533
 534         case SVGA_CMD_RECT_FILL:
 535             colour = vmsvga_fifo_read(s);
 536             x = vmsvga_fifo_read(s);
 537             y = vmsvga_fifo_read(s);
 538             width = vmsvga_fifo_read(s);
 539             height = vmsvga_fifo_read(s);
 540 #ifdef HW_FILL_ACCEL
 541             vmsvga_fill_rect(s, colour, x, y, width, height);
 542             break;
 543 #else
 544             goto badcmd;
 545 #endif
 546
 547         case SVGA_CMD_RECT_COPY:
 548             x = vmsvga_fifo_read(s);
 549             y = vmsvga_fifo_read(s);
 550             dx = vmsvga_fifo_read(s);
 551             dy = vmsvga_fifo_read(s);
 552             width = vmsvga_fifo_read(s);
 553             height = vmsvga_fifo_read(s);
 554 #ifdef HW_RECT_ACCEL
 555             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 556             break;
 557 #else
 558             goto badcmd;
 559 #endif
 560
 561         case SVGA_CMD_DEFINE_CURSOR:
 562             cursor.id = vmsvga_fifo_read(s);
 563             cursor.hot_x = vmsvga_fifo_read(s);
 564             cursor.hot_y = vmsvga_fifo_read(s);
 565             cursor.width = x = vmsvga_fifo_read(s);
 566             cursor.height = y = vmsvga_fifo_read(s);
 567             vmsvga_fifo_read(s);
 568             cursor.bpp = vmsvga_fifo_read(s);
 569             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 570                 cursor.mask[args] = vmsvga_fifo_read_raw(s);
 571             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 572                 cursor.image[args] = vmsvga_fifo_read_raw(s);
 573 #ifdef HW_MOUSE_ACCEL
 574             vmsvga_cursor_define(s, &cursor);
 575             break;
 576 #else
 577             args = 0;
 578             goto badcmd;
 579 #endif
 580
 581         /*
 582          * Other commands that we at least know the number of arguments
 583          * for so we can avoid FIFO desync if driver uses them illegally.
 584          */
 585         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 586             vmsvga_fifo_read(s);
 587             vmsvga_fifo_read(s);
 588             vmsvga_fifo_read(s);
 589             x = vmsvga_fifo_read(s);
 590             y = vmsvga_fifo_read(s);
 591             args = x * y;
 592             goto badcmd;
 593         case SVGA_CMD_RECT_ROP_FILL:
 594             args = 6;
 595             goto badcmd;
 596         case SVGA_CMD_RECT_ROP_COPY:
 597             args = 7;
 598             goto badcmd;
 599         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 600             vmsvga_fifo_read(s);
 601             vmsvga_fifo_read(s);
 602             args = 7 + (vmsvga_fifo_read(s) >> 2);
 603             goto badcmd;
 604         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 605             args = 12;
 606             goto badcmd;
 607
 608         /*
 609          * Other commands that are not listed as depending on any
 610          * CAPABILITIES bits, but are not described in the README either.
 611          */
 612         case SVGA_CMD_SURFACE_FILL:
 613         case SVGA_CMD_SURFACE_COPY:
 614         case SVGA_CMD_FRONT_ROP_FILL:
 615         case SVGA_CMD_FENCE:
 616         case SVGA_CMD_INVALID_CMD:
 617             break; /* Nop */
 618
 619         default:
 620         badcmd:
 621             while (args --)
 622                 vmsvga_fifo_read(s);
 623             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 624                             __FUNCTION__, cmd);
 625             break;
 626         }
 627
 628     s->syncing = 0;
 629 }
 630
 631 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 632 {
 633     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 634     return s->index;
 635 }
 636
 637 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 638 {
 639     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 640     s->index = index;
 641 }
 642
 643 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 644 {
 645     uint32_t caps;
 646     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 647     switch (s->index) {
 648     case SVGA_REG_ID:
 649         return s->svgaid;
 650
 651     case SVGA_REG_ENABLE:
 652         return s->enable;
 653
 654     case SVGA_REG_WIDTH:
 655         return s->width;
 656
 657     case SVGA_REG_HEIGHT:
 658         return s->height;
 659
 660     case SVGA_REG_MAX_WIDTH:
 661         return SVGA_MAX_WIDTH;
 662
 663     case SVGA_REG_MAX_HEIGHT:
 664         return SVGA_MAX_HEIGHT;
 665
 666     case SVGA_REG_DEPTH:
 667         return s->depth;
 668
 669     case SVGA_REG_BITS_PER_PIXEL:
 670         return (s->depth + 7) & ~7;
 671
 672     case SVGA_REG_PSEUDOCOLOR:
 673         return 0x0;
 674
 675     case SVGA_REG_RED_MASK:
 676         return s->wred;
 677     case SVGA_REG_GREEN_MASK:
 678         return s->wgreen;
 679     case SVGA_REG_BLUE_MASK:
 680         return s->wblue;
 681
 682     case SVGA_REG_BYTES_PER_LINE:
 683         return ((s->depth + 7) >> 3) * s->new_width;
 684
 685     case SVGA_REG_FB_START:
 686         return s->vram_base;
 687
 688     case SVGA_REG_FB_OFFSET:
 689         return 0x0;
 690
 691     case SVGA_REG_VRAM_SIZE:
 692         return s->vram_size - SVGA_FIFO_SIZE;
 693
 694     case SVGA_REG_FB_SIZE:
 695         return s->fb_size;
 696
 697     case SVGA_REG_CAPABILITIES:
 698         caps = SVGA_CAP_NONE;
 699 #ifdef HW_RECT_ACCEL
 700         caps |= SVGA_CAP_RECT_COPY;
 701 #endif
 702 #ifdef HW_FILL_ACCEL
 703         caps |= SVGA_CAP_RECT_FILL;
 704 #endif
 705 #ifdef HW_MOUSE_ACCEL
 706         if (s->ds->mouse_set)
 707             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 708                     SVGA_CAP_CURSOR_BYPASS;
 709 #endif
 710         return caps;
 711
 712     case SVGA_REG_MEM_START:
 713         return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
 714
 715     case SVGA_REG_MEM_SIZE:
 716         return SVGA_FIFO_SIZE;
 717
 718     case SVGA_REG_CONFIG_DONE:
 719         return s->config;
 720
 721     case SVGA_REG_SYNC:
 722     case SVGA_REG_BUSY:
 723         return s->syncing;
 724
 725     case SVGA_REG_GUEST_ID:
 726         return s->guest;
 727
 728     case SVGA_REG_CURSOR_ID:
 729         return s->cursor.id;
 730
 731     case SVGA_REG_CURSOR_X:
 732         return s->cursor.x;
 733
 734     case SVGA_REG_CURSOR_Y:
 735         return s->cursor.x;
 736
 737     case SVGA_REG_CURSOR_ON:
 738         return s->cursor.on;
 739
 740     case SVGA_REG_HOST_BITS_PER_PIXEL:
 741         return (s->depth + 7) & ~7;
 742
 743     case SVGA_REG_SCRATCH_SIZE:
 744         return s->scratch_size;
 745
 746     case SVGA_REG_MEM_REGS:
 747     case SVGA_REG_NUM_DISPLAYS:
 748     case SVGA_REG_PITCHLOCK:
 749     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 750         return 0;
 751
 752     default:
 753         if (s->index >= SVGA_SCRATCH_BASE &&
 754                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 755             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 756         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 757     }
 758
 759     return 0;
 760 }
 761
 762 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 763 {
 764     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 765     switch (s->index) {
 766     case SVGA_REG_ID:
 767         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 768             s->svgaid = value;
 769         break;
 770
 771     case SVGA_REG_ENABLE:
 772         s->enable = value;
 773         s->config &= !!value;
 774         s->width = -1;
 775         s->height = -1;
 776         s->invalidated = 1;
 777 #ifdef EMBED_STDVGA
 778         s->invalidate(opaque);
 779 #endif
 780         if (s->enable)
 781             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 782         break;
 783
 784     case SVGA_REG_WIDTH:
 785         s->new_width = value;
 786         s->invalidated = 1;
 787         break;
 788
 789     case SVGA_REG_HEIGHT:
 790         s->new_height = value;
 791         s->invalidated = 1;
 792         break;
 793
 794     case SVGA_REG_DEPTH:
 795     case SVGA_REG_BITS_PER_PIXEL:
 796         if (value != s->depth) {
 797             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 798             s->config = 0;
 799         }
 800         break;
 801
 802     case SVGA_REG_CONFIG_DONE:
 803         if (value) {
 804             s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
 805             /* Check range and alignment.  */
 806             if ((CMD(min) | CMD(max) |
 807                         CMD(next_cmd) | CMD(stop)) & 3)
 808                 break;
 809             if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 810                 break;
 811             if (CMD(max) > SVGA_FIFO_SIZE)
 812                 break;
 813             if (CMD(max) < CMD(min) + 10 * 1024)
 814                 break;
 815         }
 816         s->config = !!value;
 817         break;
 818
 819     case SVGA_REG_SYNC:
 820         s->syncing = 1;
 821         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 822         break;
 823
 824     case SVGA_REG_GUEST_ID:
 825         s->guest = value;
 826 #ifdef VERBOSE
 827         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 828                 ARRAY_SIZE(vmsvga_guest_id))
 829             printf("%s: guest runs %s.\n", __FUNCTION__,
 830                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 831 #endif
 832         break;
 833
 834     case SVGA_REG_CURSOR_ID:
 835         s->cursor.id = value;
 836         break;
 837
 838     case SVGA_REG_CURSOR_X:
 839         s->cursor.x = value;
 840         break;
 841
 842     case SVGA_REG_CURSOR_Y:
 843         s->cursor.y = value;
 844         break;
 845
 846     case SVGA_REG_CURSOR_ON:
 847         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 848         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 849 #ifdef HW_MOUSE_ACCEL
 850         if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 851             s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 852 #endif
 853         break;
 854
 855     case SVGA_REG_MEM_REGS:
 856     case SVGA_REG_NUM_DISPLAYS:
 857     case SVGA_REG_PITCHLOCK:
 858     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 859         break;
 860
 861     default:
 862         if (s->index >= SVGA_SCRATCH_BASE &&
 863                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 864             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 865             break;
 866         }
 867         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 868     }
 869 }
 870
 871 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 872 {
 873     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 874     return 0xcafe;
 875 }
 876
 877 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 878 {
 879     printf("%s: what are we supposed to do with (%08x)?\n",
 880                     __FUNCTION__, data);
 881 }
 882
 883 static inline void vmsvga_size(struct vmsvga_state_s *s)
 884 {
 885     if (s->new_width != s->width || s->new_height != s->height) {
 886         s->width = s->new_width;
 887         s->height = s->new_height;
 888         qemu_console_resize(s->ds, s->width, s->height);
 889         s->invalidated = 1;
 890     }
 891 }
 892
 893 static void vmsvga_update_display(void *opaque)
 894 {
 895     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 896     if (!s->enable) {
 897 #ifdef EMBED_STDVGA
 898         s->update(opaque);
 899 #endif
 900         return;
 901     }
 902
 903     vmsvga_size(s);
 904
 905     vmsvga_fifo_run(s);
 906     vmsvga_update_rect_flush(s);
 907
 908     /*
 909      * Is it more efficient to look at vram VGA-dirty bits or wait
 910      * for the driver to issue SVGA_CMD_UPDATE?
 911      */
 912     if (s->invalidated) {
 913         s->invalidated = 0;
 914         vmsvga_update_screen(s);
 915     }
 916 }
 917
 918 static void vmsvga_reset(struct vmsvga_state_s *s)
 919 {
 920     s->index = 0;
 921     s->enable = 0;
 922     s->config = 0;
 923     s->width = -1;
 924     s->height = -1;
 925     s->svgaid = SVGA_ID;
 926     s->depth = 24;
 927     s->bypp = (s->depth + 7) >> 3;
 928     s->cursor.on = 0;
 929     s->redraw_fifo_first = 0;
 930     s->redraw_fifo_last = 0;
 931     switch (s->depth) {
 932     case 8:
 933         s->wred   = 0x00000007;
 934         s->wgreen = 0x00000038;
 935         s->wblue  = 0x000000c0;
 936         break;
 937     case 15:
 938         s->wred   = 0x0000001f;
 939         s->wgreen = 0x000003e0;
 940         s->wblue  = 0x00007c00;
 941         break;
 942     case 16:
 943         s->wred   = 0x0000001f;
 944         s->wgreen = 0x000007e0;
 945         s->wblue  = 0x0000f800;
 946         break;
 947     case 24:
 948         s->wred   = 0x00ff0000;
 949         s->wgreen = 0x0000ff00;
 950         s->wblue  = 0x000000ff;
 951         break;
 952     case 32:
 953         s->wred   = 0x00ff0000;
 954         s->wgreen = 0x0000ff00;
 955         s->wblue  = 0x000000ff;
 956         break;
 957     }
 958     s->syncing = 0;
 959 }
 960
 961 static void vmsvga_invalidate_display(void *opaque)
 962 {
 963     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 964     if (!s->enable) {
 965 #ifdef EMBED_STDVGA
 966         s->invalidate(opaque);
 967 #endif
 968         return;
 969     }
 970
 971     s->invalidated = 1;
 972 }
 973
 974 /* save the vga display in a PPM image even if no display is
 975    available */
 976 static void vmsvga_screen_dump(void *opaque, const char *filename)
 977 {
 978     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 979     if (!s->enable) {
 980 #ifdef EMBED_STDVGA
 981         s->screen_dump(opaque, filename);
 982 #endif
 983         return;
 984     }
 985
 986     if (s->depth == 32) {
 987         DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
 988                 s->height, 32, ds_get_linesize(s->ds), s->vram);
 989         ppm_save(filename, ds);
 990         qemu_free(ds);
 991     }
 992 }
 993
 994 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
 995 {
 996     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 997
 998     if (s->text_update)
 999         s->text_update(opaque, chardata);
1000 }
1001
1002 #ifdef DIRECT_VRAM
1003 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
1004 {
1005     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1006     if (addr < s->fb_size)
1007         return *(uint8_t *) (ds_get_data(s->ds) + addr);
1008     else
1009         return *(uint8_t *) (s->vram + addr);
1010 }
1011
1012 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
1013 {
1014     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1015     if (addr < s->fb_size)
1016         return *(uint16_t *) (ds_get_data(s->ds) + addr);
1017     else
1018         return *(uint16_t *) (s->vram + addr);
1019 }
1020
1021 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1022 {
1023     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1024     if (addr < s->fb_size)
1025         return *(uint32_t *) (ds_get_data(s->ds) + addr);
1026     else
1027         return *(uint32_t *) (s->vram + addr);
1028 }
1029
1030 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1031                 uint32_t value)
1032 {
1033     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1034     if (addr < s->fb_size)
1035         *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
1036     else
1037         *(uint8_t *) (s->vram + addr) = value;
1038 }
1039
1040 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1041                 uint32_t value)
1042 {
1043     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1044     if (addr < s->fb_size)
1045         *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
1046     else
1047         *(uint16_t *) (s->vram + addr) = value;
1048 }
1049
1050 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1051                 uint32_t value)
1052 {
1053     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1054     if (addr < s->fb_size)
1055         *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
1056     else
1057         *(uint32_t *) (s->vram + addr) = value;
1058 }
1059
1060 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1061     vmsvga_vram_readb,
1062     vmsvga_vram_readw,
1063     vmsvga_vram_readl,
1064 };
1065
1066 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1067     vmsvga_vram_writeb,
1068     vmsvga_vram_writew,
1069     vmsvga_vram_writel,
1070 };
1071 #endif
1072
1073 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1074 {
1075     qemu_put_be32(f, s->depth);
1076     qemu_put_be32(f, s->enable);
1077     qemu_put_be32(f, s->config);
1078     qemu_put_be32(f, s->cursor.id);
1079     qemu_put_be32(f, s->cursor.x);
1080     qemu_put_be32(f, s->cursor.y);
1081     qemu_put_be32(f, s->cursor.on);
1082     qemu_put_be32(f, s->index);
1083     qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1084     qemu_put_be32(f, s->new_width);
1085     qemu_put_be32(f, s->new_height);
1086     qemu_put_be32s(f, &s->guest);
1087     qemu_put_be32s(f, &s->svgaid);
1088     qemu_put_be32(f, s->syncing);
1089     qemu_put_be32(f, s->fb_size);
1090 }
1091
1092 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1093 {
1094     int depth;
1095     depth=qemu_get_be32(f);
1096     s->enable=qemu_get_be32(f);
1097     s->config=qemu_get_be32(f);
1098     s->cursor.id=qemu_get_be32(f);
1099     s->cursor.x=qemu_get_be32(f);
1100     s->cursor.y=qemu_get_be32(f);
1101     s->cursor.on=qemu_get_be32(f);
1102     s->index=qemu_get_be32(f);
1103     qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1104     s->new_width=qemu_get_be32(f);
1105     s->new_height=qemu_get_be32(f);
1106     qemu_get_be32s(f, &s->guest);
1107     qemu_get_be32s(f, &s->svgaid);
1108     s->syncing=qemu_get_be32(f);
1109     s->fb_size=qemu_get_be32(f);
1110
1111     if (s->enable && depth != s->depth) {
1112         printf("%s: need colour depth of %i bits to resume operation.\n",
1113                         __FUNCTION__, depth);
1114         return -EINVAL;
1115     }
1116
1117     s->invalidated = 1;
1118     if (s->config)
1119         s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1120
1121     return 0;
1122 }
1123
1124 static void vmsvga_init(struct vmsvga_state_s *s,
1125                 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1126                 int vga_ram_size)
1127 {
1128     s->vram = vga_ram_base;
1129     s->vram_size = vga_ram_size;
1130     s->vram_offset = vga_ram_offset;
1131
1132     s->scratch_size = SVGA_SCRATCH_SIZE;
1133     s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1134
1135     vmsvga_reset(s);
1136
1137 #ifdef EMBED_STDVGA
1138     vga_common_init((VGAState *) s,
1139                     vga_ram_base, vga_ram_offset, vga_ram_size);
1140     vga_init((VGAState *) s);
1141 #endif
1142
1143     s->ds = graphic_console_init(vmsvga_update_display,
1144                                  vmsvga_invalidate_display,
1145                                  vmsvga_screen_dump,
1146                                  vmsvga_text_update, s);
1147
1148 #ifdef CONFIG_BOCHS_VBE
1149     /* XXX: use optimized standard vga accesses */
1150     cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1151                                  vga_ram_size, vga_ram_offset);
1152 #endif
1153 }
1154
1155 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1156 {
1157     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1158     pci_device_save(&s->card, f);
1159     vmsvga_save(&s->chip, f);
1160 }
1161
1162 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1163 {
1164     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1165     int ret;
1166
1167     ret = pci_device_load(&s->card, f);
1168     if (ret < 0)
1169         return ret;
1170
1171     ret = vmsvga_load(&s->chip, f);
1172     if (ret < 0)
1173         return ret;
1174
1175     return 0;
1176 }
1177
1178 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1179                 uint32_t addr, uint32_t size, int type)
1180 {
1181     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1182     struct vmsvga_state_s *s = &d->chip;
1183
1184     register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1185                     1, 4, vmsvga_index_read, s);
1186     register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1187                     1, 4, vmsvga_index_write, s);
1188     register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1189                     1, 4, vmsvga_value_read, s);
1190     register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1191                     1, 4, vmsvga_value_write, s);
1192     register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1193                     1, 4, vmsvga_bios_read, s);
1194     register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1195                     1, 4, vmsvga_bios_write, s);
1196 }
1197
1198 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1199                 uint32_t addr, uint32_t size, int type)
1200 {
1201     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1202     struct vmsvga_state_s *s = &d->chip;
1203     ram_addr_t iomemtype;
1204
1205     s->vram_base = addr;
1206 #ifdef DIRECT_VRAM
1207     iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1208                     vmsvga_vram_write, s);
1209 #else
1210     iomemtype = s->vram_offset | IO_MEM_RAM;
1211 #endif
1212     cpu_register_physical_memory(s->vram_base, s->vram_size,
1213                     iomemtype);
1214 }
1215
1216 #define PCI_CLASS_HEADERTYPE_00h        0x00
1217
1218 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
1219                      unsigned long vga_ram_offset, int vga_ram_size)
1220 {
1221     struct pci_vmsvga_state_s *s;
1222
1223     /* Setup PCI configuration */
1224     s = (struct pci_vmsvga_state_s *)
1225         pci_register_device(bus, "QEMUware SVGA",
1226                 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1227     pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1228     pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
1229     s->card.config[PCI_COMMAND]         = 0x07;         /* I/O + Memory */
1230     pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
1231     s->card.config[0x0c]                = 0x08;         /* Cache line size */
1232     s->card.config[0x0d]                = 0x40;         /* Latency timer */
1233     s->card.config[0x0e]                = PCI_CLASS_HEADERTYPE_00h;
1234     s->card.config[0x2c]                = PCI_VENDOR_ID_VMWARE & 0xff;
1235     s->card.config[0x2d]                = PCI_VENDOR_ID_VMWARE >> 8;
1236     s->card.config[0x2e]                = SVGA_PCI_DEVICE_ID & 0xff;
1237     s->card.config[0x2f]                = SVGA_PCI_DEVICE_ID >> 8;
1238     s->card.config[0x3c]                = 0xff;         /* End */
1239
1240     pci_register_io_region(&s->card, 0, 0x10,
1241                     PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1242     pci_register_io_region(&s->card, 1, vga_ram_size,
1243                     PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1244
1245     vmsvga_init(&s->chip, vga_ram_base, vga_ram_offset, vga_ram_size);
1246
1247     register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1248 }