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Support -singlestep option in HPPA target
[qemu/hppa.git] / linux-user / main.c
blobcd03acd16468bf7592547950533829c9f86f2685
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <stdarg.h>
24 #include <string.h>
25 #include <errno.h>
26 #include <unistd.h>
27 #include <sys/mman.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "cache-utils.h"
32 /* For tb_lock */
33 #include "exec-all.h"
34
35
36 #include "envlist.h"
37
38 #define DEBUG_LOGFILE "/tmp/qemu.log"
39
40 char *exec_path;
41
42 int singlestep;
43
44 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
45 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
46
47 #if defined(__i386__) && !defined(CONFIG_STATIC)
48 /* Force usage of an ELF interpreter even if it is an ELF shared
49 object ! */
50 const char interp[] __attribute__((section(".interp"))) = "/lib/ld-linux.so.2";
51 #endif
52
53 /* for recent libc, we add these dummy symbols which are not declared
54 when generating a linked object (bug in ld ?) */
55 #if (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && !defined(CONFIG_STATIC)
56 asm(".globl __preinit_array_start\n"
57 ".globl __preinit_array_end\n"
58 ".globl __init_array_start\n"
59 ".globl __init_array_end\n"
60 ".globl __fini_array_start\n"
61 ".globl __fini_array_end\n"
62 ".section \".rodata\"\n"
63 "__preinit_array_start:\n"
64 "__preinit_array_end:\n"
65 "__init_array_start:\n"
66 "__init_array_end:\n"
67 "__fini_array_start:\n"
68 "__fini_array_end:\n"
69 ".long 0\n"
70 ".previous\n");
71 #endif
72
73 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
74 we allocate a bigger stack. Need a better solution, for example
75 by remapping the process stack directly at the right place */
76 unsigned long x86_stack_size = 512 * 1024;
77
78 void gemu_log(const char *fmt, ...)
79 {
80 va_list ap;
81
82 va_start(ap, fmt);
83 vfprintf(stderr, fmt, ap);
84 va_end(ap);
85 }
86
87 void cpu_outb(CPUState *env, int addr, int val)
88 {
89 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", addr, val);
90 }
91
92 void cpu_outw(CPUState *env, int addr, int val)
93 {
94 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", addr, val);
95 }
96
97 void cpu_outl(CPUState *env, int addr, int val)
98 {
99 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val);
100 }
101
102 int cpu_inb(CPUState *env, int addr)
103 {
104 fprintf(stderr, "inb: port=0x%04x\n", addr);
105 return 0;
106 }
107
108 int cpu_inw(CPUState *env, int addr)
109 {
110 fprintf(stderr, "inw: port=0x%04x\n", addr);
111 return 0;
112 }
113
114 int cpu_inl(CPUState *env, int addr)
115 {
116 fprintf(stderr, "inl: port=0x%04x\n", addr);
117 return 0;
118 }
119
120 #if defined(TARGET_I386)
121 int cpu_get_pic_interrupt(CPUState *env)
122 {
123 return -1;
124 }
125 #endif
126
127 /* timers for rdtsc */
128
129 #if 0
130
131 static uint64_t emu_time;
132
133 int64_t cpu_get_real_ticks(void)
134 {
135 return emu_time++;
136 }
137
138 #endif
139
140 #if defined(USE_NPTL)
141 /***********************************************************/
142 /* Helper routines for implementing atomic operations. */
143
144 /* To implement exclusive operations we force all cpus to syncronise.
145 We don't require a full sync, only that no cpus are executing guest code.
146 The alternative is to map target atomic ops onto host equivalents,
147 which requires quite a lot of per host/target work. */
148 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
149 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
150 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
151 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
152 static int pending_cpus;
153
154 /* Make sure everything is in a consistent state for calling fork(). */
155 void fork_start(void)
156 {
157 mmap_fork_start();
158 pthread_mutex_lock(&tb_lock);
159 pthread_mutex_lock(&exclusive_lock);
160 }
161
162 void fork_end(int child)
163 {
164 if (child) {
165 /* Child processes created by fork() only have a single thread.
166 Discard information about the parent threads. */
167 first_cpu = thread_env;
168 thread_env->next_cpu = NULL;
169 pending_cpus = 0;
170 pthread_mutex_init(&exclusive_lock, NULL);
171 pthread_mutex_init(&cpu_list_mutex, NULL);
172 pthread_cond_init(&exclusive_cond, NULL);
173 pthread_cond_init(&exclusive_resume, NULL);
174 pthread_mutex_init(&tb_lock, NULL);
175 gdbserver_fork(thread_env);
176 } else {
177 pthread_mutex_unlock(&exclusive_lock);
178 pthread_mutex_unlock(&tb_lock);
179 }
180 mmap_fork_end(child);
181 }
182
183 /* Wait for pending exclusive operations to complete. The exclusive lock
184 must be held. */
185 static inline void exclusive_idle(void)
186 {
187 while (pending_cpus) {
188 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
189 }
190 }
191
192 /* Start an exclusive operation.
193 Must only be called from outside cpu_arm_exec. */
194 static inline void start_exclusive(void)
195 {
196 CPUState *other;
197 pthread_mutex_lock(&exclusive_lock);
198 exclusive_idle();
199
200 pending_cpus = 1;
201 /* Make all other cpus stop executing. */
202 for (other = first_cpu; other; other = other->next_cpu) {
203 if (other->running) {
204 pending_cpus++;
205 cpu_exit(other);
206 }
207 }
208 if (pending_cpus > 1) {
209 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
210 }
211 }
212
213 /* Finish an exclusive operation. */
214 static inline void end_exclusive(void)
215 {
216 pending_cpus = 0;
217 pthread_cond_broadcast(&exclusive_resume);
218 pthread_mutex_unlock(&exclusive_lock);
219 }
220
221 /* Wait for exclusive ops to finish, and begin cpu execution. */
222 static inline void cpu_exec_start(CPUState *env)
223 {
224 pthread_mutex_lock(&exclusive_lock);
225 exclusive_idle();
226 env->running = 1;
227 pthread_mutex_unlock(&exclusive_lock);
228 }
229
230 /* Mark cpu as not executing, and release pending exclusive ops. */
231 static inline void cpu_exec_end(CPUState *env)
232 {
233 pthread_mutex_lock(&exclusive_lock);
234 env->running = 0;
235 if (pending_cpus > 1) {
236 pending_cpus--;
237 if (pending_cpus == 1) {
238 pthread_cond_signal(&exclusive_cond);
239 }
240 }
241 exclusive_idle();
242 pthread_mutex_unlock(&exclusive_lock);
243 }
244
245 void cpu_list_lock(void)
246 {
247 pthread_mutex_lock(&cpu_list_mutex);
248 }
249
250 void cpu_list_unlock(void)
251 {
252 pthread_mutex_unlock(&cpu_list_mutex);
253 }
254 #else /* if !USE_NPTL */
255 /* These are no-ops because we are not threadsafe. */
256 static inline void cpu_exec_start(CPUState *env)
257 {
258 }
259
260 static inline void cpu_exec_end(CPUState *env)
261 {
262 }
263
264 static inline void start_exclusive(void)
265 {
266 }
267
268 static inline void end_exclusive(void)
269 {
270 }
271
272 void fork_start(void)
273 {
274 }
275
276 void fork_end(int child)
277 {
278 if (child) {
279 gdbserver_fork(thread_env);
280 }
281 }
282
283 void cpu_list_lock(void)
284 {
285 }
286
287 void cpu_list_unlock(void)
288 {
289 }
290 #endif
291
292
293 #ifdef TARGET_I386
294 /***********************************************************/
295 /* CPUX86 core interface */
296
297 void cpu_smm_update(CPUState *env)
298 {
299 }
300
301 uint64_t cpu_get_tsc(CPUX86State *env)
302 {
303 return cpu_get_real_ticks();
304 }
305
306 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
307 int flags)
308 {
309 unsigned int e1, e2;
310 uint32_t *p;
311 e1 = (addr << 16) | (limit & 0xffff);
312 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
313 e2 |= flags;
314 p = ptr;
315 p[0] = tswap32(e1);
316 p[1] = tswap32(e2);
317 }
318
319 static uint64_t *idt_table;
320 #ifdef TARGET_X86_64
321 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
322 uint64_t addr, unsigned int sel)
323 {
324 uint32_t *p, e1, e2;
325 e1 = (addr & 0xffff) | (sel << 16);
326 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
327 p = ptr;
328 p[0] = tswap32(e1);
329 p[1] = tswap32(e2);
330 p[2] = tswap32(addr >> 32);
331 p[3] = 0;
332 }
333 /* only dpl matters as we do only user space emulation */
334 static void set_idt(int n, unsigned int dpl)
335 {
336 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
337 }
338 #else
339 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
340 uint32_t addr, unsigned int sel)
341 {
342 uint32_t *p, e1, e2;
343 e1 = (addr & 0xffff) | (sel << 16);
344 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
345 p = ptr;
346 p[0] = tswap32(e1);
347 p[1] = tswap32(e2);
348 }
349
350 /* only dpl matters as we do only user space emulation */
351 static void set_idt(int n, unsigned int dpl)
352 {
353 set_gate(idt_table + n, 0, dpl, 0, 0);
354 }
355 #endif
356
357 void cpu_loop(CPUX86State *env)
358 {
359 int trapnr;
360 abi_ulong pc;
361 target_siginfo_t info;
362
363 for(;;) {
364 trapnr = cpu_x86_exec(env);
365 switch(trapnr) {
366 case 0x80:
367 /* linux syscall from int $0x80 */
368 env->regs[R_EAX] = do_syscall(env,
369 env->regs[R_EAX],
370 env->regs[R_EBX],
371 env->regs[R_ECX],
372 env->regs[R_EDX],
373 env->regs[R_ESI],
374 env->regs[R_EDI],
375 env->regs[R_EBP]);
376 break;
377 #ifndef TARGET_ABI32
378 case EXCP_SYSCALL:
379 /* linux syscall from syscall intruction */
380 env->regs[R_EAX] = do_syscall(env,
381 env->regs[R_EAX],
382 env->regs[R_EDI],
383 env->regs[R_ESI],
384 env->regs[R_EDX],
385 env->regs[10],
386 env->regs[8],
387 env->regs[9]);
388 env->eip = env->exception_next_eip;
389 break;
390 #endif
391 case EXCP0B_NOSEG:
392 case EXCP0C_STACK:
393 info.si_signo = SIGBUS;
394 info.si_errno = 0;
395 info.si_code = TARGET_SI_KERNEL;
396 info._sifields._sigfault._addr = 0;
397 queue_signal(env, info.si_signo, &info);
398 break;
399 case EXCP0D_GPF:
400 /* XXX: potential problem if ABI32 */
401 #ifndef TARGET_X86_64
402 if (env->eflags & VM_MASK) {
403 handle_vm86_fault(env);
404 } else
405 #endif
406 {
407 info.si_signo = SIGSEGV;
408 info.si_errno = 0;
409 info.si_code = TARGET_SI_KERNEL;
410 info._sifields._sigfault._addr = 0;
411 queue_signal(env, info.si_signo, &info);
412 }
413 break;
414 case EXCP0E_PAGE:
415 info.si_signo = SIGSEGV;
416 info.si_errno = 0;
417 if (!(env->error_code & 1))
418 info.si_code = TARGET_SEGV_MAPERR;
419 else
420 info.si_code = TARGET_SEGV_ACCERR;
421 info._sifields._sigfault._addr = env->cr[2];
422 queue_signal(env, info.si_signo, &info);
423 break;
424 case EXCP00_DIVZ:
425 #ifndef TARGET_X86_64
426 if (env->eflags & VM_MASK) {
427 handle_vm86_trap(env, trapnr);
428 } else
429 #endif
430 {
431 /* division by zero */
432 info.si_signo = SIGFPE;
433 info.si_errno = 0;
434 info.si_code = TARGET_FPE_INTDIV;
435 info._sifields._sigfault._addr = env->eip;
436 queue_signal(env, info.si_signo, &info);
437 }
438 break;
439 case EXCP01_DB:
440 case EXCP03_INT3:
441 #ifndef TARGET_X86_64
442 if (env->eflags & VM_MASK) {
443 handle_vm86_trap(env, trapnr);
444 } else
445 #endif
446 {
447 info.si_signo = SIGTRAP;
448 info.si_errno = 0;
449 if (trapnr == EXCP01_DB) {
450 info.si_code = TARGET_TRAP_BRKPT;
451 info._sifields._sigfault._addr = env->eip;
452 } else {
453 info.si_code = TARGET_SI_KERNEL;
454 info._sifields._sigfault._addr = 0;
455 }
456 queue_signal(env, info.si_signo, &info);
457 }
458 break;
459 case EXCP04_INTO:
460 case EXCP05_BOUND:
461 #ifndef TARGET_X86_64
462 if (env->eflags & VM_MASK) {
463 handle_vm86_trap(env, trapnr);
464 } else
465 #endif
466 {
467 info.si_signo = SIGSEGV;
468 info.si_errno = 0;
469 info.si_code = TARGET_SI_KERNEL;
470 info._sifields._sigfault._addr = 0;
471 queue_signal(env, info.si_signo, &info);
472 }
473 break;
474 case EXCP06_ILLOP:
475 info.si_signo = SIGILL;
476 info.si_errno = 0;
477 info.si_code = TARGET_ILL_ILLOPN;
478 info._sifields._sigfault._addr = env->eip;
479 queue_signal(env, info.si_signo, &info);
480 break;
481 case EXCP_INTERRUPT:
482 /* just indicate that signals should be handled asap */
483 break;
484 case EXCP_DEBUG:
485 {
486 int sig;
487
488 sig = gdb_handlesig (env, TARGET_SIGTRAP);
489 if (sig)
490 {
491 info.si_signo = sig;
492 info.si_errno = 0;
493 info.si_code = TARGET_TRAP_BRKPT;
494 queue_signal(env, info.si_signo, &info);
495 }
496 }
497 break;
498 default:
499 pc = env->segs[R_CS].base + env->eip;
500 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
501 (long)pc, trapnr);
502 abort();
503 }
504 process_pending_signals(env);
505 }
506 }
507 #endif
508
509 #ifdef TARGET_ARM
510
511 static void arm_cache_flush(abi_ulong start, abi_ulong last)
512 {
513 abi_ulong addr, last1;
514
515 if (last < start)
516 return;
517 addr = start;
518 for(;;) {
519 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
520 if (last1 > last)
521 last1 = last;
522 tb_invalidate_page_range(addr, last1 + 1);
523 if (last1 == last)
524 break;
525 addr = last1 + 1;
526 }
527 }
528
529 /* Handle a jump to the kernel code page. */
530 static int
531 do_kernel_trap(CPUARMState *env)
532 {
533 uint32_t addr;
534 uint32_t cpsr;
535 uint32_t val;
536
537 switch (env->regs[15]) {
538 case 0xffff0fa0: /* __kernel_memory_barrier */
539 /* ??? No-op. Will need to do better for SMP. */
540 break;
541 case 0xffff0fc0: /* __kernel_cmpxchg */
542 /* XXX: This only works between threads, not between processes.
543 It's probably possible to implement this with native host
544 operations. However things like ldrex/strex are much harder so
545 there's not much point trying. */
546 start_exclusive();
547 cpsr = cpsr_read(env);
548 addr = env->regs[2];
549 /* FIXME: This should SEGV if the access fails. */
550 if (get_user_u32(val, addr))
551 val = ~env->regs[0];
552 if (val == env->regs[0]) {
553 val = env->regs[1];
554 /* FIXME: Check for segfaults. */
555 put_user_u32(val, addr);
556 env->regs[0] = 0;
557 cpsr |= CPSR_C;
558 } else {
559 env->regs[0] = -1;
560 cpsr &= ~CPSR_C;
561 }
562 cpsr_write(env, cpsr, CPSR_C);
563 end_exclusive();
564 break;
565 case 0xffff0fe0: /* __kernel_get_tls */
566 env->regs[0] = env->cp15.c13_tls2;
567 break;
568 default:
569 return 1;
570 }
571 /* Jump back to the caller. */
572 addr = env->regs[14];
573 if (addr & 1) {
574 env->thumb = 1;
575 addr &= ~1;
576 }
577 env->regs[15] = addr;
578
579 return 0;
580 }
581
582 void cpu_loop(CPUARMState *env)
583 {
584 int trapnr;
585 unsigned int n, insn;
586 target_siginfo_t info;
587 uint32_t addr;
588
589 for(;;) {
590 cpu_exec_start(env);
591 trapnr = cpu_arm_exec(env);
592 cpu_exec_end(env);
593 switch(trapnr) {
594 case EXCP_UDEF:
595 {
596 TaskState *ts = env->opaque;
597 uint32_t opcode;
598 int rc;
599
600 /* we handle the FPU emulation here, as Linux */
601 /* we get the opcode */
602 /* FIXME - what to do if get_user() fails? */
603 get_user_u32(opcode, env->regs[15]);
604
605 rc = EmulateAll(opcode, &ts->fpa, env);
606 if (rc == 0) { /* illegal instruction */
607 info.si_signo = SIGILL;
608 info.si_errno = 0;
609 info.si_code = TARGET_ILL_ILLOPN;
610 info._sifields._sigfault._addr = env->regs[15];
611 queue_signal(env, info.si_signo, &info);
612 } else if (rc < 0) { /* FP exception */
613 int arm_fpe=0;
614
615 /* translate softfloat flags to FPSR flags */
616 if (-rc & float_flag_invalid)
617 arm_fpe |= BIT_IOC;
618 if (-rc & float_flag_divbyzero)
619 arm_fpe |= BIT_DZC;
620 if (-rc & float_flag_overflow)
621 arm_fpe |= BIT_OFC;
622 if (-rc & float_flag_underflow)
623 arm_fpe |= BIT_UFC;
624 if (-rc & float_flag_inexact)
625 arm_fpe |= BIT_IXC;
626
627 FPSR fpsr = ts->fpa.fpsr;
628 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
629
630 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
631 info.si_signo = SIGFPE;
632 info.si_errno = 0;
633
634 /* ordered by priority, least first */
635 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
636 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
637 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
638 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
639 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
640
641 info._sifields._sigfault._addr = env->regs[15];
642 queue_signal(env, info.si_signo, &info);
643 } else {
644 env->regs[15] += 4;
645 }
646
647 /* accumulate unenabled exceptions */
648 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
649 fpsr |= BIT_IXC;
650 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
651 fpsr |= BIT_UFC;
652 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
653 fpsr |= BIT_OFC;
654 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
655 fpsr |= BIT_DZC;
656 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
657 fpsr |= BIT_IOC;
658 ts->fpa.fpsr=fpsr;
659 } else { /* everything OK */
660 /* increment PC */
661 env->regs[15] += 4;
662 }
663 }
664 break;
665 case EXCP_SWI:
666 case EXCP_BKPT:
667 {
668 env->eabi = 1;
669 /* system call */
670 if (trapnr == EXCP_BKPT) {
671 if (env->thumb) {
672 /* FIXME - what to do if get_user() fails? */
673 get_user_u16(insn, env->regs[15]);
674 n = insn & 0xff;
675 env->regs[15] += 2;
676 } else {
677 /* FIXME - what to do if get_user() fails? */
678 get_user_u32(insn, env->regs[15]);
679 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
680 env->regs[15] += 4;
681 }
682 } else {
683 if (env->thumb) {
684 /* FIXME - what to do if get_user() fails? */
685 get_user_u16(insn, env->regs[15] - 2);
686 n = insn & 0xff;
687 } else {
688 /* FIXME - what to do if get_user() fails? */
689 get_user_u32(insn, env->regs[15] - 4);
690 n = insn & 0xffffff;
691 }
692 }
693
694 if (n == ARM_NR_cacheflush) {
695 arm_cache_flush(env->regs[0], env->regs[1]);
696 } else if (n == ARM_NR_semihosting
697 || n == ARM_NR_thumb_semihosting) {
698 env->regs[0] = do_arm_semihosting (env);
699 } else if (n == 0 || n >= ARM_SYSCALL_BASE
700 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
701 /* linux syscall */
702 if (env->thumb || n == 0) {
703 n = env->regs[7];
704 } else {
705 n -= ARM_SYSCALL_BASE;
706 env->eabi = 0;
707 }
708 if ( n > ARM_NR_BASE) {
709 switch (n) {
710 case ARM_NR_cacheflush:
711 arm_cache_flush(env->regs[0], env->regs[1]);
712 break;
713 case ARM_NR_set_tls:
714 cpu_set_tls(env, env->regs[0]);
715 env->regs[0] = 0;
716 break;
717 default:
718 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
719 n);
720 env->regs[0] = -TARGET_ENOSYS;
721 break;
722 }
723 } else {
724 env->regs[0] = do_syscall(env,
725 n,
726 env->regs[0],
727 env->regs[1],
728 env->regs[2],
729 env->regs[3],
730 env->regs[4],
731 env->regs[5]);
732 }
733 } else {
734 goto error;
735 }
736 }
737 break;
738 case EXCP_INTERRUPT:
739 /* just indicate that signals should be handled asap */
740 break;
741 case EXCP_PREFETCH_ABORT:
742 addr = env->cp15.c6_insn;
743 goto do_segv;
744 case EXCP_DATA_ABORT:
745 addr = env->cp15.c6_data;
746 goto do_segv;
747 do_segv:
748 {
749 info.si_signo = SIGSEGV;
750 info.si_errno = 0;
751 /* XXX: check env->error_code */
752 info.si_code = TARGET_SEGV_MAPERR;
753 info._sifields._sigfault._addr = addr;
754 queue_signal(env, info.si_signo, &info);
755 }
756 break;
757 case EXCP_DEBUG:
758 {
759 int sig;
760
761 sig = gdb_handlesig (env, TARGET_SIGTRAP);
762 if (sig)
763 {
764 info.si_signo = sig;
765 info.si_errno = 0;
766 info.si_code = TARGET_TRAP_BRKPT;
767 queue_signal(env, info.si_signo, &info);
768 }
769 }
770 break;
771 case EXCP_KERNEL_TRAP:
772 if (do_kernel_trap(env))
773 goto error;
774 break;
775 default:
776 error:
777 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
778 trapnr);
779 cpu_dump_state(env, stderr, fprintf, 0);
780 abort();
781 }
782 process_pending_signals(env);
783 }
784 }
785
786 #endif
787
788 #ifdef TARGET_SPARC
789 #define SPARC64_STACK_BIAS 2047
790
791 //#define DEBUG_WIN
792
793 /* WARNING: dealing with register windows _is_ complicated. More info
794 can be found at http://www.sics.se/~psm/sparcstack.html */
795 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
796 {
797 index = (index + cwp * 16) % (16 * env->nwindows);
798 /* wrap handling : if cwp is on the last window, then we use the
799 registers 'after' the end */
800 if (index < 8 && env->cwp == env->nwindows - 1)
801 index += 16 * env->nwindows;
802 return index;
803 }
804
805 /* save the register window 'cwp1' */
806 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
807 {
808 unsigned int i;
809 abi_ulong sp_ptr;
810
811 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
812 #ifdef TARGET_SPARC64
813 if (sp_ptr & 3)
814 sp_ptr += SPARC64_STACK_BIAS;
815 #endif
816 #if defined(DEBUG_WIN)
817 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
818 sp_ptr, cwp1);
819 #endif
820 for(i = 0; i < 16; i++) {
821 /* FIXME - what to do if put_user() fails? */
822 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
823 sp_ptr += sizeof(abi_ulong);
824 }
825 }
826
827 static void save_window(CPUSPARCState *env)
828 {
829 #ifndef TARGET_SPARC64
830 unsigned int new_wim;
831 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
832 ((1LL << env->nwindows) - 1);
833 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
834 env->wim = new_wim;
835 #else
836 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
837 env->cansave++;
838 env->canrestore--;
839 #endif
840 }
841
842 static void restore_window(CPUSPARCState *env)
843 {
844 #ifndef TARGET_SPARC64
845 unsigned int new_wim;
846 #endif
847 unsigned int i, cwp1;
848 abi_ulong sp_ptr;
849
850 #ifndef TARGET_SPARC64
851 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
852 ((1LL << env->nwindows) - 1);
853 #endif
854
855 /* restore the invalid window */
856 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
857 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
858 #ifdef TARGET_SPARC64
859 if (sp_ptr & 3)
860 sp_ptr += SPARC64_STACK_BIAS;
861 #endif
862 #if defined(DEBUG_WIN)
863 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
864 sp_ptr, cwp1);
865 #endif
866 for(i = 0; i < 16; i++) {
867 /* FIXME - what to do if get_user() fails? */
868 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
869 sp_ptr += sizeof(abi_ulong);
870 }
871 #ifdef TARGET_SPARC64
872 env->canrestore++;
873 if (env->cleanwin < env->nwindows - 1)
874 env->cleanwin++;
875 env->cansave--;
876 #else
877 env->wim = new_wim;
878 #endif
879 }
880
881 static void flush_windows(CPUSPARCState *env)
882 {
883 int offset, cwp1;
884
885 offset = 1;
886 for(;;) {
887 /* if restore would invoke restore_window(), then we can stop */
888 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
889 #ifndef TARGET_SPARC64
890 if (env->wim & (1 << cwp1))
891 break;
892 #else
893 if (env->canrestore == 0)
894 break;
895 env->cansave++;
896 env->canrestore--;
897 #endif
898 save_window_offset(env, cwp1);
899 offset++;
900 }
901 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
902 #ifndef TARGET_SPARC64
903 /* set wim so that restore will reload the registers */
904 env->wim = 1 << cwp1;
905 #endif
906 #if defined(DEBUG_WIN)
907 printf("flush_windows: nb=%d\n", offset - 1);
908 #endif
909 }
910
911 void cpu_loop (CPUSPARCState *env)
912 {
913 int trapnr, ret;
914 target_siginfo_t info;
915
916 while (1) {
917 trapnr = cpu_sparc_exec (env);
918
919 switch (trapnr) {
920 #ifndef TARGET_SPARC64
921 case 0x88:
922 case 0x90:
923 #else
924 case 0x110:
925 case 0x16d:
926 #endif
927 ret = do_syscall (env, env->gregs[1],
928 env->regwptr[0], env->regwptr[1],
929 env->regwptr[2], env->regwptr[3],
930 env->regwptr[4], env->regwptr[5]);
931 if ((unsigned int)ret >= (unsigned int)(-515)) {
932 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
933 env->xcc |= PSR_CARRY;
934 #else
935 env->psr |= PSR_CARRY;
936 #endif
937 ret = -ret;
938 } else {
939 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
940 env->xcc &= ~PSR_CARRY;
941 #else
942 env->psr &= ~PSR_CARRY;
943 #endif
944 }
945 env->regwptr[0] = ret;
946 /* next instruction */
947 env->pc = env->npc;
948 env->npc = env->npc + 4;
949 break;
950 case 0x83: /* flush windows */
951 #ifdef TARGET_ABI32
952 case 0x103:
953 #endif
954 flush_windows(env);
955 /* next instruction */
956 env->pc = env->npc;
957 env->npc = env->npc + 4;
958 break;
959 #ifndef TARGET_SPARC64
960 case TT_WIN_OVF: /* window overflow */
961 save_window(env);
962 break;
963 case TT_WIN_UNF: /* window underflow */
964 restore_window(env);
965 break;
966 case TT_TFAULT:
967 case TT_DFAULT:
968 {
969 info.si_signo = SIGSEGV;
970 info.si_errno = 0;
971 /* XXX: check env->error_code */
972 info.si_code = TARGET_SEGV_MAPERR;
973 info._sifields._sigfault._addr = env->mmuregs[4];
974 queue_signal(env, info.si_signo, &info);
975 }
976 break;
977 #else
978 case TT_SPILL: /* window overflow */
979 save_window(env);
980 break;
981 case TT_FILL: /* window underflow */
982 restore_window(env);
983 break;
984 case TT_TFAULT:
985 case TT_DFAULT:
986 {
987 info.si_signo = SIGSEGV;
988 info.si_errno = 0;
989 /* XXX: check env->error_code */
990 info.si_code = TARGET_SEGV_MAPERR;
991 if (trapnr == TT_DFAULT)
992 info._sifields._sigfault._addr = env->dmmuregs[4];
993 else
994 info._sifields._sigfault._addr = env->tsptr->tpc;
995 queue_signal(env, info.si_signo, &info);
996 }
997 break;
998 #ifndef TARGET_ABI32
999 case 0x16e:
1000 flush_windows(env);
1001 sparc64_get_context(env);
1002 break;
1003 case 0x16f:
1004 flush_windows(env);
1005 sparc64_set_context(env);
1006 break;
1007 #endif
1008 #endif
1009 case EXCP_INTERRUPT:
1010 /* just indicate that signals should be handled asap */
1011 break;
1012 case EXCP_DEBUG:
1013 {
1014 int sig;
1015
1016 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1017 if (sig)
1018 {
1019 info.si_signo = sig;
1020 info.si_errno = 0;
1021 info.si_code = TARGET_TRAP_BRKPT;
1022 queue_signal(env, info.si_signo, &info);
1023 }
1024 }
1025 break;
1026 default:
1027 printf ("Unhandled trap: 0x%x\n", trapnr);
1028 cpu_dump_state(env, stderr, fprintf, 0);
1029 exit (1);
1030 }
1031 process_pending_signals (env);
1032 }
1033 }
1034
1035 #endif
1036
1037 #ifdef TARGET_PPC
1038 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1039 {
1040 /* TO FIX */
1041 return 0;
1042 }
1043
1044 uint32_t cpu_ppc_load_tbl (CPUState *env)
1045 {
1046 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1047 }
1048
1049 uint32_t cpu_ppc_load_tbu (CPUState *env)
1050 {
1051 return cpu_ppc_get_tb(env) >> 32;
1052 }
1053
1054 uint32_t cpu_ppc_load_atbl (CPUState *env)
1055 {
1056 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1057 }
1058
1059 uint32_t cpu_ppc_load_atbu (CPUState *env)
1060 {
1061 return cpu_ppc_get_tb(env) >> 32;
1062 }
1063
1064 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1065 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1066
1067 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1068 {
1069 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1070 }
1071
1072 /* XXX: to be fixed */
1073 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1074 {
1075 return -1;
1076 }
1077
1078 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1079 {
1080 return -1;
1081 }
1082
1083 #define EXCP_DUMP(env, fmt, args...) \
1084 do { \
1085 fprintf(stderr, fmt , ##args); \
1086 cpu_dump_state(env, stderr, fprintf, 0); \
1087 qemu_log(fmt, ##args); \
1088 log_cpu_state(env, 0); \
1089 } while (0)
1090
1091 void cpu_loop(CPUPPCState *env)
1092 {
1093 target_siginfo_t info;
1094 int trapnr;
1095 uint32_t ret;
1096
1097 for(;;) {
1098 trapnr = cpu_ppc_exec(env);
1099 switch(trapnr) {
1100 case POWERPC_EXCP_NONE:
1101 /* Just go on */
1102 break;
1103 case POWERPC_EXCP_CRITICAL: /* Critical input */
1104 cpu_abort(env, "Critical interrupt while in user mode. "
1105 "Aborting\n");
1106 break;
1107 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1108 cpu_abort(env, "Machine check exception while in user mode. "
1109 "Aborting\n");
1110 break;
1111 case POWERPC_EXCP_DSI: /* Data storage exception */
1112 EXCP_DUMP(env, "Invalid data memory access: 0x" ADDRX "\n",
1113 env->spr[SPR_DAR]);
1114 /* XXX: check this. Seems bugged */
1115 switch (env->error_code & 0xFF000000) {
1116 case 0x40000000:
1117 info.si_signo = TARGET_SIGSEGV;
1118 info.si_errno = 0;
1119 info.si_code = TARGET_SEGV_MAPERR;
1120 break;
1121 case 0x04000000:
1122 info.si_signo = TARGET_SIGILL;
1123 info.si_errno = 0;
1124 info.si_code = TARGET_ILL_ILLADR;
1125 break;
1126 case 0x08000000:
1127 info.si_signo = TARGET_SIGSEGV;
1128 info.si_errno = 0;
1129 info.si_code = TARGET_SEGV_ACCERR;
1130 break;
1131 default:
1132 /* Let's send a regular segfault... */
1133 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1134 env->error_code);
1135 info.si_signo = TARGET_SIGSEGV;
1136 info.si_errno = 0;
1137 info.si_code = TARGET_SEGV_MAPERR;
1138 break;
1139 }
1140 info._sifields._sigfault._addr = env->nip;
1141 queue_signal(env, info.si_signo, &info);
1142 break;
1143 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1144 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" ADDRX "\n",
1145 env->spr[SPR_SRR0]);
1146 /* XXX: check this */
1147 switch (env->error_code & 0xFF000000) {
1148 case 0x40000000:
1149 info.si_signo = TARGET_SIGSEGV;
1150 info.si_errno = 0;
1151 info.si_code = TARGET_SEGV_MAPERR;
1152 break;
1153 case 0x10000000:
1154 case 0x08000000:
1155 info.si_signo = TARGET_SIGSEGV;
1156 info.si_errno = 0;
1157 info.si_code = TARGET_SEGV_ACCERR;
1158 break;
1159 default:
1160 /* Let's send a regular segfault... */
1161 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1162 env->error_code);
1163 info.si_signo = TARGET_SIGSEGV;
1164 info.si_errno = 0;
1165 info.si_code = TARGET_SEGV_MAPERR;
1166 break;
1167 }
1168 info._sifields._sigfault._addr = env->nip - 4;
1169 queue_signal(env, info.si_signo, &info);
1170 break;
1171 case POWERPC_EXCP_EXTERNAL: /* External input */
1172 cpu_abort(env, "External interrupt while in user mode. "
1173 "Aborting\n");
1174 break;
1175 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1176 EXCP_DUMP(env, "Unaligned memory access\n");
1177 /* XXX: check this */
1178 info.si_signo = TARGET_SIGBUS;
1179 info.si_errno = 0;
1180 info.si_code = TARGET_BUS_ADRALN;
1181 info._sifields._sigfault._addr = env->nip - 4;
1182 queue_signal(env, info.si_signo, &info);
1183 break;
1184 case POWERPC_EXCP_PROGRAM: /* Program exception */
1185 /* XXX: check this */
1186 switch (env->error_code & ~0xF) {
1187 case POWERPC_EXCP_FP:
1188 EXCP_DUMP(env, "Floating point program exception\n");
1189 info.si_signo = TARGET_SIGFPE;
1190 info.si_errno = 0;
1191 switch (env->error_code & 0xF) {
1192 case POWERPC_EXCP_FP_OX:
1193 info.si_code = TARGET_FPE_FLTOVF;
1194 break;
1195 case POWERPC_EXCP_FP_UX:
1196 info.si_code = TARGET_FPE_FLTUND;
1197 break;
1198 case POWERPC_EXCP_FP_ZX:
1199 case POWERPC_EXCP_FP_VXZDZ:
1200 info.si_code = TARGET_FPE_FLTDIV;
1201 break;
1202 case POWERPC_EXCP_FP_XX:
1203 info.si_code = TARGET_FPE_FLTRES;
1204 break;
1205 case POWERPC_EXCP_FP_VXSOFT:
1206 info.si_code = TARGET_FPE_FLTINV;
1207 break;
1208 case POWERPC_EXCP_FP_VXSNAN:
1209 case POWERPC_EXCP_FP_VXISI:
1210 case POWERPC_EXCP_FP_VXIDI:
1211 case POWERPC_EXCP_FP_VXIMZ:
1212 case POWERPC_EXCP_FP_VXVC:
1213 case POWERPC_EXCP_FP_VXSQRT:
1214 case POWERPC_EXCP_FP_VXCVI:
1215 info.si_code = TARGET_FPE_FLTSUB;
1216 break;
1217 default:
1218 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1219 env->error_code);
1220 break;
1221 }
1222 break;
1223 case POWERPC_EXCP_INVAL:
1224 EXCP_DUMP(env, "Invalid instruction\n");
1225 info.si_signo = TARGET_SIGILL;
1226 info.si_errno = 0;
1227 switch (env->error_code & 0xF) {
1228 case POWERPC_EXCP_INVAL_INVAL:
1229 info.si_code = TARGET_ILL_ILLOPC;
1230 break;
1231 case POWERPC_EXCP_INVAL_LSWX:
1232 info.si_code = TARGET_ILL_ILLOPN;
1233 break;
1234 case POWERPC_EXCP_INVAL_SPR:
1235 info.si_code = TARGET_ILL_PRVREG;
1236 break;
1237 case POWERPC_EXCP_INVAL_FP:
1238 info.si_code = TARGET_ILL_COPROC;
1239 break;
1240 default:
1241 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1242 env->error_code & 0xF);
1243 info.si_code = TARGET_ILL_ILLADR;
1244 break;
1245 }
1246 break;
1247 case POWERPC_EXCP_PRIV:
1248 EXCP_DUMP(env, "Privilege violation\n");
1249 info.si_signo = TARGET_SIGILL;
1250 info.si_errno = 0;
1251 switch (env->error_code & 0xF) {
1252 case POWERPC_EXCP_PRIV_OPC:
1253 info.si_code = TARGET_ILL_PRVOPC;
1254 break;
1255 case POWERPC_EXCP_PRIV_REG:
1256 info.si_code = TARGET_ILL_PRVREG;
1257 break;
1258 default:
1259 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1260 env->error_code & 0xF);
1261 info.si_code = TARGET_ILL_PRVOPC;
1262 break;
1263 }
1264 break;
1265 case POWERPC_EXCP_TRAP:
1266 cpu_abort(env, "Tried to call a TRAP\n");
1267 break;
1268 default:
1269 /* Should not happen ! */
1270 cpu_abort(env, "Unknown program exception (%02x)\n",
1271 env->error_code);
1272 break;
1273 }
1274 info._sifields._sigfault._addr = env->nip - 4;
1275 queue_signal(env, info.si_signo, &info);
1276 break;
1277 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1278 EXCP_DUMP(env, "No floating point allowed\n");
1279 info.si_signo = TARGET_SIGILL;
1280 info.si_errno = 0;
1281 info.si_code = TARGET_ILL_COPROC;
1282 info._sifields._sigfault._addr = env->nip - 4;
1283 queue_signal(env, info.si_signo, &info);
1284 break;
1285 case POWERPC_EXCP_SYSCALL: /* System call exception */
1286 cpu_abort(env, "Syscall exception while in user mode. "
1287 "Aborting\n");
1288 break;
1289 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1290 EXCP_DUMP(env, "No APU instruction allowed\n");
1291 info.si_signo = TARGET_SIGILL;
1292 info.si_errno = 0;
1293 info.si_code = TARGET_ILL_COPROC;
1294 info._sifields._sigfault._addr = env->nip - 4;
1295 queue_signal(env, info.si_signo, &info);
1296 break;
1297 case POWERPC_EXCP_DECR: /* Decrementer exception */
1298 cpu_abort(env, "Decrementer interrupt while in user mode. "
1299 "Aborting\n");
1300 break;
1301 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1302 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1303 "Aborting\n");
1304 break;
1305 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1306 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1307 "Aborting\n");
1308 break;
1309 case POWERPC_EXCP_DTLB: /* Data TLB error */
1310 cpu_abort(env, "Data TLB exception while in user mode. "
1311 "Aborting\n");
1312 break;
1313 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1314 cpu_abort(env, "Instruction TLB exception while in user mode. "
1315 "Aborting\n");
1316 break;
1317 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1318 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1319 info.si_signo = TARGET_SIGILL;
1320 info.si_errno = 0;
1321 info.si_code = TARGET_ILL_COPROC;
1322 info._sifields._sigfault._addr = env->nip - 4;
1323 queue_signal(env, info.si_signo, &info);
1324 break;
1325 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1326 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1327 break;
1328 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1329 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1330 break;
1331 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1332 cpu_abort(env, "Performance monitor exception not handled\n");
1333 break;
1334 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1335 cpu_abort(env, "Doorbell interrupt while in user mode. "
1336 "Aborting\n");
1337 break;
1338 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1339 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1340 "Aborting\n");
1341 break;
1342 case POWERPC_EXCP_RESET: /* System reset exception */
1343 cpu_abort(env, "Reset interrupt while in user mode. "
1344 "Aborting\n");
1345 break;
1346 case POWERPC_EXCP_DSEG: /* Data segment exception */
1347 cpu_abort(env, "Data segment exception while in user mode. "
1348 "Aborting\n");
1349 break;
1350 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1351 cpu_abort(env, "Instruction segment exception "
1352 "while in user mode. Aborting\n");
1353 break;
1354 /* PowerPC 64 with hypervisor mode support */
1355 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1356 cpu_abort(env, "Hypervisor decrementer interrupt "
1357 "while in user mode. Aborting\n");
1358 break;
1359 case POWERPC_EXCP_TRACE: /* Trace exception */
1360 /* Nothing to do:
1361 * we use this exception to emulate step-by-step execution mode.
1362 */
1363 break;
1364 /* PowerPC 64 with hypervisor mode support */
1365 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1366 cpu_abort(env, "Hypervisor data storage exception "
1367 "while in user mode. Aborting\n");
1368 break;
1369 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1370 cpu_abort(env, "Hypervisor instruction storage exception "
1371 "while in user mode. Aborting\n");
1372 break;
1373 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1374 cpu_abort(env, "Hypervisor data segment exception "
1375 "while in user mode. Aborting\n");
1376 break;
1377 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1378 cpu_abort(env, "Hypervisor instruction segment exception "
1379 "while in user mode. Aborting\n");
1380 break;
1381 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1382 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1383 info.si_signo = TARGET_SIGILL;
1384 info.si_errno = 0;
1385 info.si_code = TARGET_ILL_COPROC;
1386 info._sifields._sigfault._addr = env->nip - 4;
1387 queue_signal(env, info.si_signo, &info);
1388 break;
1389 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1390 cpu_abort(env, "Programable interval timer interrupt "
1391 "while in user mode. Aborting\n");
1392 break;
1393 case POWERPC_EXCP_IO: /* IO error exception */
1394 cpu_abort(env, "IO error exception while in user mode. "
1395 "Aborting\n");
1396 break;
1397 case POWERPC_EXCP_RUNM: /* Run mode exception */
1398 cpu_abort(env, "Run mode exception while in user mode. "
1399 "Aborting\n");
1400 break;
1401 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1402 cpu_abort(env, "Emulation trap exception not handled\n");
1403 break;
1404 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1405 cpu_abort(env, "Instruction fetch TLB exception "
1406 "while in user-mode. Aborting");
1407 break;
1408 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1409 cpu_abort(env, "Data load TLB exception while in user-mode. "
1410 "Aborting");
1411 break;
1412 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1413 cpu_abort(env, "Data store TLB exception while in user-mode. "
1414 "Aborting");
1415 break;
1416 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1417 cpu_abort(env, "Floating-point assist exception not handled\n");
1418 break;
1419 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1420 cpu_abort(env, "Instruction address breakpoint exception "
1421 "not handled\n");
1422 break;
1423 case POWERPC_EXCP_SMI: /* System management interrupt */
1424 cpu_abort(env, "System management interrupt while in user mode. "
1425 "Aborting\n");
1426 break;
1427 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1428 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1429 "Aborting\n");
1430 break;
1431 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1432 cpu_abort(env, "Performance monitor exception not handled\n");
1433 break;
1434 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1435 cpu_abort(env, "Vector assist exception not handled\n");
1436 break;
1437 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1438 cpu_abort(env, "Soft patch exception not handled\n");
1439 break;
1440 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1441 cpu_abort(env, "Maintenance exception while in user mode. "
1442 "Aborting\n");
1443 break;
1444 case POWERPC_EXCP_STOP: /* stop translation */
1445 /* We did invalidate the instruction cache. Go on */
1446 break;
1447 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1448 /* We just stopped because of a branch. Go on */
1449 break;
1450 case POWERPC_EXCP_SYSCALL_USER:
1451 /* system call in user-mode emulation */
1452 /* WARNING:
1453 * PPC ABI uses overflow flag in cr0 to signal an error
1454 * in syscalls.
1455 */
1456 #if 0
1457 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1458 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1459 #endif
1460 env->crf[0] &= ~0x1;
1461 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1462 env->gpr[5], env->gpr[6], env->gpr[7],
1463 env->gpr[8]);
1464 if (ret > (uint32_t)(-515)) {
1465 env->crf[0] |= 0x1;
1466 ret = -ret;
1467 }
1468 env->gpr[3] = ret;
1469 #if 0
1470 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1471 #endif
1472 break;
1473 case EXCP_DEBUG:
1474 {
1475 int sig;
1476
1477 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1478 if (sig) {
1479 info.si_signo = sig;
1480 info.si_errno = 0;
1481 info.si_code = TARGET_TRAP_BRKPT;
1482 queue_signal(env, info.si_signo, &info);
1483 }
1484 }
1485 break;
1486 case EXCP_INTERRUPT:
1487 /* just indicate that signals should be handled asap */
1488 break;
1489 default:
1490 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1491 break;
1492 }
1493 process_pending_signals(env);
1494 }
1495 }
1496 #endif
1497
1498 #ifdef TARGET_MIPS
1499
1500 #define MIPS_SYS(name, args) args,
1501
1502 static const uint8_t mips_syscall_args[] = {
1503 MIPS_SYS(sys_syscall , 0) /* 4000 */
1504 MIPS_SYS(sys_exit , 1)
1505 MIPS_SYS(sys_fork , 0)
1506 MIPS_SYS(sys_read , 3)
1507 MIPS_SYS(sys_write , 3)
1508 MIPS_SYS(sys_open , 3) /* 4005 */
1509 MIPS_SYS(sys_close , 1)
1510 MIPS_SYS(sys_waitpid , 3)
1511 MIPS_SYS(sys_creat , 2)
1512 MIPS_SYS(sys_link , 2)
1513 MIPS_SYS(sys_unlink , 1) /* 4010 */
1514 MIPS_SYS(sys_execve , 0)
1515 MIPS_SYS(sys_chdir , 1)
1516 MIPS_SYS(sys_time , 1)
1517 MIPS_SYS(sys_mknod , 3)
1518 MIPS_SYS(sys_chmod , 2) /* 4015 */
1519 MIPS_SYS(sys_lchown , 3)
1520 MIPS_SYS(sys_ni_syscall , 0)
1521 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1522 MIPS_SYS(sys_lseek , 3)
1523 MIPS_SYS(sys_getpid , 0) /* 4020 */
1524 MIPS_SYS(sys_mount , 5)
1525 MIPS_SYS(sys_oldumount , 1)
1526 MIPS_SYS(sys_setuid , 1)
1527 MIPS_SYS(sys_getuid , 0)
1528 MIPS_SYS(sys_stime , 1) /* 4025 */
1529 MIPS_SYS(sys_ptrace , 4)
1530 MIPS_SYS(sys_alarm , 1)
1531 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1532 MIPS_SYS(sys_pause , 0)
1533 MIPS_SYS(sys_utime , 2) /* 4030 */
1534 MIPS_SYS(sys_ni_syscall , 0)
1535 MIPS_SYS(sys_ni_syscall , 0)
1536 MIPS_SYS(sys_access , 2)
1537 MIPS_SYS(sys_nice , 1)
1538 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1539 MIPS_SYS(sys_sync , 0)
1540 MIPS_SYS(sys_kill , 2)
1541 MIPS_SYS(sys_rename , 2)
1542 MIPS_SYS(sys_mkdir , 2)
1543 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1544 MIPS_SYS(sys_dup , 1)
1545 MIPS_SYS(sys_pipe , 0)
1546 MIPS_SYS(sys_times , 1)
1547 MIPS_SYS(sys_ni_syscall , 0)
1548 MIPS_SYS(sys_brk , 1) /* 4045 */
1549 MIPS_SYS(sys_setgid , 1)
1550 MIPS_SYS(sys_getgid , 0)
1551 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1552 MIPS_SYS(sys_geteuid , 0)
1553 MIPS_SYS(sys_getegid , 0) /* 4050 */
1554 MIPS_SYS(sys_acct , 0)
1555 MIPS_SYS(sys_umount , 2)
1556 MIPS_SYS(sys_ni_syscall , 0)
1557 MIPS_SYS(sys_ioctl , 3)
1558 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1559 MIPS_SYS(sys_ni_syscall , 2)
1560 MIPS_SYS(sys_setpgid , 2)
1561 MIPS_SYS(sys_ni_syscall , 0)
1562 MIPS_SYS(sys_olduname , 1)
1563 MIPS_SYS(sys_umask , 1) /* 4060 */
1564 MIPS_SYS(sys_chroot , 1)
1565 MIPS_SYS(sys_ustat , 2)
1566 MIPS_SYS(sys_dup2 , 2)
1567 MIPS_SYS(sys_getppid , 0)
1568 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1569 MIPS_SYS(sys_setsid , 0)
1570 MIPS_SYS(sys_sigaction , 3)
1571 MIPS_SYS(sys_sgetmask , 0)
1572 MIPS_SYS(sys_ssetmask , 1)
1573 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1574 MIPS_SYS(sys_setregid , 2)
1575 MIPS_SYS(sys_sigsuspend , 0)
1576 MIPS_SYS(sys_sigpending , 1)
1577 MIPS_SYS(sys_sethostname , 2)
1578 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1579 MIPS_SYS(sys_getrlimit , 2)
1580 MIPS_SYS(sys_getrusage , 2)
1581 MIPS_SYS(sys_gettimeofday, 2)
1582 MIPS_SYS(sys_settimeofday, 2)
1583 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1584 MIPS_SYS(sys_setgroups , 2)
1585 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1586 MIPS_SYS(sys_symlink , 2)
1587 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1588 MIPS_SYS(sys_readlink , 3) /* 4085 */
1589 MIPS_SYS(sys_uselib , 1)
1590 MIPS_SYS(sys_swapon , 2)
1591 MIPS_SYS(sys_reboot , 3)
1592 MIPS_SYS(old_readdir , 3)
1593 MIPS_SYS(old_mmap , 6) /* 4090 */
1594 MIPS_SYS(sys_munmap , 2)
1595 MIPS_SYS(sys_truncate , 2)
1596 MIPS_SYS(sys_ftruncate , 2)
1597 MIPS_SYS(sys_fchmod , 2)
1598 MIPS_SYS(sys_fchown , 3) /* 4095 */
1599 MIPS_SYS(sys_getpriority , 2)
1600 MIPS_SYS(sys_setpriority , 3)
1601 MIPS_SYS(sys_ni_syscall , 0)
1602 MIPS_SYS(sys_statfs , 2)
1603 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1604 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1605 MIPS_SYS(sys_socketcall , 2)
1606 MIPS_SYS(sys_syslog , 3)
1607 MIPS_SYS(sys_setitimer , 3)
1608 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1609 MIPS_SYS(sys_newstat , 2)
1610 MIPS_SYS(sys_newlstat , 2)
1611 MIPS_SYS(sys_newfstat , 2)
1612 MIPS_SYS(sys_uname , 1)
1613 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1614 MIPS_SYS(sys_vhangup , 0)
1615 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1616 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1617 MIPS_SYS(sys_wait4 , 4)
1618 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1619 MIPS_SYS(sys_sysinfo , 1)
1620 MIPS_SYS(sys_ipc , 6)
1621 MIPS_SYS(sys_fsync , 1)
1622 MIPS_SYS(sys_sigreturn , 0)
1623 MIPS_SYS(sys_clone , 0) /* 4120 */
1624 MIPS_SYS(sys_setdomainname, 2)
1625 MIPS_SYS(sys_newuname , 1)
1626 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1627 MIPS_SYS(sys_adjtimex , 1)
1628 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1629 MIPS_SYS(sys_sigprocmask , 3)
1630 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1631 MIPS_SYS(sys_init_module , 5)
1632 MIPS_SYS(sys_delete_module, 1)
1633 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1634 MIPS_SYS(sys_quotactl , 0)
1635 MIPS_SYS(sys_getpgid , 1)
1636 MIPS_SYS(sys_fchdir , 1)
1637 MIPS_SYS(sys_bdflush , 2)
1638 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1639 MIPS_SYS(sys_personality , 1)
1640 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1641 MIPS_SYS(sys_setfsuid , 1)
1642 MIPS_SYS(sys_setfsgid , 1)
1643 MIPS_SYS(sys_llseek , 5) /* 4140 */
1644 MIPS_SYS(sys_getdents , 3)
1645 MIPS_SYS(sys_select , 5)
1646 MIPS_SYS(sys_flock , 2)
1647 MIPS_SYS(sys_msync , 3)
1648 MIPS_SYS(sys_readv , 3) /* 4145 */
1649 MIPS_SYS(sys_writev , 3)
1650 MIPS_SYS(sys_cacheflush , 3)
1651 MIPS_SYS(sys_cachectl , 3)
1652 MIPS_SYS(sys_sysmips , 4)
1653 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1654 MIPS_SYS(sys_getsid , 1)
1655 MIPS_SYS(sys_fdatasync , 0)
1656 MIPS_SYS(sys_sysctl , 1)
1657 MIPS_SYS(sys_mlock , 2)
1658 MIPS_SYS(sys_munlock , 2) /* 4155 */
1659 MIPS_SYS(sys_mlockall , 1)
1660 MIPS_SYS(sys_munlockall , 0)
1661 MIPS_SYS(sys_sched_setparam, 2)
1662 MIPS_SYS(sys_sched_getparam, 2)
1663 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1664 MIPS_SYS(sys_sched_getscheduler, 1)
1665 MIPS_SYS(sys_sched_yield , 0)
1666 MIPS_SYS(sys_sched_get_priority_max, 1)
1667 MIPS_SYS(sys_sched_get_priority_min, 1)
1668 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1669 MIPS_SYS(sys_nanosleep, 2)
1670 MIPS_SYS(sys_mremap , 4)
1671 MIPS_SYS(sys_accept , 3)
1672 MIPS_SYS(sys_bind , 3)
1673 MIPS_SYS(sys_connect , 3) /* 4170 */
1674 MIPS_SYS(sys_getpeername , 3)
1675 MIPS_SYS(sys_getsockname , 3)
1676 MIPS_SYS(sys_getsockopt , 5)
1677 MIPS_SYS(sys_listen , 2)
1678 MIPS_SYS(sys_recv , 4) /* 4175 */
1679 MIPS_SYS(sys_recvfrom , 6)
1680 MIPS_SYS(sys_recvmsg , 3)
1681 MIPS_SYS(sys_send , 4)
1682 MIPS_SYS(sys_sendmsg , 3)
1683 MIPS_SYS(sys_sendto , 6) /* 4180 */
1684 MIPS_SYS(sys_setsockopt , 5)
1685 MIPS_SYS(sys_shutdown , 2)
1686 MIPS_SYS(sys_socket , 3)
1687 MIPS_SYS(sys_socketpair , 4)
1688 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1689 MIPS_SYS(sys_getresuid , 3)
1690 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1691 MIPS_SYS(sys_poll , 3)
1692 MIPS_SYS(sys_nfsservctl , 3)
1693 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1694 MIPS_SYS(sys_getresgid , 3)
1695 MIPS_SYS(sys_prctl , 5)
1696 MIPS_SYS(sys_rt_sigreturn, 0)
1697 MIPS_SYS(sys_rt_sigaction, 4)
1698 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1699 MIPS_SYS(sys_rt_sigpending, 2)
1700 MIPS_SYS(sys_rt_sigtimedwait, 4)
1701 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1702 MIPS_SYS(sys_rt_sigsuspend, 0)
1703 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1704 MIPS_SYS(sys_pwrite64 , 6)
1705 MIPS_SYS(sys_chown , 3)
1706 MIPS_SYS(sys_getcwd , 2)
1707 MIPS_SYS(sys_capget , 2)
1708 MIPS_SYS(sys_capset , 2) /* 4205 */
1709 MIPS_SYS(sys_sigaltstack , 0)
1710 MIPS_SYS(sys_sendfile , 4)
1711 MIPS_SYS(sys_ni_syscall , 0)
1712 MIPS_SYS(sys_ni_syscall , 0)
1713 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1714 MIPS_SYS(sys_truncate64 , 4)
1715 MIPS_SYS(sys_ftruncate64 , 4)
1716 MIPS_SYS(sys_stat64 , 2)
1717 MIPS_SYS(sys_lstat64 , 2)
1718 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1719 MIPS_SYS(sys_pivot_root , 2)
1720 MIPS_SYS(sys_mincore , 3)
1721 MIPS_SYS(sys_madvise , 3)
1722 MIPS_SYS(sys_getdents64 , 3)
1723 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1724 MIPS_SYS(sys_ni_syscall , 0)
1725 MIPS_SYS(sys_gettid , 0)
1726 MIPS_SYS(sys_readahead , 5)
1727 MIPS_SYS(sys_setxattr , 5)
1728 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1729 MIPS_SYS(sys_fsetxattr , 5)
1730 MIPS_SYS(sys_getxattr , 4)
1731 MIPS_SYS(sys_lgetxattr , 4)
1732 MIPS_SYS(sys_fgetxattr , 4)
1733 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1734 MIPS_SYS(sys_llistxattr , 3)
1735 MIPS_SYS(sys_flistxattr , 3)
1736 MIPS_SYS(sys_removexattr , 2)
1737 MIPS_SYS(sys_lremovexattr, 2)
1738 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1739 MIPS_SYS(sys_tkill , 2)
1740 MIPS_SYS(sys_sendfile64 , 5)
1741 MIPS_SYS(sys_futex , 2)
1742 MIPS_SYS(sys_sched_setaffinity, 3)
1743 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1744 MIPS_SYS(sys_io_setup , 2)
1745 MIPS_SYS(sys_io_destroy , 1)
1746 MIPS_SYS(sys_io_getevents, 5)
1747 MIPS_SYS(sys_io_submit , 3)
1748 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1749 MIPS_SYS(sys_exit_group , 1)
1750 MIPS_SYS(sys_lookup_dcookie, 3)
1751 MIPS_SYS(sys_epoll_create, 1)
1752 MIPS_SYS(sys_epoll_ctl , 4)
1753 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1754 MIPS_SYS(sys_remap_file_pages, 5)
1755 MIPS_SYS(sys_set_tid_address, 1)
1756 MIPS_SYS(sys_restart_syscall, 0)
1757 MIPS_SYS(sys_fadvise64_64, 7)
1758 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1759 MIPS_SYS(sys_fstatfs64 , 2)
1760 MIPS_SYS(sys_timer_create, 3)
1761 MIPS_SYS(sys_timer_settime, 4)
1762 MIPS_SYS(sys_timer_gettime, 2)
1763 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1764 MIPS_SYS(sys_timer_delete, 1)
1765 MIPS_SYS(sys_clock_settime, 2)
1766 MIPS_SYS(sys_clock_gettime, 2)
1767 MIPS_SYS(sys_clock_getres, 2)
1768 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1769 MIPS_SYS(sys_tgkill , 3)
1770 MIPS_SYS(sys_utimes , 2)
1771 MIPS_SYS(sys_mbind , 4)
1772 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1773 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1774 MIPS_SYS(sys_mq_open , 4)
1775 MIPS_SYS(sys_mq_unlink , 1)
1776 MIPS_SYS(sys_mq_timedsend, 5)
1777 MIPS_SYS(sys_mq_timedreceive, 5)
1778 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1779 MIPS_SYS(sys_mq_getsetattr, 3)
1780 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1781 MIPS_SYS(sys_waitid , 4)
1782 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1783 MIPS_SYS(sys_add_key , 5)
1784 MIPS_SYS(sys_request_key, 4)
1785 MIPS_SYS(sys_keyctl , 5)
1786 MIPS_SYS(sys_set_thread_area, 1)
1787 MIPS_SYS(sys_inotify_init, 0)
1788 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1789 MIPS_SYS(sys_inotify_rm_watch, 2)
1790 MIPS_SYS(sys_migrate_pages, 4)
1791 MIPS_SYS(sys_openat, 4)
1792 MIPS_SYS(sys_mkdirat, 3)
1793 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1794 MIPS_SYS(sys_fchownat, 5)
1795 MIPS_SYS(sys_futimesat, 3)
1796 MIPS_SYS(sys_fstatat64, 4)
1797 MIPS_SYS(sys_unlinkat, 3)
1798 MIPS_SYS(sys_renameat, 4) /* 4295 */
1799 MIPS_SYS(sys_linkat, 5)
1800 MIPS_SYS(sys_symlinkat, 3)
1801 MIPS_SYS(sys_readlinkat, 4)
1802 MIPS_SYS(sys_fchmodat, 3)
1803 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1804 MIPS_SYS(sys_pselect6, 6)
1805 MIPS_SYS(sys_ppoll, 5)
1806 MIPS_SYS(sys_unshare, 1)
1807 MIPS_SYS(sys_splice, 4)
1808 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1809 MIPS_SYS(sys_tee, 4)
1810 MIPS_SYS(sys_vmsplice, 4)
1811 MIPS_SYS(sys_move_pages, 6)
1812 MIPS_SYS(sys_set_robust_list, 2)
1813 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1814 MIPS_SYS(sys_kexec_load, 4)
1815 MIPS_SYS(sys_getcpu, 3)
1816 MIPS_SYS(sys_epoll_pwait, 6)
1817 MIPS_SYS(sys_ioprio_set, 3)
1818 MIPS_SYS(sys_ioprio_get, 2)
1819 };
1820
1821 #undef MIPS_SYS
1822
1823 void cpu_loop(CPUMIPSState *env)
1824 {
1825 target_siginfo_t info;
1826 int trapnr, ret;
1827 unsigned int syscall_num;
1828
1829 for(;;) {
1830 trapnr = cpu_mips_exec(env);
1831 switch(trapnr) {
1832 case EXCP_SYSCALL:
1833 syscall_num = env->active_tc.gpr[2] - 4000;
1834 env->active_tc.PC += 4;
1835 if (syscall_num >= sizeof(mips_syscall_args)) {
1836 ret = -ENOSYS;
1837 } else {
1838 int nb_args;
1839 abi_ulong sp_reg;
1840 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1841
1842 nb_args = mips_syscall_args[syscall_num];
1843 sp_reg = env->active_tc.gpr[29];
1844 switch (nb_args) {
1845 /* these arguments are taken from the stack */
1846 /* FIXME - what to do if get_user() fails? */
1847 case 8: get_user_ual(arg8, sp_reg + 28);
1848 case 7: get_user_ual(arg7, sp_reg + 24);
1849 case 6: get_user_ual(arg6, sp_reg + 20);
1850 case 5: get_user_ual(arg5, sp_reg + 16);
1851 default:
1852 break;
1853 }
1854 ret = do_syscall(env, env->active_tc.gpr[2],
1855 env->active_tc.gpr[4],
1856 env->active_tc.gpr[5],
1857 env->active_tc.gpr[6],
1858 env->active_tc.gpr[7],
1859 arg5, arg6/*, arg7, arg8*/);
1860 }
1861 if ((unsigned int)ret >= (unsigned int)(-1133)) {
1862 env->active_tc.gpr[7] = 1; /* error flag */
1863 ret = -ret;
1864 } else {
1865 env->active_tc.gpr[7] = 0; /* error flag */
1866 }
1867 env->active_tc.gpr[2] = ret;
1868 break;
1869 case EXCP_TLBL:
1870 case EXCP_TLBS:
1871 case EXCP_CpU:
1872 case EXCP_RI:
1873 info.si_signo = TARGET_SIGILL;
1874 info.si_errno = 0;
1875 info.si_code = 0;
1876 queue_signal(env, info.si_signo, &info);
1877 break;
1878 case EXCP_INTERRUPT:
1879 /* just indicate that signals should be handled asap */
1880 break;
1881 case EXCP_DEBUG:
1882 {
1883 int sig;
1884
1885 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1886 if (sig)
1887 {
1888 info.si_signo = sig;
1889 info.si_errno = 0;
1890 info.si_code = TARGET_TRAP_BRKPT;
1891 queue_signal(env, info.si_signo, &info);
1892 }
1893 }
1894 break;
1895 default:
1896 // error:
1897 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1898 trapnr);
1899 cpu_dump_state(env, stderr, fprintf, 0);
1900 abort();
1901 }
1902 process_pending_signals(env);
1903 }
1904 }
1905 #endif
1906
1907 #ifdef TARGET_SH4
1908 void cpu_loop (CPUState *env)
1909 {
1910 int trapnr, ret;
1911 target_siginfo_t info;
1912
1913 while (1) {
1914 trapnr = cpu_sh4_exec (env);
1915
1916 switch (trapnr) {
1917 case 0x160:
1918 env->pc += 2;
1919 ret = do_syscall(env,
1920 env->gregs[3],
1921 env->gregs[4],
1922 env->gregs[5],
1923 env->gregs[6],
1924 env->gregs[7],
1925 env->gregs[0],
1926 env->gregs[1]);
1927 env->gregs[0] = ret;
1928 break;
1929 case EXCP_INTERRUPT:
1930 /* just indicate that signals should be handled asap */
1931 break;
1932 case EXCP_DEBUG:
1933 {
1934 int sig;
1935
1936 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1937 if (sig)
1938 {
1939 info.si_signo = sig;
1940 info.si_errno = 0;
1941 info.si_code = TARGET_TRAP_BRKPT;
1942 queue_signal(env, info.si_signo, &info);
1943 }
1944 }
1945 break;
1946 case 0xa0:
1947 case 0xc0:
1948 info.si_signo = SIGSEGV;
1949 info.si_errno = 0;
1950 info.si_code = TARGET_SEGV_MAPERR;
1951 info._sifields._sigfault._addr = env->tea;
1952 queue_signal(env, info.si_signo, &info);
1953 break;
1954
1955 default:
1956 printf ("Unhandled trap: 0x%x\n", trapnr);
1957 cpu_dump_state(env, stderr, fprintf, 0);
1958 exit (1);
1959 }
1960 process_pending_signals (env);
1961 }
1962 }
1963 #endif
1964
1965 #ifdef TARGET_CRIS
1966 void cpu_loop (CPUState *env)
1967 {
1968 int trapnr, ret;
1969 target_siginfo_t info;
1970
1971 while (1) {
1972 trapnr = cpu_cris_exec (env);
1973 switch (trapnr) {
1974 case 0xaa:
1975 {
1976 info.si_signo = SIGSEGV;
1977 info.si_errno = 0;
1978 /* XXX: check env->error_code */
1979 info.si_code = TARGET_SEGV_MAPERR;
1980 info._sifields._sigfault._addr = env->pregs[PR_EDA];
1981 queue_signal(env, info.si_signo, &info);
1982 }
1983 break;
1984 case EXCP_INTERRUPT:
1985 /* just indicate that signals should be handled asap */
1986 break;
1987 case EXCP_BREAK:
1988 ret = do_syscall(env,
1989 env->regs[9],
1990 env->regs[10],
1991 env->regs[11],
1992 env->regs[12],
1993 env->regs[13],
1994 env->pregs[7],
1995 env->pregs[11]);
1996 env->regs[10] = ret;
1997 break;
1998 case EXCP_DEBUG:
1999 {
2000 int sig;
2001
2002 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2003 if (sig)
2004 {
2005 info.si_signo = sig;
2006 info.si_errno = 0;
2007 info.si_code = TARGET_TRAP_BRKPT;
2008 queue_signal(env, info.si_signo, &info);
2009 }
2010 }
2011 break;
2012 default:
2013 printf ("Unhandled trap: 0x%x\n", trapnr);
2014 cpu_dump_state(env, stderr, fprintf, 0);
2015 exit (1);
2016 }
2017 process_pending_signals (env);
2018 }
2019 }
2020 #endif
2021
2022 #ifdef TARGET_M68K
2023
2024 void cpu_loop(CPUM68KState *env)
2025 {
2026 int trapnr;
2027 unsigned int n;
2028 target_siginfo_t info;
2029 TaskState *ts = env->opaque;
2030
2031 for(;;) {
2032 trapnr = cpu_m68k_exec(env);
2033 switch(trapnr) {
2034 case EXCP_ILLEGAL:
2035 {
2036 if (ts->sim_syscalls) {
2037 uint16_t nr;
2038 nr = lduw(env->pc + 2);
2039 env->pc += 4;
2040 do_m68k_simcall(env, nr);
2041 } else {
2042 goto do_sigill;
2043 }
2044 }
2045 break;
2046 case EXCP_HALT_INSN:
2047 /* Semihosing syscall. */
2048 env->pc += 4;
2049 do_m68k_semihosting(env, env->dregs[0]);
2050 break;
2051 case EXCP_LINEA:
2052 case EXCP_LINEF:
2053 case EXCP_UNSUPPORTED:
2054 do_sigill:
2055 info.si_signo = SIGILL;
2056 info.si_errno = 0;
2057 info.si_code = TARGET_ILL_ILLOPN;
2058 info._sifields._sigfault._addr = env->pc;
2059 queue_signal(env, info.si_signo, &info);
2060 break;
2061 case EXCP_TRAP0:
2062 {
2063 ts->sim_syscalls = 0;
2064 n = env->dregs[0];
2065 env->pc += 2;
2066 env->dregs[0] = do_syscall(env,
2067 n,
2068 env->dregs[1],
2069 env->dregs[2],
2070 env->dregs[3],
2071 env->dregs[4],
2072 env->dregs[5],
2073 env->aregs[0]);
2074 }
2075 break;
2076 case EXCP_INTERRUPT:
2077 /* just indicate that signals should be handled asap */
2078 break;
2079 case EXCP_ACCESS:
2080 {
2081 info.si_signo = SIGSEGV;
2082 info.si_errno = 0;
2083 /* XXX: check env->error_code */
2084 info.si_code = TARGET_SEGV_MAPERR;
2085 info._sifields._sigfault._addr = env->mmu.ar;
2086 queue_signal(env, info.si_signo, &info);
2087 }
2088 break;
2089 case EXCP_DEBUG:
2090 {
2091 int sig;
2092
2093 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2094 if (sig)
2095 {
2096 info.si_signo = sig;
2097 info.si_errno = 0;
2098 info.si_code = TARGET_TRAP_BRKPT;
2099 queue_signal(env, info.si_signo, &info);
2100 }
2101 }
2102 break;
2103 default:
2104 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2105 trapnr);
2106 cpu_dump_state(env, stderr, fprintf, 0);
2107 abort();
2108 }
2109 process_pending_signals(env);
2110 }
2111 }
2112 #endif /* TARGET_M68K */
2113
2114 #ifdef TARGET_HPPA
2115
2116 void cpu_loop(CPUHPPAState *env)
2117 {
2118 int trapnr;
2119 target_siginfo_t info;
2120
2121 for (;;)
2122 {
2123 trapnr = cpu_hppa_exec(env);
2124 switch (trapnr)
2125 {
2126 case EXCP_DEBUG:
2127 {
2128 int sig;
2129
2130 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2131 if (sig)
2132 {
2133 info.si_signo = sig;
2134 info.si_errno = 0;
2135 info.si_code = TARGET_TRAP_BRKPT;
2136 queue_signal(env, info.si_signo, &info);
2137 }
2138 }
2139 break;
2140 default:
2141 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2142 trapnr);
2143 cpu_dump_state(env, stderr, fprintf, 0);
2144 abort();
2145 }
2146 process_pending_signals(env);
2147 }
2148 }
2149
2150 #endif
2151
2152 #ifdef TARGET_ALPHA
2153 void cpu_loop (CPUState *env)
2154 {
2155 int trapnr;
2156 target_siginfo_t info;
2157
2158 while (1) {
2159 trapnr = cpu_alpha_exec (env);
2160
2161 switch (trapnr) {
2162 case EXCP_RESET:
2163 fprintf(stderr, "Reset requested. Exit\n");
2164 exit(1);
2165 break;
2166 case EXCP_MCHK:
2167 fprintf(stderr, "Machine check exception. Exit\n");
2168 exit(1);
2169 break;
2170 case EXCP_ARITH:
2171 fprintf(stderr, "Arithmetic trap.\n");
2172 exit(1);
2173 break;
2174 case EXCP_HW_INTERRUPT:
2175 fprintf(stderr, "External interrupt. Exit\n");
2176 exit(1);
2177 break;
2178 case EXCP_DFAULT:
2179 fprintf(stderr, "MMU data fault\n");
2180 exit(1);
2181 break;
2182 case EXCP_DTB_MISS_PAL:
2183 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2184 exit(1);
2185 break;
2186 case EXCP_ITB_MISS:
2187 fprintf(stderr, "MMU instruction TLB miss\n");
2188 exit(1);
2189 break;
2190 case EXCP_ITB_ACV:
2191 fprintf(stderr, "MMU instruction access violation\n");
2192 exit(1);
2193 break;
2194 case EXCP_DTB_MISS_NATIVE:
2195 fprintf(stderr, "MMU data TLB miss\n");
2196 exit(1);
2197 break;
2198 case EXCP_UNALIGN:
2199 fprintf(stderr, "Unaligned access\n");
2200 exit(1);
2201 break;
2202 case EXCP_OPCDEC:
2203 fprintf(stderr, "Invalid instruction\n");
2204 exit(1);
2205 break;
2206 case EXCP_FEN:
2207 fprintf(stderr, "Floating-point not allowed\n");
2208 exit(1);
2209 break;
2210 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2211 call_pal(env, (trapnr >> 6) | 0x80);
2212 break;
2213 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2214 fprintf(stderr, "Privileged call to PALcode\n");
2215 exit(1);
2216 break;
2217 case EXCP_DEBUG:
2218 {
2219 int sig;
2220
2221 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2222 if (sig)
2223 {
2224 info.si_signo = sig;
2225 info.si_errno = 0;
2226 info.si_code = TARGET_TRAP_BRKPT;
2227 queue_signal(env, info.si_signo, &info);
2228 }
2229 }
2230 break;
2231 default:
2232 printf ("Unhandled trap: 0x%x\n", trapnr);
2233 cpu_dump_state(env, stderr, fprintf, 0);
2234 exit (1);
2235 }
2236 process_pending_signals (env);
2237 }
2238 }
2239 #endif /* TARGET_ALPHA */
2240
2241 static void usage(void)
2242 {
2243 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2244 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2245 "Linux CPU emulator (compiled for %s emulation)\n"
2246 "\n"
2247 "Standard options:\n"
2248 "-h print this help\n"
2249 "-g port wait gdb connection to port\n"
2250 "-L path set the elf interpreter prefix (default=%s)\n"
2251 "-s size set the stack size in bytes (default=%ld)\n"
2252 "-cpu model select CPU (-cpu ? for list)\n"
2253 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2254 "-E var=value sets/modifies targets environment variable(s)\n"
2255 "-U var unsets targets environment variable(s)\n"
2256 "\n"
2257 "Debug options:\n"
2258 "-d options activate log (logfile=%s)\n"
2259 "-p pagesize set the host page size to 'pagesize'\n"
2260 "-singlestep always run in singlestep mode\n"
2261 "-strace log system calls\n"
2262 "\n"
2263 "Environment variables:\n"
2264 "QEMU_STRACE Print system calls and arguments similar to the\n"
2265 " 'strace' program. Enable by setting to any value.\n"
2266 "You can use -E and -U options to set/unset environment variables\n"
2267 "for target process. It is possible to provide several variables\n"
2268 "by repeating the option. For example:\n"
2269 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2270 "Note that if you provide several changes to single variable\n"
2271 "last change will stay in effect.\n"
2272 ,
2273 TARGET_ARCH,
2274 interp_prefix,
2275 x86_stack_size,
2276 DEBUG_LOGFILE);
2277 exit(1);
2278 }
2279
2280 THREAD CPUState *thread_env;
2281
2282 /* Assumes contents are already zeroed. */
2283 void init_task_state(TaskState *ts)
2284 {
2285 int i;
2286
2287 ts->used = 1;
2288 ts->first_free = ts->sigqueue_table;
2289 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2290 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2291 }
2292 ts->sigqueue_table[i].next = NULL;
2293 }
2294
2295 int main(int argc, char **argv, char **envp)
2296 {
2297 const char *filename;
2298 const char *cpu_model;
2299 struct target_pt_regs regs1, *regs = &regs1;
2300 struct image_info info1, *info = &info1;
2301 TaskState ts1, *ts = &ts1;
2302 CPUState *env;
2303 int optind;
2304 const char *r;
2305 int gdbstub_port = 0;
2306 char **target_environ, **wrk;
2307 envlist_t *envlist = NULL;
2308
2309 if (argc <= 1)
2310 usage();
2311
2312 qemu_cache_utils_init(envp);
2313
2314 /* init debug */
2315 cpu_set_log_filename(DEBUG_LOGFILE);
2316
2317 if ((envlist = envlist_create()) == NULL) {
2318 (void) fprintf(stderr, "Unable to allocate envlist\n");
2319 exit(1);
2320 }
2321
2322 /* add current environment into the list */
2323 for (wrk = environ; *wrk != NULL; wrk++) {
2324 (void) envlist_setenv(envlist, *wrk);
2325 }
2326
2327 cpu_model = NULL;
2328 optind = 1;
2329 for(;;) {
2330 if (optind >= argc)
2331 break;
2332 r = argv[optind];
2333 if (r[0] != '-')
2334 break;
2335 optind++;
2336 r++;
2337 if (!strcmp(r, "-")) {
2338 break;
2339 } else if (!strcmp(r, "d")) {
2340 int mask;
2341 const CPULogItem *item;
2342
2343 if (optind >= argc)
2344 break;
2345
2346 r = argv[optind++];
2347 mask = cpu_str_to_log_mask(r);
2348 if (!mask) {
2349 printf("Log items (comma separated):\n");
2350 for(item = cpu_log_items; item->mask != 0; item++) {
2351 printf("%-10s %s\n", item->name, item->help);
2352 }
2353 exit(1);
2354 }
2355 cpu_set_log(mask);
2356 } else if (!strcmp(r, "E")) {
2357 r = argv[optind++];
2358 if (envlist_setenv(envlist, r) != 0)
2359 usage();
2360 } else if (!strcmp(r, "U")) {
2361 r = argv[optind++];
2362 if (envlist_unsetenv(envlist, r) != 0)
2363 usage();
2364 } else if (!strcmp(r, "s")) {
2365 if (optind >= argc)
2366 break;
2367 r = argv[optind++];
2368 x86_stack_size = strtol(r, (char **)&r, 0);
2369 if (x86_stack_size <= 0)
2370 usage();
2371 if (*r == 'M')
2372 x86_stack_size *= 1024 * 1024;
2373 else if (*r == 'k' || *r == 'K')
2374 x86_stack_size *= 1024;
2375 } else if (!strcmp(r, "L")) {
2376 interp_prefix = argv[optind++];
2377 } else if (!strcmp(r, "p")) {
2378 if (optind >= argc)
2379 break;
2380 qemu_host_page_size = atoi(argv[optind++]);
2381 if (qemu_host_page_size == 0 ||
2382 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2383 fprintf(stderr, "page size must be a power of two\n");
2384 exit(1);
2385 }
2386 } else if (!strcmp(r, "g")) {
2387 if (optind >= argc)
2388 break;
2389 gdbstub_port = atoi(argv[optind++]);
2390 } else if (!strcmp(r, "r")) {
2391 qemu_uname_release = argv[optind++];
2392 } else if (!strcmp(r, "cpu")) {
2393 cpu_model = argv[optind++];
2394 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2395 /* XXX: implement xxx_cpu_list for targets that still miss it */
2396 #if defined(cpu_list)
2397 cpu_list(stdout, &fprintf);
2398 #endif
2399 exit(1);
2400 }
2401 } else if (!strcmp(r, "drop-ld-preload")) {
2402 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
2403 } else if (!strcmp(r, "singlestep")) {
2404 singlestep = 1;
2405 } else if (!strcmp(r, "strace")) {
2406 do_strace = 1;
2407 } else
2408 {
2409 usage();
2410 }
2411 }
2412 if (optind >= argc)
2413 usage();
2414 filename = argv[optind];
2415 exec_path = argv[optind];
2416
2417 /* Zero out regs */
2418 memset(regs, 0, sizeof(struct target_pt_regs));
2419
2420 /* Zero out image_info */
2421 memset(info, 0, sizeof(struct image_info));
2422
2423 /* Scan interp_prefix dir for replacement files. */
2424 init_paths(interp_prefix);
2425
2426 if (cpu_model == NULL) {
2427 #if defined(TARGET_I386)
2428 #ifdef TARGET_X86_64
2429 cpu_model = "qemu64";
2430 #else
2431 cpu_model = "qemu32";
2432 #endif
2433 #elif defined(TARGET_ARM)
2434 cpu_model = "any";
2435 #elif defined(TARGET_M68K)
2436 cpu_model = "any";
2437 #elif defined(TARGET_SPARC)
2438 #ifdef TARGET_SPARC64
2439 cpu_model = "TI UltraSparc II";
2440 #else
2441 cpu_model = "Fujitsu MB86904";
2442 #endif
2443 #elif defined(TARGET_MIPS)
2444 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2445 cpu_model = "20Kc";
2446 #else
2447 cpu_model = "24Kf";
2448 #endif
2449 #elif defined(TARGET_PPC)
2450 #ifdef TARGET_PPC64
2451 cpu_model = "970";
2452 #else
2453 cpu_model = "750";
2454 #endif
2455 #else
2456 cpu_model = "any";
2457 #endif
2458 }
2459 cpu_exec_init_all(0);
2460 /* NOTE: we need to init the CPU at this stage to get
2461 qemu_host_page_size */
2462 env = cpu_init(cpu_model);
2463 if (!env) {
2464 fprintf(stderr, "Unable to find CPU definition\n");
2465 exit(1);
2466 }
2467 thread_env = env;
2468
2469 if (getenv("QEMU_STRACE")) {
2470 do_strace = 1;
2471 }
2472
2473 target_environ = envlist_to_environ(envlist, NULL);
2474 envlist_free(envlist);
2475
2476 if (loader_exec(filename, argv+optind, target_environ, regs, info) != 0) {
2477 printf("Error loading %s\n", filename);
2478 _exit(1);
2479 }
2480
2481 for (wrk = target_environ; *wrk; wrk++) {
2482 free(*wrk);
2483 }
2484
2485 free(target_environ);
2486
2487 if (qemu_log_enabled()) {
2488 log_page_dump();
2489
2490 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2491 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2492 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2493 info->start_code);
2494 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2495 info->start_data);
2496 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2497 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2498 info->start_stack);
2499 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2500 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2501 }
2502
2503 target_set_brk(info->brk);
2504 syscall_init();
2505 signal_init();
2506
2507 /* build Task State */
2508 memset(ts, 0, sizeof(TaskState));
2509 init_task_state(ts);
2510 ts->info = info;
2511 env->opaque = ts;
2512
2513 #if defined(TARGET_I386)
2514 cpu_x86_set_cpl(env, 3);
2515
2516 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2517 env->hflags |= HF_PE_MASK;
2518 if (env->cpuid_features & CPUID_SSE) {
2519 env->cr[4] |= CR4_OSFXSR_MASK;
2520 env->hflags |= HF_OSFXSR_MASK;
2521 }
2522 #ifndef TARGET_ABI32
2523 /* enable 64 bit mode if possible */
2524 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2525 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2526 exit(1);
2527 }
2528 env->cr[4] |= CR4_PAE_MASK;
2529 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2530 env->hflags |= HF_LMA_MASK;
2531 #endif
2532
2533 /* flags setup : we activate the IRQs by default as in user mode */
2534 env->eflags |= IF_MASK;
2535
2536 /* linux register setup */
2537 #ifndef TARGET_ABI32
2538 env->regs[R_EAX] = regs->rax;
2539 env->regs[R_EBX] = regs->rbx;
2540 env->regs[R_ECX] = regs->rcx;
2541 env->regs[R_EDX] = regs->rdx;
2542 env->regs[R_ESI] = regs->rsi;
2543 env->regs[R_EDI] = regs->rdi;
2544 env->regs[R_EBP] = regs->rbp;
2545 env->regs[R_ESP] = regs->rsp;
2546 env->eip = regs->rip;
2547 #else
2548 env->regs[R_EAX] = regs->eax;
2549 env->regs[R_EBX] = regs->ebx;
2550 env->regs[R_ECX] = regs->ecx;
2551 env->regs[R_EDX] = regs->edx;
2552 env->regs[R_ESI] = regs->esi;
2553 env->regs[R_EDI] = regs->edi;
2554 env->regs[R_EBP] = regs->ebp;
2555 env->regs[R_ESP] = regs->esp;
2556 env->eip = regs->eip;
2557 #endif
2558
2559 /* linux interrupt setup */
2560 #ifndef TARGET_ABI32
2561 env->idt.limit = 511;
2562 #else
2563 env->idt.limit = 255;
2564 #endif
2565 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
2566 PROT_READ|PROT_WRITE,
2567 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2568 idt_table = g2h(env->idt.base);
2569 set_idt(0, 0);
2570 set_idt(1, 0);
2571 set_idt(2, 0);
2572 set_idt(3, 3);
2573 set_idt(4, 3);
2574 set_idt(5, 0);
2575 set_idt(6, 0);
2576 set_idt(7, 0);
2577 set_idt(8, 0);
2578 set_idt(9, 0);
2579 set_idt(10, 0);
2580 set_idt(11, 0);
2581 set_idt(12, 0);
2582 set_idt(13, 0);
2583 set_idt(14, 0);
2584 set_idt(15, 0);
2585 set_idt(16, 0);
2586 set_idt(17, 0);
2587 set_idt(18, 0);
2588 set_idt(19, 0);
2589 set_idt(0x80, 3);
2590
2591 /* linux segment setup */
2592 {
2593 uint64_t *gdt_table;
2594 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
2595 PROT_READ|PROT_WRITE,
2596 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2597 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2598 gdt_table = g2h(env->gdt.base);
2599 #ifdef TARGET_ABI32
2600 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2601 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2602 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2603 #else
2604 /* 64 bit code segment */
2605 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2606 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2607 DESC_L_MASK |
2608 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2609 #endif
2610 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2611 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2612 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2613 }
2614 cpu_x86_load_seg(env, R_CS, __USER_CS);
2615 cpu_x86_load_seg(env, R_SS, __USER_DS);
2616 #ifdef TARGET_ABI32
2617 cpu_x86_load_seg(env, R_DS, __USER_DS);
2618 cpu_x86_load_seg(env, R_ES, __USER_DS);
2619 cpu_x86_load_seg(env, R_FS, __USER_DS);
2620 cpu_x86_load_seg(env, R_GS, __USER_DS);
2621 /* This hack makes Wine work... */
2622 env->segs[R_FS].selector = 0;
2623 #else
2624 cpu_x86_load_seg(env, R_DS, 0);
2625 cpu_x86_load_seg(env, R_ES, 0);
2626 cpu_x86_load_seg(env, R_FS, 0);
2627 cpu_x86_load_seg(env, R_GS, 0);
2628 #endif
2629 #elif defined(TARGET_ARM)
2630 {
2631 int i;
2632 cpsr_write(env, regs->uregs[16], 0xffffffff);
2633 for(i = 0; i < 16; i++) {
2634 env->regs[i] = regs->uregs[i];
2635 }
2636 }
2637 #elif defined(TARGET_SPARC)
2638 {
2639 int i;
2640 env->pc = regs->pc;
2641 env->npc = regs->npc;
2642 env->y = regs->y;
2643 for(i = 0; i < 8; i++)
2644 env->gregs[i] = regs->u_regs[i];
2645 for(i = 0; i < 8; i++)
2646 env->regwptr[i] = regs->u_regs[i + 8];
2647 }
2648 #elif defined(TARGET_PPC)
2649 {
2650 int i;
2651
2652 #if defined(TARGET_PPC64)
2653 #if defined(TARGET_ABI32)
2654 env->msr &= ~((target_ulong)1 << MSR_SF);
2655 #else
2656 env->msr |= (target_ulong)1 << MSR_SF;
2657 #endif
2658 #endif
2659 env->nip = regs->nip;
2660 for(i = 0; i < 32; i++) {
2661 env->gpr[i] = regs->gpr[i];
2662 }
2663 }
2664 #elif defined(TARGET_M68K)
2665 {
2666 env->pc = regs->pc;
2667 env->dregs[0] = regs->d0;
2668 env->dregs[1] = regs->d1;
2669 env->dregs[2] = regs->d2;
2670 env->dregs[3] = regs->d3;
2671 env->dregs[4] = regs->d4;
2672 env->dregs[5] = regs->d5;
2673 env->dregs[6] = regs->d6;
2674 env->dregs[7] = regs->d7;
2675 env->aregs[0] = regs->a0;
2676 env->aregs[1] = regs->a1;
2677 env->aregs[2] = regs->a2;
2678 env->aregs[3] = regs->a3;
2679 env->aregs[4] = regs->a4;
2680 env->aregs[5] = regs->a5;
2681 env->aregs[6] = regs->a6;
2682 env->aregs[7] = regs->usp;
2683 env->sr = regs->sr;
2684 ts->sim_syscalls = 1;
2685 }
2686 #elif defined(TARGET_MIPS)
2687 {
2688 int i;
2689
2690 for(i = 0; i < 32; i++) {
2691 env->active_tc.gpr[i] = regs->regs[i];
2692 }
2693 env->active_tc.PC = regs->cp0_epc;
2694 }
2695 #elif defined(TARGET_SH4)
2696 {
2697 int i;
2698
2699 for(i = 0; i < 16; i++) {
2700 env->gregs[i] = regs->regs[i];
2701 }
2702 env->pc = regs->pc;
2703 }
2704 #elif defined(TARGET_HPPA)
2705 {
2706 int i;
2707
2708 for(i = 0; i < 32; i++) {
2709 env->gr[i] = regs->gr[i];
2710 }
2711 env->iaoq[0] = regs->iaoq[0];
2712 env->iaoq[1] = regs->iaoq[1];
2713 env->iasq[0] = regs->iasq[0];
2714 env->iasq[1] = regs->iasq[1];
2715 }
2716 #elif defined(TARGET_ALPHA)
2717 {
2718 int i;
2719
2720 for(i = 0; i < 28; i++) {
2721 env->ir[i] = ((abi_ulong *)regs)[i];
2722 }
2723 env->ipr[IPR_USP] = regs->usp;
2724 env->ir[30] = regs->usp;
2725 env->pc = regs->pc;
2726 env->unique = regs->unique;
2727 }
2728 #elif defined(TARGET_CRIS)
2729 {
2730 env->regs[0] = regs->r0;
2731 env->regs[1] = regs->r1;
2732 env->regs[2] = regs->r2;
2733 env->regs[3] = regs->r3;
2734 env->regs[4] = regs->r4;
2735 env->regs[5] = regs->r5;
2736 env->regs[6] = regs->r6;
2737 env->regs[7] = regs->r7;
2738 env->regs[8] = regs->r8;
2739 env->regs[9] = regs->r9;
2740 env->regs[10] = regs->r10;
2741 env->regs[11] = regs->r11;
2742 env->regs[12] = regs->r12;
2743 env->regs[13] = regs->r13;
2744 env->regs[14] = info->start_stack;
2745 env->regs[15] = regs->acr;
2746 env->pc = regs->erp;
2747 }
2748 #else
2749 #error unsupported target CPU
2750 #endif
2751
2752 #if defined(TARGET_ARM) || defined(TARGET_M68K)
2753 ts->stack_base = info->start_stack;
2754 ts->heap_base = info->brk;
2755 /* This will be filled in on the first SYS_HEAPINFO call. */
2756 ts->heap_limit = 0;
2757 #endif
2758
2759 if (gdbstub_port) {
2760 gdbserver_start (gdbstub_port);
2761 gdb_handlesig(env, 0);
2762 }
2763 cpu_loop(env);
2764 /* never exits */
2765 return 0;
2766 }
HPPA (PA-RISC) target for QEMU