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Merge branch 'master' of git://repo.or.cz/qemu
[qemu/hppa.git] / target-cris / translate.c
blob0d8097a2882e9422b86ce6a7910c0c220572b963
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 * FIXME:
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
26 */
27
28 #include <stdarg.h>
29 #include <stdlib.h>
30 #include <stdio.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <assert.h>
34
35 #include "cpu.h"
36 #include "exec-all.h"
37 #include "disas.h"
38 #include "tcg-op.h"
39 #include "helper.h"
40 #include "crisv32-decode.h"
41 #include "qemu-common.h"
42
43 #define CRIS_STATS 0
44 #if CRIS_STATS
45 #define STATS(x) x
46 #else
47 #define STATS(x)
48 #endif
49
50 #define DISAS_CRIS 0
51 #if DISAS_CRIS
52 #define DIS(x) x
53 #else
54 #define DIS(x)
55 #endif
56
57 #define D(x)
58 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59 #define BUG_ON(x) ({if (x) BUG();})
60
61 #define DISAS_SWI 5
62
63 /* Used by the decoder. */
64 #define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
66
67 #define CC_MASK_NZ 0xc
68 #define CC_MASK_NZV 0xe
69 #define CC_MASK_NZVC 0xf
70 #define CC_MASK_RNZV 0x10e
71
72 TCGv cpu_env;
73 TCGv cpu_T[2];
74 TCGv cpu_R[16];
75 TCGv cpu_PR[16];
76 TCGv cc_src;
77 TCGv cc_dest;
78 TCGv cc_result;
79 TCGv cc_op;
80 TCGv cc_size;
81 TCGv cc_mask;
82
83 TCGv env_btarget;
84 TCGv env_pc;
85
86 /* This is the state at translation time. */
87 typedef struct DisasContext {
88 CPUState *env;
89 target_ulong pc, ppc;
90
91 /* Decoder. */
92 uint32_t ir;
93 uint32_t opcode;
94 unsigned int op1;
95 unsigned int op2;
96 unsigned int zsize, zzsize;
97 unsigned int mode;
98 unsigned int postinc;
99
100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
106 translation time. */
107 int flags_x;
108 int clear_x; /* Clear x after this insn? */
109
110 int user; /* user or kernel mode. */
111 int is_jmp;
112 int dyn_jmp;
113
114 uint32_t delayed_pc;
115 int delayed_branch;
116 int bcc;
117 uint32_t condlabel;
118
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
121 } DisasContext;
122
123 void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124 static void gen_BUG(DisasContext *dc, char *file, int line)
125 {
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
129 fflush(NULL);
130 cris_prepare_jmp (dc, 0x70000000 + line);
131 }
132
133 const char *regnames[] =
134 {
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
139 };
140 const char *pregnames[] =
141 {
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
146 };
147
148 /* We need this table to handle preg-moves with implicit width. */
149 int preg_sizes[] = {
150 1, /* bz. */
151 1, /* vr. */
152 4, /* pid. */
153 1, /* srs. */
154 2, /* wz. */
155 4, 4, 4,
156 4, 4, 4, 4,
157 4, 4, 4, 4,
158 };
159
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
164
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
166 {
167 if (r < 0 || r > 15)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
170 }
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
172 {
173 if (r < 0 || r > 15)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
176 }
177
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
179 {
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
183 }
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
185 {
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
189 }
190
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
192 {
193 if (r < 0 || r > 15)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
197 else if (r == PR_VR)
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
202 }
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 }
207 else
208 tcg_gen_mov_tl(tn, cpu_PR[r]);
209 }
210 static inline void t_gen_mov_preg_TN(int r, TCGv tn)
211 {
212 if (r < 0 || r > 15)
213 fprintf(stderr, "wrong register write $p%d\n", r);
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
215 return;
216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 else {
219 if (r == PR_PID) {
220 tcg_gen_helper_0_0(helper_tlb_flush);
221 }
222 tcg_gen_mov_tl(cpu_PR[r], tn);
223 }
224 }
225
226 static inline void t_gen_raise_exception(uint32_t index)
227 {
228 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
229 }
230
231 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
232 {
233 int l1;
234
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
241 gen_set_label(l1);
242 }
243
244 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
245 {
246 int l1;
247
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
251 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
254 gen_set_label(l1);
255 }
256
257 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
258 {
259 int l1;
260
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
264 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
265 /* Clear dst if shift operands were to large. */
266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
267 gen_set_label(l1);
268 }
269
270 /* 64-bit signed mul, lower result in d and upper in d2. */
271 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
272 {
273 TCGv t0, t1;
274
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
277
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
281
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
285
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
288 }
289
290 /* 64-bit unsigned muls, lower result in d and upper in d2. */
291 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
292 {
293 TCGv t0, t1;
294
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
297
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
301
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
305
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
308 }
309
310 /* 32bit branch-free binary search for counting leading zeros. */
311 static void t_gen_lz_i32(TCGv d, TCGv x)
312 {
313 TCGv y, m, n;
314
315 y = tcg_temp_new(TCG_TYPE_I32);
316 m = tcg_temp_new(TCG_TYPE_I32);
317 n = tcg_temp_new(TCG_TYPE_I32);
318
319 /* y = -(x >> 16) */
320 tcg_gen_shri_i32(y, x, 16);
321 tcg_gen_sub_i32(y, tcg_const_i32(0), y);
322
323 /* m = (y >> 16) & 16 */
324 tcg_gen_sari_i32(m, y, 16);
325 tcg_gen_andi_i32(m, m, 16);
326
327 /* n = 16 - m */
328 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
329 /* x = x >> m */
330 tcg_gen_shr_i32(x, x, m);
331
332 /* y = x - 0x100 */
333 tcg_gen_subi_i32(y, x, 0x100);
334 /* m = (y >> 16) & 8 */
335 tcg_gen_sari_i32(m, y, 16);
336 tcg_gen_andi_i32(m, m, 8);
337 /* n = n + m */
338 tcg_gen_add_i32(n, n, m);
339 /* x = x << m */
340 tcg_gen_shl_i32(x, x, m);
341
342 /* y = x - 0x1000 */
343 tcg_gen_subi_i32(y, x, 0x1000);
344 /* m = (y >> 16) & 4 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 4);
347 /* n = n + m */
348 tcg_gen_add_i32(n, n, m);
349 /* x = x << m */
350 tcg_gen_shl_i32(x, x, m);
351
352 /* y = x - 0x4000 */
353 tcg_gen_subi_i32(y, x, 0x4000);
354 /* m = (y >> 16) & 2 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 2);
357 /* n = n + m */
358 tcg_gen_add_i32(n, n, m);
359 /* x = x << m */
360 tcg_gen_shl_i32(x, x, m);
361
362 /* y = x >> 14 */
363 tcg_gen_shri_i32(y, x, 14);
364 /* m = y & ~(y >> 1) */
365 tcg_gen_sari_i32(m, y, 1);
366 tcg_gen_xori_i32(m, m, 0xffffffff);
367 tcg_gen_and_i32(m, m, y);
368
369 /* d = n + 2 - m */
370 tcg_gen_addi_i32(d, n, 2);
371 tcg_gen_sub_i32(d, d, m);
372
373 tcg_gen_discard_i32(y);
374 tcg_gen_discard_i32(m);
375 tcg_gen_discard_i32(n);
376 }
377
378 static void t_gen_btst(TCGv d, TCGv s)
379 {
380 TCGv sbit;
381 TCGv bset;
382 int l1;
383
384 /* des ref:
385 The N flag is set according to the selected bit in the dest reg.
386 The Z flag is set if the selected bit and all bits to the right are
387 zero.
388 The X flag is cleared.
389 Other flags are left untouched.
390 The destination reg is not affected.
391
392 unsigned int fz, sbit, bset, mask, masked_t0;
393
394 sbit = T1 & 31;
395 bset = !!(T0 & (1 << sbit));
396 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
397 masked_t0 = T0 & mask;
398 fz = !(masked_t0 | bset);
399
400 // Clear the X, N and Z flags.
401 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
402 // Set the N and Z flags accordingly.
403 T0 |= (bset << 3) | (fz << 2);
404 */
405
406 l1 = gen_new_label();
407 sbit = tcg_temp_new(TCG_TYPE_TL);
408 bset = tcg_temp_new(TCG_TYPE_TL);
409
410 /* Compute bset and sbit. */
411 tcg_gen_andi_tl(sbit, s, 31);
412 tcg_gen_shl_tl(s, tcg_const_tl(1), sbit);
413 tcg_gen_and_tl(bset, d, s);
414 tcg_gen_shr_tl(bset, bset, sbit);
415 /* Displace to N_FLAG. */
416 tcg_gen_shli_tl(bset, bset, 3);
417
418 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
419 tcg_gen_subi_tl(sbit, sbit, 1);
420 tcg_gen_and_tl(sbit, d, sbit);
421
422 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
423 /* or in the N_FLAG. */
424 tcg_gen_or_tl(d, d, bset);
425 tcg_gen_brcond_tl(TCG_COND_NE, sbit, tcg_const_tl(0), l1);
426 /* or in the Z_FLAG. */
427 tcg_gen_ori_tl(d, d, Z_FLAG);
428 gen_set_label(l1);
429
430 tcg_gen_discard_tl(sbit);
431 tcg_gen_discard_tl(bset);
432 }
433
434 static void t_gen_cris_dstep(TCGv d, TCGv s)
435 {
436 int l1;
437
438 l1 = gen_new_label();
439
440 /*
441 * d <<= 1
442 * if (d >= s)
443 * d -= s;
444 */
445 tcg_gen_shli_tl(d, d, 1);
446 tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
447 tcg_gen_sub_tl(d, d, s);
448 gen_set_label(l1);
449 }
450
451 /* Extended arithmetics on CRIS. */
452 static inline void t_gen_add_flag(TCGv d, int flag)
453 {
454 TCGv c;
455
456 c = tcg_temp_new(TCG_TYPE_TL);
457 t_gen_mov_TN_preg(c, PR_CCS);
458 /* Propagate carry into d. */
459 tcg_gen_andi_tl(c, c, 1 << flag);
460 if (flag)
461 tcg_gen_shri_tl(c, c, flag);
462 tcg_gen_add_tl(d, d, c);
463 tcg_gen_discard_tl(c);
464 }
465
466 static inline void t_gen_addx_carry(TCGv d)
467 {
468 TCGv x, c;
469
470 x = tcg_temp_new(TCG_TYPE_TL);
471 c = tcg_temp_new(TCG_TYPE_TL);
472 t_gen_mov_TN_preg(x, PR_CCS);
473 tcg_gen_mov_tl(c, x);
474
475 /* Propagate carry into d if X is set. Branch free. */
476 tcg_gen_andi_tl(c, c, C_FLAG);
477 tcg_gen_andi_tl(x, x, X_FLAG);
478 tcg_gen_shri_tl(x, x, 4);
479
480 tcg_gen_and_tl(x, x, c);
481 tcg_gen_add_tl(d, d, x);
482 tcg_gen_discard_tl(x);
483 tcg_gen_discard_tl(c);
484 }
485
486 static inline void t_gen_subx_carry(TCGv d)
487 {
488 TCGv x, c;
489
490 x = tcg_temp_new(TCG_TYPE_TL);
491 c = tcg_temp_new(TCG_TYPE_TL);
492 t_gen_mov_TN_preg(x, PR_CCS);
493 tcg_gen_mov_tl(c, x);
494
495 /* Propagate carry into d if X is set. Branch free. */
496 tcg_gen_andi_tl(c, c, C_FLAG);
497 tcg_gen_andi_tl(x, x, X_FLAG);
498 tcg_gen_shri_tl(x, x, 4);
499
500 tcg_gen_and_tl(x, x, c);
501 tcg_gen_sub_tl(d, d, x);
502 tcg_gen_discard_tl(x);
503 tcg_gen_discard_tl(c);
504 }
505
506 /* Swap the two bytes within each half word of the s operand.
507 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
508 static inline void t_gen_swapb(TCGv d, TCGv s)
509 {
510 TCGv t, org_s;
511
512 t = tcg_temp_new(TCG_TYPE_TL);
513 org_s = tcg_temp_new(TCG_TYPE_TL);
514
515 /* d and s may refer to the same object. */
516 tcg_gen_mov_tl(org_s, s);
517 tcg_gen_shli_tl(t, org_s, 8);
518 tcg_gen_andi_tl(d, t, 0xff00ff00);
519 tcg_gen_shri_tl(t, org_s, 8);
520 tcg_gen_andi_tl(t, t, 0x00ff00ff);
521 tcg_gen_or_tl(d, d, t);
522 tcg_gen_discard_tl(t);
523 tcg_gen_discard_tl(org_s);
524 }
525
526 /* Swap the halfwords of the s operand. */
527 static inline void t_gen_swapw(TCGv d, TCGv s)
528 {
529 TCGv t;
530 /* d and s refer the same object. */
531 t = tcg_temp_new(TCG_TYPE_TL);
532 tcg_gen_mov_tl(t, s);
533 tcg_gen_shli_tl(d, t, 16);
534 tcg_gen_shri_tl(t, t, 16);
535 tcg_gen_or_tl(d, d, t);
536 tcg_gen_discard_tl(t);
537 }
538
539 /* Reverse the within each byte.
540 T0 = (((T0 << 7) & 0x80808080) |
541 ((T0 << 5) & 0x40404040) |
542 ((T0 << 3) & 0x20202020) |
543 ((T0 << 1) & 0x10101010) |
544 ((T0 >> 1) & 0x08080808) |
545 ((T0 >> 3) & 0x04040404) |
546 ((T0 >> 5) & 0x02020202) |
547 ((T0 >> 7) & 0x01010101));
548 */
549 static inline void t_gen_swapr(TCGv d, TCGv s)
550 {
551 struct {
552 int shift; /* LSL when positive, LSR when negative. */
553 uint32_t mask;
554 } bitrev [] = {
555 {7, 0x80808080},
556 {5, 0x40404040},
557 {3, 0x20202020},
558 {1, 0x10101010},
559 {-1, 0x08080808},
560 {-3, 0x04040404},
561 {-5, 0x02020202},
562 {-7, 0x01010101}
563 };
564 int i;
565 TCGv t, org_s;
566
567 /* d and s refer the same object. */
568 t = tcg_temp_new(TCG_TYPE_TL);
569 org_s = tcg_temp_new(TCG_TYPE_TL);
570 tcg_gen_mov_tl(org_s, s);
571
572 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
573 tcg_gen_andi_tl(d, t, bitrev[0].mask);
574 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
575 if (bitrev[i].shift >= 0) {
576 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
577 } else {
578 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
579 }
580 tcg_gen_andi_tl(t, t, bitrev[i].mask);
581 tcg_gen_or_tl(d, d, t);
582 }
583 tcg_gen_discard_tl(t);
584 tcg_gen_discard_tl(org_s);
585 }
586
587 static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
588 {
589 TCGv btaken;
590 int l1;
591
592 l1 = gen_new_label();
593 btaken = tcg_temp_new(TCG_TYPE_TL);
594
595 /* Conditional jmp. */
596 t_gen_mov_TN_env(btaken, btaken);
597 tcg_gen_movi_tl(env_pc, pc_false);
598 tcg_gen_brcond_tl(TCG_COND_EQ, btaken, tcg_const_tl(0), l1);
599 tcg_gen_movi_tl(env_pc, pc_true);
600 gen_set_label(l1);
601
602 tcg_gen_discard_tl(btaken);
603 }
604
605 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
606 {
607 TranslationBlock *tb;
608 tb = dc->tb;
609 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
610 tcg_gen_goto_tb(n);
611 tcg_gen_movi_tl(env_pc, dest);
612 tcg_gen_exit_tb((long)tb + n);
613 } else {
614 tcg_gen_mov_tl(env_pc, cpu_T[0]);
615 tcg_gen_exit_tb(0);
616 }
617 }
618
619 /* Sign extend at translation time. */
620 static int sign_extend(unsigned int val, unsigned int width)
621 {
622 int sval;
623
624 /* LSL. */
625 val <<= 31 - width;
626 sval = val;
627 /* ASR. */
628 sval >>= 31 - width;
629 return sval;
630 }
631
632 static inline void cris_clear_x_flag(DisasContext *dc)
633 {
634 if (!dc->flagx_live
635 || (dc->flagx_live && dc->flags_x)
636 || dc->cc_op != CC_OP_FLAGS)
637 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
638 dc->flagx_live = 1;
639 dc->flags_x = 0;
640 }
641
642 static void cris_evaluate_flags(DisasContext *dc)
643 {
644 if (!dc->flags_live) {
645 tcg_gen_movi_tl(cc_op, dc->cc_op);
646 tcg_gen_movi_tl(cc_size, dc->cc_size);
647 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
648
649 switch (dc->cc_op)
650 {
651 case CC_OP_MCP:
652 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
653 break;
654 case CC_OP_MULS:
655 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
656 break;
657 case CC_OP_MULU:
658 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
659 break;
660 case CC_OP_MOVE:
661 switch (dc->cc_size)
662 {
663 case 4:
664 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
665 break;
666 case 2:
667 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
668 break;
669 default:
670 tcg_gen_helper_0_0(helper_evaluate_flags);
671 break;
672 }
673 break;
674 case CC_OP_FLAGS:
675 /* live. */
676 break;
677 default:
678 {
679 switch (dc->cc_size)
680 {
681 case 4:
682 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
683 break;
684 default:
685 tcg_gen_helper_0_0(helper_evaluate_flags);
686 break;
687 }
688 }
689 break;
690 }
691 dc->flags_live = 1;
692 }
693 }
694
695 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
696 {
697 uint32_t ovl;
698
699 /* Check if we need to evaluate the condition codes due to
700 CC overlaying. */
701 ovl = (dc->cc_mask ^ mask) & ~mask;
702 if (ovl) {
703 /* TODO: optimize this case. It trigs all the time. */
704 cris_evaluate_flags (dc);
705 }
706 dc->cc_mask = mask;
707 dc->update_cc = 1;
708
709 if (mask == 0)
710 dc->update_cc = 0;
711 else
712 dc->flags_live = 0;
713 }
714
715 static void cris_update_cc_op(DisasContext *dc, int op, int size)
716 {
717 dc->cc_op = op;
718 dc->cc_size = size;
719 dc->flags_live = 0;
720 }
721
722 /* op is the operation.
723 T0, T1 are the operands.
724 dst is the destination reg.
725 */
726 static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
727 {
728 int writeback = 1;
729 if (dc->update_cc) {
730 cris_update_cc_op(dc, op, size);
731 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
732
733 /* FIXME: This shouldn't be needed. But we don't pass the
734 tests without it. Investigate. */
735 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
736 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
737 }
738
739 /* Emit the ALU insns. */
740 switch (op)
741 {
742 case CC_OP_ADD:
743 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
744 /* Extended arithmetics. */
745 t_gen_addx_carry(cpu_T[0]);
746 break;
747 case CC_OP_ADDC:
748 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
749 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
750 break;
751 case CC_OP_MCP:
752 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
753 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
754 break;
755 case CC_OP_SUB:
756 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
757 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
758 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
759 /* CRIS flag evaluation needs ~src. */
760 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
761
762 /* Extended arithmetics. */
763 t_gen_subx_carry(cpu_T[0]);
764 break;
765 case CC_OP_MOVE:
766 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
767 break;
768 case CC_OP_OR:
769 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
770 break;
771 case CC_OP_AND:
772 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
773 break;
774 case CC_OP_XOR:
775 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
776 break;
777 case CC_OP_LSL:
778 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
779 break;
780 case CC_OP_LSR:
781 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
782 break;
783 case CC_OP_ASR:
784 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
785 break;
786 case CC_OP_NEG:
787 /* Hopefully the TCG backend recognizes this pattern
788 and makes a real neg out of it. */
789 tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
790 /* Extended arithmetics. */
791 t_gen_subx_carry(cpu_T[0]);
792 break;
793 case CC_OP_LZ:
794 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
795 break;
796 case CC_OP_BTST:
797 t_gen_btst(cpu_T[0], cpu_T[1]);
798 writeback = 0;
799 break;
800 case CC_OP_MULS:
801 {
802 TCGv mof;
803 mof = tcg_temp_new(TCG_TYPE_TL);
804 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
805 t_gen_mov_preg_TN(PR_MOF, mof);
806 tcg_gen_discard_tl(mof);
807 }
808 break;
809 case CC_OP_MULU:
810 {
811 TCGv mof;
812 mof = tcg_temp_new(TCG_TYPE_TL);
813 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
814 t_gen_mov_preg_TN(PR_MOF, mof);
815 tcg_gen_discard_tl(mof);
816 }
817 break;
818 case CC_OP_DSTEP:
819 t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
820 break;
821 case CC_OP_BOUND:
822 {
823 int l1;
824 l1 = gen_new_label();
825 tcg_gen_brcond_tl(TCG_COND_LEU,
826 cpu_T[0], cpu_T[1], l1);
827 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
828 gen_set_label(l1);
829 }
830 break;
831 case CC_OP_CMP:
832 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
833 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
834 /* CRIS flag evaluation needs ~src. */
835 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
836 /* CRIS flag evaluation needs ~src. */
837 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
838
839 /* Extended arithmetics. */
840 t_gen_subx_carry(cpu_T[0]);
841 writeback = 0;
842 break;
843 default:
844 fprintf (logfile, "illegal ALU op.\n");
845 BUG();
846 break;
847 }
848
849 if (dc->update_cc)
850 tcg_gen_mov_tl(cc_src, cpu_T[1]);
851
852 if (size == 1)
853 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
854 else if (size == 2)
855 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
856
857 /* Writeback. */
858 if (writeback) {
859 if (size == 4)
860 t_gen_mov_reg_TN(rd, cpu_T[0]);
861 else {
862 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
863 t_gen_mov_TN_reg(cpu_T[0], rd);
864 if (size == 1)
865 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
866 else
867 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
868 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
869 t_gen_mov_reg_TN(rd, cpu_T[0]);
870 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
871 }
872 }
873 if (dc->update_cc)
874 tcg_gen_mov_tl(cc_result, cpu_T[0]);
875
876 {
877 /* TODO: Optimize this. */
878 if (!dc->flagx_live)
879 cris_evaluate_flags(dc);
880 }
881 }
882
883 static int arith_cc(DisasContext *dc)
884 {
885 if (dc->update_cc) {
886 switch (dc->cc_op) {
887 case CC_OP_ADD: return 1;
888 case CC_OP_SUB: return 1;
889 case CC_OP_LSL: return 1;
890 case CC_OP_LSR: return 1;
891 case CC_OP_ASR: return 1;
892 case CC_OP_CMP: return 1;
893 default:
894 return 0;
895 }
896 }
897 return 0;
898 }
899
900 static void gen_tst_cc (DisasContext *dc, int cond)
901 {
902 int arith_opt;
903
904 /* TODO: optimize more condition codes. */
905
906 /*
907 * If the flags are live, we've gotta look into the bits of CCS.
908 * Otherwise, if we just did an arithmetic operation we try to
909 * evaluate the condition code faster.
910 *
911 * When this function is done, T0 should be non-zero if the condition
912 * code is true.
913 */
914 arith_opt = arith_cc(dc) && !dc->flags_live;
915 switch (cond) {
916 case CC_EQ:
917 if (arith_opt) {
918 /* If cc_result is zero, T0 should be
919 non-zero otherwise T0 should be zero. */
920 int l1;
921 l1 = gen_new_label();
922 tcg_gen_movi_tl(cpu_T[0], 0);
923 tcg_gen_brcond_tl(TCG_COND_NE, cc_result,
924 tcg_const_tl(0), l1);
925 tcg_gen_movi_tl(cpu_T[0], 1);
926 gen_set_label(l1);
927 }
928 else {
929 cris_evaluate_flags(dc);
930 tcg_gen_andi_tl(cpu_T[0],
931 cpu_PR[PR_CCS], Z_FLAG);
932 }
933 break;
934 case CC_NE:
935 if (arith_opt)
936 tcg_gen_mov_tl(cpu_T[0], cc_result);
937 else {
938 cris_evaluate_flags(dc);
939 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
940 Z_FLAG);
941 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
942 }
943 break;
944 case CC_CS:
945 cris_evaluate_flags(dc);
946 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
947 break;
948 case CC_CC:
949 cris_evaluate_flags(dc);
950 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
951 C_FLAG);
952 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
953 break;
954 case CC_VS:
955 cris_evaluate_flags(dc);
956 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
957 break;
958 case CC_VC:
959 cris_evaluate_flags(dc);
960 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
961 V_FLAG);
962 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
963 break;
964 case CC_PL:
965 if (arith_opt)
966 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
967 else {
968 cris_evaluate_flags(dc);
969 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
970 N_FLAG);
971 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
972 }
973 break;
974 case CC_MI:
975 if (arith_opt) {
976 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
977 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
978 }
979 else {
980 cris_evaluate_flags(dc);
981 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
982 N_FLAG);
983 }
984 break;
985 case CC_LS:
986 cris_evaluate_flags(dc);
987 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
988 C_FLAG | Z_FLAG);
989 break;
990 case CC_HI:
991 cris_evaluate_flags(dc);
992 {
993 TCGv tmp;
994
995 tmp = tcg_temp_new(TCG_TYPE_TL);
996 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
997 C_FLAG | Z_FLAG);
998 /* Overlay the C flag on top of the Z. */
999 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
1000 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
1001 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1002
1003 tcg_gen_discard_tl(tmp);
1004 }
1005 break;
1006 case CC_GE:
1007 cris_evaluate_flags(dc);
1008 /* Overlay the V flag on top of the N. */
1009 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1010 tcg_gen_xor_tl(cpu_T[0],
1011 cpu_PR[PR_CCS], cpu_T[0]);
1012 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1013 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
1014 break;
1015 case CC_LT:
1016 cris_evaluate_flags(dc);
1017 /* Overlay the V flag on top of the N. */
1018 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1019 tcg_gen_xor_tl(cpu_T[0],
1020 cpu_PR[PR_CCS], cpu_T[0]);
1021 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1022 break;
1023 case CC_GT:
1024 cris_evaluate_flags(dc);
1025 {
1026 TCGv n, z;
1027
1028 n = tcg_temp_new(TCG_TYPE_TL);
1029 z = tcg_temp_new(TCG_TYPE_TL);
1030
1031 /* To avoid a shift we overlay everything on
1032 the V flag. */
1033 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1034 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1035 /* invert Z. */
1036 tcg_gen_xori_tl(z, z, 2);
1037
1038 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1039 tcg_gen_xori_tl(n, n, 2);
1040 tcg_gen_and_tl(cpu_T[0], z, n);
1041 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1042
1043 tcg_gen_discard_tl(n);
1044 tcg_gen_discard_tl(z);
1045 }
1046 break;
1047 case CC_LE:
1048 cris_evaluate_flags(dc);
1049 {
1050 TCGv n, z;
1051
1052 n = tcg_temp_new(TCG_TYPE_TL);
1053 z = tcg_temp_new(TCG_TYPE_TL);
1054
1055 /* To avoid a shift we overlay everything on
1056 the V flag. */
1057 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1058 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1059
1060 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1061 tcg_gen_or_tl(cpu_T[0], z, n);
1062 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1063
1064 tcg_gen_discard_tl(n);
1065 tcg_gen_discard_tl(z);
1066 }
1067 break;
1068 case CC_P:
1069 cris_evaluate_flags(dc);
1070 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
1071 break;
1072 case CC_A:
1073 cris_evaluate_flags(dc);
1074 tcg_gen_movi_tl(cpu_T[0], 1);
1075 break;
1076 default:
1077 BUG();
1078 break;
1079 };
1080 }
1081
1082 static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
1083 {
1084 /* This helps us re-schedule the micro-code to insns in delay-slots
1085 before the actual jump. */
1086 dc->delayed_branch = 2;
1087 dc->delayed_pc = dc->pc + offset;
1088 dc->bcc = cond;
1089 if (cond != CC_A)
1090 {
1091 gen_tst_cc (dc, cond);
1092 t_gen_mov_env_TN(btaken, cpu_T[0]);
1093 }
1094 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
1095 }
1096
1097
1098 /* Dynamic jumps, when the dest is in a live reg for example. */
1099 void cris_prepare_dyn_jmp (DisasContext *dc)
1100 {
1101 /* This helps us re-schedule the micro-code to insns in delay-slots
1102 before the actual jump. */
1103 dc->delayed_branch = 2;
1104 dc->dyn_jmp = 1;
1105 dc->bcc = CC_A;
1106 }
1107
1108 void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
1109 {
1110 /* This helps us re-schedule the micro-code to insns in delay-slots
1111 before the actual jump. */
1112 dc->delayed_branch = 2;
1113 dc->delayed_pc = dst;
1114 dc->dyn_jmp = 0;
1115 dc->bcc = CC_A;
1116 }
1117
1118 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1119 unsigned int size, int sign)
1120 {
1121 int mem_index = cpu_mmu_index(dc->env);
1122
1123 cris_evaluate_flags(dc);
1124 if (size == 1) {
1125 if (sign)
1126 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1127 else
1128 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1129 }
1130 else if (size == 2) {
1131 if (sign)
1132 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1133 else
1134 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1135 }
1136 else {
1137 tcg_gen_qemu_ld32s(dst, addr, mem_index);
1138 }
1139 }
1140
1141 void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1142 unsigned int size)
1143 {
1144 int mem_index = cpu_mmu_index(dc->env);
1145
1146 cris_evaluate_flags(dc);
1147
1148 /* Remember, operands are flipped. CRIS has reversed order. */
1149 if (size == 1)
1150 tcg_gen_qemu_st8(val, addr, mem_index);
1151 else if (size == 2)
1152 tcg_gen_qemu_st16(val, addr, mem_index);
1153 else
1154 tcg_gen_qemu_st32(val, addr, mem_index);
1155 }
1156
1157 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1158 {
1159 if (size == 1)
1160 tcg_gen_ext8s_i32(d, s);
1161 else if (size == 2)
1162 tcg_gen_ext16s_i32(d, s);
1163 else
1164 tcg_gen_mov_tl(d, s);
1165 }
1166
1167 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1168 {
1169 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
1170 if (size == 1)
1171 tcg_gen_andi_i32(d, s, 0xff);
1172 else if (size == 2)
1173 tcg_gen_andi_i32(d, s, 0xffff);
1174 else
1175 tcg_gen_mov_tl(d, s);
1176 }
1177
1178 #if DISAS_CRIS
1179 static char memsize_char(int size)
1180 {
1181 switch (size)
1182 {
1183 case 1: return 'b'; break;
1184 case 2: return 'w'; break;
1185 case 4: return 'd'; break;
1186 default:
1187 return 'x';
1188 break;
1189 }
1190 }
1191 #endif
1192
1193 static unsigned int memsize_z(DisasContext *dc)
1194 {
1195 return dc->zsize + 1;
1196 }
1197
1198 static unsigned int memsize_zz(DisasContext *dc)
1199 {
1200 switch (dc->zzsize)
1201 {
1202 case 0: return 1;
1203 case 1: return 2;
1204 default:
1205 return 4;
1206 }
1207 }
1208
1209 static inline void do_postinc (DisasContext *dc, int size)
1210 {
1211 if (dc->postinc)
1212 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1213 }
1214
1215
1216 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1217 int size, int s_ext)
1218 {
1219 if (s_ext)
1220 t_gen_sext(cpu_T[1], cpu_R[rs], size);
1221 else
1222 t_gen_zext(cpu_T[1], cpu_R[rs], size);
1223 }
1224
1225 /* Prepare T0 and T1 for a register alu operation.
1226 s_ext decides if the operand1 should be sign-extended or zero-extended when
1227 needed. */
1228 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1229 int size, int s_ext)
1230 {
1231 dec_prep_move_r(dc, rs, rd, size, s_ext);
1232
1233 if (s_ext)
1234 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1235 else
1236 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1237 }
1238
1239 /* Prepare T0 and T1 for a memory + alu operation.
1240 s_ext decides if the operand1 should be sign-extended or zero-extended when
1241 needed. */
1242 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1243 {
1244 unsigned int rs, rd;
1245 uint32_t imm;
1246 int is_imm;
1247 int insn_len = 2;
1248
1249 rs = dc->op1;
1250 rd = dc->op2;
1251 is_imm = rs == 15 && dc->postinc;
1252
1253 /* Load [$rs] onto T1. */
1254 if (is_imm) {
1255 insn_len = 2 + memsize;
1256 if (memsize == 1)
1257 insn_len++;
1258
1259 if (memsize != 4) {
1260 if (s_ext) {
1261 if (memsize == 1)
1262 imm = ldsb_code(dc->pc + 2);
1263 else
1264 imm = ldsw_code(dc->pc + 2);
1265 } else {
1266 if (memsize == 1)
1267 imm = ldub_code(dc->pc + 2);
1268 else
1269 imm = lduw_code(dc->pc + 2);
1270 }
1271 } else
1272 imm = ldl_code(dc->pc + 2);
1273
1274 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1275 imm, rd, s_ext, memsize));
1276 tcg_gen_movi_tl(cpu_T[1], imm);
1277 dc->postinc = 0;
1278 } else {
1279 /* FIXME: qemu_ld does not act as a barrier? */
1280 tcg_gen_helper_0_0(helper_dummy);
1281 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
1282 if (s_ext)
1283 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
1284 else
1285 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
1286 }
1287
1288 /* put dest in T0. */
1289 t_gen_mov_TN_reg(cpu_T[0], rd);
1290 return insn_len;
1291 }
1292
1293 #if DISAS_CRIS
1294 static const char *cc_name(int cc)
1295 {
1296 static char *cc_names[16] = {
1297 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1298 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1299 };
1300 assert(cc < 16);
1301 return cc_names[cc];
1302 }
1303 #endif
1304
1305 /* Start of insn decoders. */
1306
1307 static unsigned int dec_bccq(DisasContext *dc)
1308 {
1309 int32_t offset;
1310 int sign;
1311 uint32_t cond = dc->op2;
1312 int tmp;
1313
1314 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1315 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1316
1317 offset *= 2;
1318 offset |= sign << 8;
1319 tmp = offset;
1320 offset = sign_extend(offset, 8);
1321
1322 /* op2 holds the condition-code. */
1323 cris_cc_mask(dc, 0);
1324 cris_prepare_cc_branch (dc, offset, cond);
1325 return 2;
1326 }
1327 static unsigned int dec_addoq(DisasContext *dc)
1328 {
1329 int32_t imm;
1330
1331 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1332 imm = sign_extend(dc->op1, 7);
1333
1334 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1335 cris_cc_mask(dc, 0);
1336 /* Fetch register operand, */
1337 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1338 return 2;
1339 }
1340 static unsigned int dec_addq(DisasContext *dc)
1341 {
1342 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1343
1344 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1345
1346 cris_cc_mask(dc, CC_MASK_NZVC);
1347 /* Fetch register operand, */
1348 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1349 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1350 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1351 return 2;
1352 }
1353 static unsigned int dec_moveq(DisasContext *dc)
1354 {
1355 uint32_t imm;
1356
1357 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1358 imm = sign_extend(dc->op1, 5);
1359 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1360
1361 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
1362 return 2;
1363 }
1364 static unsigned int dec_subq(DisasContext *dc)
1365 {
1366 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1367
1368 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1369
1370 cris_cc_mask(dc, CC_MASK_NZVC);
1371 /* Fetch register operand, */
1372 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1373 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1374 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1375 return 2;
1376 }
1377 static unsigned int dec_cmpq(DisasContext *dc)
1378 {
1379 uint32_t imm;
1380 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1381 imm = sign_extend(dc->op1, 5);
1382
1383 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1384 cris_cc_mask(dc, CC_MASK_NZVC);
1385 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1386 tcg_gen_movi_tl(cpu_T[1], imm);
1387 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1388 return 2;
1389 }
1390 static unsigned int dec_andq(DisasContext *dc)
1391 {
1392 uint32_t imm;
1393 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1394 imm = sign_extend(dc->op1, 5);
1395
1396 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1397 cris_cc_mask(dc, CC_MASK_NZ);
1398 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1399 tcg_gen_movi_tl(cpu_T[1], imm);
1400 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1401 return 2;
1402 }
1403 static unsigned int dec_orq(DisasContext *dc)
1404 {
1405 uint32_t imm;
1406 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1407 imm = sign_extend(dc->op1, 5);
1408 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1409 cris_cc_mask(dc, CC_MASK_NZ);
1410 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1411 tcg_gen_movi_tl(cpu_T[1], imm);
1412 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1413 return 2;
1414 }
1415 static unsigned int dec_btstq(DisasContext *dc)
1416 {
1417 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1418 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1419
1420 cris_cc_mask(dc, CC_MASK_NZ);
1421 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1422 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1423 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1424
1425 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1426 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1427 dc->flags_live = 1;
1428 return 2;
1429 }
1430 static unsigned int dec_asrq(DisasContext *dc)
1431 {
1432 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1433 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1434 cris_cc_mask(dc, CC_MASK_NZ);
1435 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1436 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1437 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1438 return 2;
1439 }
1440 static unsigned int dec_lslq(DisasContext *dc)
1441 {
1442 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1443 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1444
1445 cris_cc_mask(dc, CC_MASK_NZ);
1446 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1447 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1448 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1449 return 2;
1450 }
1451 static unsigned int dec_lsrq(DisasContext *dc)
1452 {
1453 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1454 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1455
1456 cris_cc_mask(dc, CC_MASK_NZ);
1457 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1458 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1459 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1460 return 2;
1461 }
1462
1463 static unsigned int dec_move_r(DisasContext *dc)
1464 {
1465 int size = memsize_zz(dc);
1466
1467 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1468 memsize_char(size), dc->op1, dc->op2));
1469
1470 cris_cc_mask(dc, CC_MASK_NZ);
1471 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1472 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1473 return 2;
1474 }
1475
1476 static unsigned int dec_scc_r(DisasContext *dc)
1477 {
1478 int cond = dc->op2;
1479
1480 DIS(fprintf (logfile, "s%s $r%u\n",
1481 cc_name(cond), dc->op1));
1482
1483 if (cond != CC_A)
1484 {
1485 int l1;
1486
1487 gen_tst_cc (dc, cond);
1488
1489 l1 = gen_new_label();
1490 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1491 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
1492 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1493 gen_set_label(l1);
1494 }
1495 else
1496 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1497
1498 cris_cc_mask(dc, 0);
1499 return 2;
1500 }
1501
1502 static unsigned int dec_and_r(DisasContext *dc)
1503 {
1504 int size = memsize_zz(dc);
1505
1506 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1507 memsize_char(size), dc->op1, dc->op2));
1508 cris_cc_mask(dc, CC_MASK_NZ);
1509 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1510 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1511 return 2;
1512 }
1513
1514 static unsigned int dec_lz_r(DisasContext *dc)
1515 {
1516 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1517 dc->op1, dc->op2));
1518 cris_cc_mask(dc, CC_MASK_NZ);
1519 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1520 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1521 return 2;
1522 }
1523
1524 static unsigned int dec_lsl_r(DisasContext *dc)
1525 {
1526 int size = memsize_zz(dc);
1527
1528 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1529 memsize_char(size), dc->op1, dc->op2));
1530 cris_cc_mask(dc, CC_MASK_NZ);
1531 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1532 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1533 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1534 return 2;
1535 }
1536
1537 static unsigned int dec_lsr_r(DisasContext *dc)
1538 {
1539 int size = memsize_zz(dc);
1540
1541 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1542 memsize_char(size), dc->op1, dc->op2));
1543 cris_cc_mask(dc, CC_MASK_NZ);
1544 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1545 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1546 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1547 return 2;
1548 }
1549
1550 static unsigned int dec_asr_r(DisasContext *dc)
1551 {
1552 int size = memsize_zz(dc);
1553
1554 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1555 memsize_char(size), dc->op1, dc->op2));
1556 cris_cc_mask(dc, CC_MASK_NZ);
1557 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1558 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1559 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1560 return 2;
1561 }
1562
1563 static unsigned int dec_muls_r(DisasContext *dc)
1564 {
1565 int size = memsize_zz(dc);
1566
1567 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1568 memsize_char(size), dc->op1, dc->op2));
1569 cris_cc_mask(dc, CC_MASK_NZV);
1570 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1571 t_gen_sext(cpu_T[0], cpu_T[0], size);
1572 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1573 return 2;
1574 }
1575
1576 static unsigned int dec_mulu_r(DisasContext *dc)
1577 {
1578 int size = memsize_zz(dc);
1579
1580 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1581 memsize_char(size), dc->op1, dc->op2));
1582 cris_cc_mask(dc, CC_MASK_NZV);
1583 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1584 t_gen_zext(cpu_T[0], cpu_T[0], size);
1585 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1586 return 2;
1587 }
1588
1589
1590 static unsigned int dec_dstep_r(DisasContext *dc)
1591 {
1592 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1593 cris_cc_mask(dc, CC_MASK_NZ);
1594 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1595 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1596 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1597 return 2;
1598 }
1599
1600 static unsigned int dec_xor_r(DisasContext *dc)
1601 {
1602 int size = memsize_zz(dc);
1603 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1604 memsize_char(size), dc->op1, dc->op2));
1605 BUG_ON(size != 4); /* xor is dword. */
1606 cris_cc_mask(dc, CC_MASK_NZ);
1607 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1608 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1609 return 2;
1610 }
1611
1612 static unsigned int dec_bound_r(DisasContext *dc)
1613 {
1614 int size = memsize_zz(dc);
1615 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1616 memsize_char(size), dc->op1, dc->op2));
1617 cris_cc_mask(dc, CC_MASK_NZ);
1618 /* TODO: needs optmimization. */
1619 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1620 /* rd should be 4. */
1621 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1622 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1623 return 2;
1624 }
1625
1626 static unsigned int dec_cmp_r(DisasContext *dc)
1627 {
1628 int size = memsize_zz(dc);
1629 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1630 memsize_char(size), dc->op1, dc->op2));
1631 cris_cc_mask(dc, CC_MASK_NZVC);
1632 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1633 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1634 return 2;
1635 }
1636
1637 static unsigned int dec_abs_r(DisasContext *dc)
1638 {
1639 int l1;
1640
1641 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1642 dc->op1, dc->op2));
1643 cris_cc_mask(dc, CC_MASK_NZ);
1644 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1645
1646 /* TODO: consider a branch free approach. */
1647 l1 = gen_new_label();
1648 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1649 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
1650 gen_set_label(l1);
1651 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1652 return 2;
1653 }
1654
1655 static unsigned int dec_add_r(DisasContext *dc)
1656 {
1657 int size = memsize_zz(dc);
1658 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1659 memsize_char(size), dc->op1, dc->op2));
1660 cris_cc_mask(dc, CC_MASK_NZVC);
1661 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1662 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1663 return 2;
1664 }
1665
1666 static unsigned int dec_addc_r(DisasContext *dc)
1667 {
1668 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1669 dc->op1, dc->op2));
1670 cris_evaluate_flags(dc);
1671 cris_cc_mask(dc, CC_MASK_NZVC);
1672 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1673 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1674 return 2;
1675 }
1676
1677 static unsigned int dec_mcp_r(DisasContext *dc)
1678 {
1679 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1680 dc->op2, dc->op1));
1681 cris_evaluate_flags(dc);
1682 cris_cc_mask(dc, CC_MASK_RNZV);
1683 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1684 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1685 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1686 return 2;
1687 }
1688
1689 #if DISAS_CRIS
1690 static char * swapmode_name(int mode, char *modename) {
1691 int i = 0;
1692 if (mode & 8)
1693 modename[i++] = 'n';
1694 if (mode & 4)
1695 modename[i++] = 'w';
1696 if (mode & 2)
1697 modename[i++] = 'b';
1698 if (mode & 1)
1699 modename[i++] = 'r';
1700 modename[i++] = 0;
1701 return modename;
1702 }
1703 #endif
1704
1705 static unsigned int dec_swap_r(DisasContext *dc)
1706 {
1707 DIS(char modename[4]);
1708 DIS(fprintf (logfile, "swap%s $r%u\n",
1709 swapmode_name(dc->op2, modename), dc->op1));
1710
1711 cris_cc_mask(dc, CC_MASK_NZ);
1712 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1713 if (dc->op2 & 8)
1714 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1715 if (dc->op2 & 4)
1716 t_gen_swapw(cpu_T[0], cpu_T[0]);
1717 if (dc->op2 & 2)
1718 t_gen_swapb(cpu_T[0], cpu_T[0]);
1719 if (dc->op2 & 1)
1720 t_gen_swapr(cpu_T[0], cpu_T[0]);
1721 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1722 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1723 return 2;
1724 }
1725
1726 static unsigned int dec_or_r(DisasContext *dc)
1727 {
1728 int size = memsize_zz(dc);
1729 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1730 memsize_char(size), dc->op1, dc->op2));
1731 cris_cc_mask(dc, CC_MASK_NZ);
1732 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1733 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1734 return 2;
1735 }
1736
1737 static unsigned int dec_addi_r(DisasContext *dc)
1738 {
1739 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1740 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1741 cris_cc_mask(dc, 0);
1742 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1743 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1744 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1745 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1746 return 2;
1747 }
1748
1749 static unsigned int dec_addi_acr(DisasContext *dc)
1750 {
1751 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1752 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1753 cris_cc_mask(dc, 0);
1754 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1755 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1756
1757 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1758 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1759 return 2;
1760 }
1761
1762 static unsigned int dec_neg_r(DisasContext *dc)
1763 {
1764 int size = memsize_zz(dc);
1765 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1766 memsize_char(size), dc->op1, dc->op2));
1767 cris_cc_mask(dc, CC_MASK_NZVC);
1768 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1769 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1770 return 2;
1771 }
1772
1773 static unsigned int dec_btst_r(DisasContext *dc)
1774 {
1775 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1776 dc->op1, dc->op2));
1777 cris_cc_mask(dc, CC_MASK_NZ);
1778 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1779 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1780
1781 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1782 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1783 dc->flags_live = 1;
1784 return 2;
1785 }
1786
1787 static unsigned int dec_sub_r(DisasContext *dc)
1788 {
1789 int size = memsize_zz(dc);
1790 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1791 memsize_char(size), dc->op1, dc->op2));
1792 cris_cc_mask(dc, CC_MASK_NZVC);
1793 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1794 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1795 return 2;
1796 }
1797
1798 /* Zero extension. From size to dword. */
1799 static unsigned int dec_movu_r(DisasContext *dc)
1800 {
1801 int size = memsize_z(dc);
1802 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1803 memsize_char(size),
1804 dc->op1, dc->op2));
1805
1806 cris_cc_mask(dc, CC_MASK_NZ);
1807 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1808 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1809 return 2;
1810 }
1811
1812 /* Sign extension. From size to dword. */
1813 static unsigned int dec_movs_r(DisasContext *dc)
1814 {
1815 int size = memsize_z(dc);
1816 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1817 memsize_char(size),
1818 dc->op1, dc->op2));
1819
1820 cris_cc_mask(dc, CC_MASK_NZ);
1821 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1822 /* Size can only be qi or hi. */
1823 t_gen_sext(cpu_T[1], cpu_T[0], size);
1824 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1825 return 2;
1826 }
1827
1828 /* zero extension. From size to dword. */
1829 static unsigned int dec_addu_r(DisasContext *dc)
1830 {
1831 int size = memsize_z(dc);
1832 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1833 memsize_char(size),
1834 dc->op1, dc->op2));
1835
1836 cris_cc_mask(dc, CC_MASK_NZVC);
1837 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1838 /* Size can only be qi or hi. */
1839 t_gen_zext(cpu_T[1], cpu_T[1], size);
1840 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1841 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1842 return 2;
1843 }
1844
1845 /* Sign extension. From size to dword. */
1846 static unsigned int dec_adds_r(DisasContext *dc)
1847 {
1848 int size = memsize_z(dc);
1849 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1850 memsize_char(size),
1851 dc->op1, dc->op2));
1852
1853 cris_cc_mask(dc, CC_MASK_NZVC);
1854 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1855 /* Size can only be qi or hi. */
1856 t_gen_sext(cpu_T[1], cpu_T[1], size);
1857 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1858
1859 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1860 return 2;
1861 }
1862
1863 /* Zero extension. From size to dword. */
1864 static unsigned int dec_subu_r(DisasContext *dc)
1865 {
1866 int size = memsize_z(dc);
1867 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1868 memsize_char(size),
1869 dc->op1, dc->op2));
1870
1871 cris_cc_mask(dc, CC_MASK_NZVC);
1872 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1873 /* Size can only be qi or hi. */
1874 t_gen_zext(cpu_T[1], cpu_T[1], size);
1875 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1876 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1877 return 2;
1878 }
1879
1880 /* Sign extension. From size to dword. */
1881 static unsigned int dec_subs_r(DisasContext *dc)
1882 {
1883 int size = memsize_z(dc);
1884 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1885 memsize_char(size),
1886 dc->op1, dc->op2));
1887
1888 cris_cc_mask(dc, CC_MASK_NZVC);
1889 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1890 /* Size can only be qi or hi. */
1891 t_gen_sext(cpu_T[1], cpu_T[1], size);
1892 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1893 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1894 return 2;
1895 }
1896
1897 static unsigned int dec_setclrf(DisasContext *dc)
1898 {
1899 uint32_t flags;
1900 int set = (~dc->opcode >> 2) & 1;
1901
1902 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1903 | EXTRACT_FIELD(dc->ir, 0, 3);
1904 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1905 if (set && flags == 0)
1906 DIS(fprintf (logfile, "nop\n"));
1907 else if (!set && (flags & 0x20))
1908 DIS(fprintf (logfile, "di\n"));
1909 else
1910 DIS(fprintf (logfile, "%sf %x\n",
1911 set ? "set" : "clr",
1912 flags));
1913
1914 if (set && (flags & X_FLAG)) {
1915 dc->flagx_live = 1;
1916 dc->flags_x = 1;
1917 }
1918
1919 /* Simply decode the flags. */
1920 cris_evaluate_flags (dc);
1921 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1922 tcg_gen_movi_tl(cc_op, dc->cc_op);
1923
1924 if (set) {
1925 if (!dc->user && (flags & U_FLAG)) {
1926 /* Enter user mode. */
1927 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
1928 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
1929 dc->is_jmp = DISAS_UPDATE;
1930 }
1931 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
1932 }
1933 else
1934 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
1935
1936 dc->flags_live = 1;
1937 dc->clear_x = 0;
1938 return 2;
1939 }
1940
1941 static unsigned int dec_move_rs(DisasContext *dc)
1942 {
1943 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1944 cris_cc_mask(dc, 0);
1945 tcg_gen_helper_0_2(helper_movl_sreg_reg,
1946 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
1947 return 2;
1948 }
1949 static unsigned int dec_move_sr(DisasContext *dc)
1950 {
1951 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1952 cris_cc_mask(dc, 0);
1953 tcg_gen_helper_0_2(helper_movl_reg_sreg,
1954 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
1955 return 2;
1956 }
1957
1958 static unsigned int dec_move_rp(DisasContext *dc)
1959 {
1960 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1961 cris_cc_mask(dc, 0);
1962
1963 if (dc->op2 == PR_CCS) {
1964 cris_evaluate_flags(dc);
1965 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1966 if (dc->user) {
1967 /* User space is not allowed to touch all flags. */
1968 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1969 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1970 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1971 }
1972 }
1973 else
1974 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1975
1976 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1977 if (dc->op2 == PR_CCS) {
1978 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1979 dc->flags_live = 1;
1980 }
1981 return 2;
1982 }
1983 static unsigned int dec_move_pr(DisasContext *dc)
1984 {
1985 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1986 cris_cc_mask(dc, 0);
1987 /* Support register 0 is hardwired to zero.
1988 Treat it specially. */
1989 if (dc->op2 == 0)
1990 tcg_gen_movi_tl(cpu_T[1], 0);
1991 else if (dc->op2 == PR_CCS) {
1992 cris_evaluate_flags(dc);
1993 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1994 } else
1995 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1996 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1997 return 2;
1998 }
1999
2000 static unsigned int dec_move_mr(DisasContext *dc)
2001 {
2002 int memsize = memsize_zz(dc);
2003 int insn_len;
2004 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
2005 memsize_char(memsize),
2006 dc->op1, dc->postinc ? "+]" : "]",
2007 dc->op2));
2008
2009 insn_len = dec_prep_alu_m(dc, 0, memsize);
2010 cris_cc_mask(dc, CC_MASK_NZ);
2011 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
2012 do_postinc(dc, memsize);
2013 return insn_len;
2014 }
2015
2016 static unsigned int dec_movs_m(DisasContext *dc)
2017 {
2018 int memsize = memsize_z(dc);
2019 int insn_len;
2020 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2021 memsize_char(memsize),
2022 dc->op1, dc->postinc ? "+]" : "]",
2023 dc->op2));
2024
2025 /* sign extend. */
2026 insn_len = dec_prep_alu_m(dc, 1, memsize);
2027 cris_cc_mask(dc, CC_MASK_NZ);
2028 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2029 do_postinc(dc, memsize);
2030 return insn_len;
2031 }
2032
2033 static unsigned int dec_addu_m(DisasContext *dc)
2034 {
2035 int memsize = memsize_z(dc);
2036 int insn_len;
2037 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2038 memsize_char(memsize),
2039 dc->op1, dc->postinc ? "+]" : "]",
2040 dc->op2));
2041
2042 /* sign extend. */
2043 insn_len = dec_prep_alu_m(dc, 0, memsize);
2044 cris_cc_mask(dc, CC_MASK_NZVC);
2045 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2046 do_postinc(dc, memsize);
2047 return insn_len;
2048 }
2049
2050 static unsigned int dec_adds_m(DisasContext *dc)
2051 {
2052 int memsize = memsize_z(dc);
2053 int insn_len;
2054 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2055 memsize_char(memsize),
2056 dc->op1, dc->postinc ? "+]" : "]",
2057 dc->op2));
2058
2059 /* sign extend. */
2060 insn_len = dec_prep_alu_m(dc, 1, memsize);
2061 cris_cc_mask(dc, CC_MASK_NZVC);
2062 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2063 do_postinc(dc, memsize);
2064 return insn_len;
2065 }
2066
2067 static unsigned int dec_subu_m(DisasContext *dc)
2068 {
2069 int memsize = memsize_z(dc);
2070 int insn_len;
2071 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2072 memsize_char(memsize),
2073 dc->op1, dc->postinc ? "+]" : "]",
2074 dc->op2));
2075
2076 /* sign extend. */
2077 insn_len = dec_prep_alu_m(dc, 0, memsize);
2078 cris_cc_mask(dc, CC_MASK_NZVC);
2079 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2080 do_postinc(dc, memsize);
2081 return insn_len;
2082 }
2083
2084 static unsigned int dec_subs_m(DisasContext *dc)
2085 {
2086 int memsize = memsize_z(dc);
2087 int insn_len;
2088 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2089 memsize_char(memsize),
2090 dc->op1, dc->postinc ? "+]" : "]",
2091 dc->op2));
2092
2093 /* sign extend. */
2094 insn_len = dec_prep_alu_m(dc, 1, memsize);
2095 cris_cc_mask(dc, CC_MASK_NZVC);
2096 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2097 do_postinc(dc, memsize);
2098 return insn_len;
2099 }
2100
2101 static unsigned int dec_movu_m(DisasContext *dc)
2102 {
2103 int memsize = memsize_z(dc);
2104 int insn_len;
2105
2106 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2107 memsize_char(memsize),
2108 dc->op1, dc->postinc ? "+]" : "]",
2109 dc->op2));
2110
2111 insn_len = dec_prep_alu_m(dc, 0, memsize);
2112 cris_cc_mask(dc, CC_MASK_NZ);
2113 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2114 do_postinc(dc, memsize);
2115 return insn_len;
2116 }
2117
2118 static unsigned int dec_cmpu_m(DisasContext *dc)
2119 {
2120 int memsize = memsize_z(dc);
2121 int insn_len;
2122 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2123 memsize_char(memsize),
2124 dc->op1, dc->postinc ? "+]" : "]",
2125 dc->op2));
2126
2127 insn_len = dec_prep_alu_m(dc, 0, memsize);
2128 cris_cc_mask(dc, CC_MASK_NZVC);
2129 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
2130 do_postinc(dc, memsize);
2131 return insn_len;
2132 }
2133
2134 static unsigned int dec_cmps_m(DisasContext *dc)
2135 {
2136 int memsize = memsize_z(dc);
2137 int insn_len;
2138 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2139 memsize_char(memsize),
2140 dc->op1, dc->postinc ? "+]" : "]",
2141 dc->op2));
2142
2143 insn_len = dec_prep_alu_m(dc, 1, memsize);
2144 cris_cc_mask(dc, CC_MASK_NZVC);
2145 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2146 do_postinc(dc, memsize);
2147 return insn_len;
2148 }
2149
2150 static unsigned int dec_cmp_m(DisasContext *dc)
2151 {
2152 int memsize = memsize_zz(dc);
2153 int insn_len;
2154 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2155 memsize_char(memsize),
2156 dc->op1, dc->postinc ? "+]" : "]",
2157 dc->op2));
2158
2159 insn_len = dec_prep_alu_m(dc, 0, memsize);
2160 cris_cc_mask(dc, CC_MASK_NZVC);
2161 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2162 do_postinc(dc, memsize);
2163 return insn_len;
2164 }
2165
2166 static unsigned int dec_test_m(DisasContext *dc)
2167 {
2168 int memsize = memsize_zz(dc);
2169 int insn_len;
2170 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2171 memsize_char(memsize),
2172 dc->op1, dc->postinc ? "+]" : "]",
2173 dc->op2));
2174
2175 cris_evaluate_flags(dc);
2176
2177 insn_len = dec_prep_alu_m(dc, 0, memsize);
2178 cris_cc_mask(dc, CC_MASK_NZ);
2179 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2180
2181 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2182 tcg_gen_movi_tl(cpu_T[1], 0);
2183 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2184 do_postinc(dc, memsize);
2185 return insn_len;
2186 }
2187
2188 static unsigned int dec_and_m(DisasContext *dc)
2189 {
2190 int memsize = memsize_zz(dc);
2191 int insn_len;
2192 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2193 memsize_char(memsize),
2194 dc->op1, dc->postinc ? "+]" : "]",
2195 dc->op2));
2196
2197 insn_len = dec_prep_alu_m(dc, 0, memsize);
2198 cris_cc_mask(dc, CC_MASK_NZ);
2199 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
2200 do_postinc(dc, memsize);
2201 return insn_len;
2202 }
2203
2204 static unsigned int dec_add_m(DisasContext *dc)
2205 {
2206 int memsize = memsize_zz(dc);
2207 int insn_len;
2208 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2209 memsize_char(memsize),
2210 dc->op1, dc->postinc ? "+]" : "]",
2211 dc->op2));
2212
2213 insn_len = dec_prep_alu_m(dc, 0, memsize);
2214 cris_cc_mask(dc, CC_MASK_NZVC);
2215 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
2216 do_postinc(dc, memsize);
2217 return insn_len;
2218 }
2219
2220 static unsigned int dec_addo_m(DisasContext *dc)
2221 {
2222 int memsize = memsize_zz(dc);
2223 int insn_len;
2224 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2225 memsize_char(memsize),
2226 dc->op1, dc->postinc ? "+]" : "]",
2227 dc->op2));
2228
2229 insn_len = dec_prep_alu_m(dc, 1, memsize);
2230 cris_cc_mask(dc, 0);
2231 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
2232 do_postinc(dc, memsize);
2233 return insn_len;
2234 }
2235
2236 static unsigned int dec_bound_m(DisasContext *dc)
2237 {
2238 int memsize = memsize_zz(dc);
2239 int insn_len;
2240 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2241 memsize_char(memsize),
2242 dc->op1, dc->postinc ? "+]" : "]",
2243 dc->op2));
2244
2245 insn_len = dec_prep_alu_m(dc, 0, memsize);
2246 cris_cc_mask(dc, CC_MASK_NZ);
2247 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
2248 do_postinc(dc, memsize);
2249 return insn_len;
2250 }
2251
2252 static unsigned int dec_addc_mr(DisasContext *dc)
2253 {
2254 int insn_len = 2;
2255 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2256 dc->op1, dc->postinc ? "+]" : "]",
2257 dc->op2));
2258
2259 cris_evaluate_flags(dc);
2260 insn_len = dec_prep_alu_m(dc, 0, 4);
2261 cris_cc_mask(dc, CC_MASK_NZVC);
2262 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2263 do_postinc(dc, 4);
2264 return insn_len;
2265 }
2266
2267 static unsigned int dec_sub_m(DisasContext *dc)
2268 {
2269 int memsize = memsize_zz(dc);
2270 int insn_len;
2271 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2272 memsize_char(memsize),
2273 dc->op1, dc->postinc ? "+]" : "]",
2274 dc->op2, dc->ir, dc->zzsize));
2275
2276 insn_len = dec_prep_alu_m(dc, 0, memsize);
2277 cris_cc_mask(dc, CC_MASK_NZVC);
2278 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2279 do_postinc(dc, memsize);
2280 return insn_len;
2281 }
2282
2283 static unsigned int dec_or_m(DisasContext *dc)
2284 {
2285 int memsize = memsize_zz(dc);
2286 int insn_len;
2287 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2288 memsize_char(memsize),
2289 dc->op1, dc->postinc ? "+]" : "]",
2290 dc->op2, dc->pc));
2291
2292 insn_len = dec_prep_alu_m(dc, 0, memsize);
2293 cris_cc_mask(dc, CC_MASK_NZ);
2294 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2295 do_postinc(dc, memsize);
2296 return insn_len;
2297 }
2298
2299 static unsigned int dec_move_mp(DisasContext *dc)
2300 {
2301 int memsize = memsize_zz(dc);
2302 int insn_len = 2;
2303
2304 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2305 memsize_char(memsize),
2306 dc->op1,
2307 dc->postinc ? "+]" : "]",
2308 dc->op2));
2309
2310 insn_len = dec_prep_alu_m(dc, 0, memsize);
2311 cris_cc_mask(dc, 0);
2312 if (dc->op2 == PR_CCS) {
2313 cris_evaluate_flags(dc);
2314 if (dc->user) {
2315 /* User space is not allowed to touch all flags. */
2316 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2317 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2318 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2319 }
2320 }
2321
2322 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
2323
2324 do_postinc(dc, memsize);
2325 return insn_len;
2326 }
2327
2328 static unsigned int dec_move_pm(DisasContext *dc)
2329 {
2330 int memsize;
2331
2332 memsize = preg_sizes[dc->op2];
2333
2334 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2335 memsize_char(memsize),
2336 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2337
2338 /* prepare store. Address in T0, value in T1. */
2339 if (dc->op2 == PR_CCS)
2340 cris_evaluate_flags(dc);
2341 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2342
2343 /* FIXME: qemu_st does not act as a barrier? */
2344 tcg_gen_helper_0_0(helper_dummy);
2345 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2346
2347 cris_cc_mask(dc, 0);
2348 if (dc->postinc)
2349 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2350 return 2;
2351 }
2352
2353 static unsigned int dec_movem_mr(DisasContext *dc)
2354 {
2355 TCGv tmp[16];
2356 int i;
2357
2358 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2359 dc->postinc ? "+]" : "]", dc->op2));
2360
2361 /* FIXME: qemu_ld does not act as a barrier? */
2362 tcg_gen_helper_0_0(helper_dummy);
2363
2364 /* fetch the address into T0 and T1. */
2365 for (i = 0; i <= dc->op2; i++) {
2366 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
2367 /* Perform the load onto regnum i. Always dword wide. */
2368 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2369 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2370 }
2371
2372 for (i = 0; i <= dc->op2; i++) {
2373 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2374 tcg_gen_discard_tl(tmp[i]);
2375 }
2376
2377 /* writeback the updated pointer value. */
2378 if (dc->postinc)
2379 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2380
2381 /* gen_load might want to evaluate the previous insns flags. */
2382 cris_cc_mask(dc, 0);
2383 return 2;
2384 }
2385
2386 static unsigned int dec_movem_rm(DisasContext *dc)
2387 {
2388 int i;
2389
2390 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2391 dc->postinc ? "+]" : "]"));
2392
2393 /* FIXME: qemu_st does not act as a barrier? */
2394 tcg_gen_helper_0_0(helper_dummy);
2395
2396 for (i = 0; i <= dc->op2; i++) {
2397 /* Displace addr. */
2398 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2399 /* Perform the store. */
2400 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2401 }
2402 if (dc->postinc)
2403 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2404 cris_cc_mask(dc, 0);
2405 return 2;
2406 }
2407
2408 static unsigned int dec_move_rm(DisasContext *dc)
2409 {
2410 int memsize;
2411
2412 memsize = memsize_zz(dc);
2413
2414 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2415 memsize, dc->op2, dc->op1));
2416
2417 /* prepare store. */
2418 /* FIXME: qemu_st does not act as a barrier? */
2419 tcg_gen_helper_0_0(helper_dummy);
2420 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2421
2422 if (dc->postinc)
2423 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2424 cris_cc_mask(dc, 0);
2425 return 2;
2426 }
2427
2428 static unsigned int dec_lapcq(DisasContext *dc)
2429 {
2430 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2431 dc->pc + dc->op1*2, dc->op2));
2432 cris_cc_mask(dc, 0);
2433 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2434 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2435 return 2;
2436 }
2437
2438 static unsigned int dec_lapc_im(DisasContext *dc)
2439 {
2440 unsigned int rd;
2441 int32_t imm;
2442 int32_t pc;
2443
2444 rd = dc->op2;
2445
2446 cris_cc_mask(dc, 0);
2447 imm = ldl_code(dc->pc + 2);
2448 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2449
2450 pc = dc->pc;
2451 pc += imm;
2452 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2453 return 6;
2454 }
2455
2456 /* Jump to special reg. */
2457 static unsigned int dec_jump_p(DisasContext *dc)
2458 {
2459 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2460
2461 if (dc->op2 == PR_CCS)
2462 cris_evaluate_flags(dc);
2463 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2464 /* rete will often have low bit set to indicate delayslot. */
2465 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2466 cris_cc_mask(dc, 0);
2467 cris_prepare_dyn_jmp(dc);
2468 return 2;
2469 }
2470
2471 /* Jump and save. */
2472 static unsigned int dec_jas_r(DisasContext *dc)
2473 {
2474 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2475 cris_cc_mask(dc, 0);
2476 /* Store the return address in Pd. */
2477 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2478 if (dc->op2 > 15)
2479 abort();
2480 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
2481 tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
2482
2483 cris_prepare_dyn_jmp(dc);
2484 return 2;
2485 }
2486
2487 static unsigned int dec_jas_im(DisasContext *dc)
2488 {
2489 uint32_t imm;
2490
2491 imm = ldl_code(dc->pc + 2);
2492
2493 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2494 cris_cc_mask(dc, 0);
2495 /* Store the return address in Pd. */
2496 tcg_gen_movi_tl(env_btarget, imm);
2497 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
2498 cris_prepare_dyn_jmp(dc);
2499 return 6;
2500 }
2501
2502 static unsigned int dec_jasc_im(DisasContext *dc)
2503 {
2504 uint32_t imm;
2505
2506 imm = ldl_code(dc->pc + 2);
2507
2508 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2509 cris_cc_mask(dc, 0);
2510 /* Store the return address in Pd. */
2511 tcg_gen_movi_tl(cpu_T[0], imm);
2512 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2513 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2514 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2515 cris_prepare_dyn_jmp(dc);
2516 return 6;
2517 }
2518
2519 static unsigned int dec_jasc_r(DisasContext *dc)
2520 {
2521 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2522 cris_cc_mask(dc, 0);
2523 /* Store the return address in Pd. */
2524 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2525 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2526 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2527 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2528 cris_prepare_dyn_jmp(dc);
2529 return 2;
2530 }
2531
2532 static unsigned int dec_bcc_im(DisasContext *dc)
2533 {
2534 int32_t offset;
2535 uint32_t cond = dc->op2;
2536
2537 offset = ldsw_code(dc->pc + 2);
2538
2539 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2540 cc_name(cond), offset,
2541 dc->pc, dc->pc + offset));
2542
2543 cris_cc_mask(dc, 0);
2544 /* op2 holds the condition-code. */
2545 cris_prepare_cc_branch (dc, offset, cond);
2546 return 4;
2547 }
2548
2549 static unsigned int dec_bas_im(DisasContext *dc)
2550 {
2551 int32_t simm;
2552
2553
2554 simm = ldl_code(dc->pc + 2);
2555
2556 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2557 cris_cc_mask(dc, 0);
2558 /* Stor the return address in Pd. */
2559 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2560 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2561 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2562 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2563 cris_prepare_dyn_jmp(dc);
2564 return 6;
2565 }
2566
2567 static unsigned int dec_basc_im(DisasContext *dc)
2568 {
2569 int32_t simm;
2570 simm = ldl_code(dc->pc + 2);
2571
2572 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2573 cris_cc_mask(dc, 0);
2574 /* Stor the return address in Pd. */
2575 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2576 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2577 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2578 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2579 cris_prepare_dyn_jmp(dc);
2580 return 6;
2581 }
2582
2583 static unsigned int dec_rfe_etc(DisasContext *dc)
2584 {
2585 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2586 dc->opcode, dc->pc, dc->op1, dc->op2));
2587
2588 cris_cc_mask(dc, 0);
2589
2590 if (dc->op2 == 15) /* ignore halt. */
2591 return 2;
2592
2593 switch (dc->op2 & 7) {
2594 case 2:
2595 /* rfe. */
2596 cris_evaluate_flags(dc);
2597 tcg_gen_helper_0_0(helper_rfe);
2598 dc->is_jmp = DISAS_UPDATE;
2599 break;
2600 case 5:
2601 /* rfn. */
2602 BUG();
2603 break;
2604 case 6:
2605 /* break. */
2606 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2607 t_gen_mov_env_TN(pc, cpu_T[0]);
2608 /* Breaks start at 16 in the exception vector. */
2609 t_gen_mov_env_TN(trap_vector,
2610 tcg_const_tl(dc->op1 + 16));
2611 t_gen_raise_exception(EXCP_BREAK);
2612 dc->is_jmp = DISAS_UPDATE;
2613 break;
2614 default:
2615 printf ("op2=%x\n", dc->op2);
2616 BUG();
2617 break;
2618
2619 }
2620 return 2;
2621 }
2622
2623 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2624 {
2625 /* Ignore D-cache flushes. */
2626 return 2;
2627 }
2628
2629 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2630 {
2631 /* Ignore I-cache flushes. */
2632 return 2;
2633 }
2634
2635 static unsigned int dec_null(DisasContext *dc)
2636 {
2637 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2638 dc->pc, dc->opcode, dc->op1, dc->op2);
2639 fflush(NULL);
2640 BUG();
2641 return 2;
2642 }
2643
2644 struct decoder_info {
2645 struct {
2646 uint32_t bits;
2647 uint32_t mask;
2648 };
2649 unsigned int (*dec)(DisasContext *dc);
2650 } decinfo[] = {
2651 /* Order matters here. */
2652 {DEC_MOVEQ, dec_moveq},
2653 {DEC_BTSTQ, dec_btstq},
2654 {DEC_CMPQ, dec_cmpq},
2655 {DEC_ADDOQ, dec_addoq},
2656 {DEC_ADDQ, dec_addq},
2657 {DEC_SUBQ, dec_subq},
2658 {DEC_ANDQ, dec_andq},
2659 {DEC_ORQ, dec_orq},
2660 {DEC_ASRQ, dec_asrq},
2661 {DEC_LSLQ, dec_lslq},
2662 {DEC_LSRQ, dec_lsrq},
2663 {DEC_BCCQ, dec_bccq},
2664
2665 {DEC_BCC_IM, dec_bcc_im},
2666 {DEC_JAS_IM, dec_jas_im},
2667 {DEC_JAS_R, dec_jas_r},
2668 {DEC_JASC_IM, dec_jasc_im},
2669 {DEC_JASC_R, dec_jasc_r},
2670 {DEC_BAS_IM, dec_bas_im},
2671 {DEC_BASC_IM, dec_basc_im},
2672 {DEC_JUMP_P, dec_jump_p},
2673 {DEC_LAPC_IM, dec_lapc_im},
2674 {DEC_LAPCQ, dec_lapcq},
2675
2676 {DEC_RFE_ETC, dec_rfe_etc},
2677 {DEC_ADDC_MR, dec_addc_mr},
2678
2679 {DEC_MOVE_MP, dec_move_mp},
2680 {DEC_MOVE_PM, dec_move_pm},
2681 {DEC_MOVEM_MR, dec_movem_mr},
2682 {DEC_MOVEM_RM, dec_movem_rm},
2683 {DEC_MOVE_PR, dec_move_pr},
2684 {DEC_SCC_R, dec_scc_r},
2685 {DEC_SETF, dec_setclrf},
2686 {DEC_CLEARF, dec_setclrf},
2687
2688 {DEC_MOVE_SR, dec_move_sr},
2689 {DEC_MOVE_RP, dec_move_rp},
2690 {DEC_SWAP_R, dec_swap_r},
2691 {DEC_ABS_R, dec_abs_r},
2692 {DEC_LZ_R, dec_lz_r},
2693 {DEC_MOVE_RS, dec_move_rs},
2694 {DEC_BTST_R, dec_btst_r},
2695 {DEC_ADDC_R, dec_addc_r},
2696
2697 {DEC_DSTEP_R, dec_dstep_r},
2698 {DEC_XOR_R, dec_xor_r},
2699 {DEC_MCP_R, dec_mcp_r},
2700 {DEC_CMP_R, dec_cmp_r},
2701
2702 {DEC_ADDI_R, dec_addi_r},
2703 {DEC_ADDI_ACR, dec_addi_acr},
2704
2705 {DEC_ADD_R, dec_add_r},
2706 {DEC_SUB_R, dec_sub_r},
2707
2708 {DEC_ADDU_R, dec_addu_r},
2709 {DEC_ADDS_R, dec_adds_r},
2710 {DEC_SUBU_R, dec_subu_r},
2711 {DEC_SUBS_R, dec_subs_r},
2712 {DEC_LSL_R, dec_lsl_r},
2713
2714 {DEC_AND_R, dec_and_r},
2715 {DEC_OR_R, dec_or_r},
2716 {DEC_BOUND_R, dec_bound_r},
2717 {DEC_ASR_R, dec_asr_r},
2718 {DEC_LSR_R, dec_lsr_r},
2719
2720 {DEC_MOVU_R, dec_movu_r},
2721 {DEC_MOVS_R, dec_movs_r},
2722 {DEC_NEG_R, dec_neg_r},
2723 {DEC_MOVE_R, dec_move_r},
2724
2725 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2726 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2727
2728 {DEC_MULS_R, dec_muls_r},
2729 {DEC_MULU_R, dec_mulu_r},
2730
2731 {DEC_ADDU_M, dec_addu_m},
2732 {DEC_ADDS_M, dec_adds_m},
2733 {DEC_SUBU_M, dec_subu_m},
2734 {DEC_SUBS_M, dec_subs_m},
2735
2736 {DEC_CMPU_M, dec_cmpu_m},
2737 {DEC_CMPS_M, dec_cmps_m},
2738 {DEC_MOVU_M, dec_movu_m},
2739 {DEC_MOVS_M, dec_movs_m},
2740
2741 {DEC_CMP_M, dec_cmp_m},
2742 {DEC_ADDO_M, dec_addo_m},
2743 {DEC_BOUND_M, dec_bound_m},
2744 {DEC_ADD_M, dec_add_m},
2745 {DEC_SUB_M, dec_sub_m},
2746 {DEC_AND_M, dec_and_m},
2747 {DEC_OR_M, dec_or_m},
2748 {DEC_MOVE_RM, dec_move_rm},
2749 {DEC_TEST_M, dec_test_m},
2750 {DEC_MOVE_MR, dec_move_mr},
2751
2752 {{0, 0}, dec_null}
2753 };
2754
2755 static inline unsigned int
2756 cris_decoder(DisasContext *dc)
2757 {
2758 unsigned int insn_len = 2;
2759 int i;
2760
2761 /* Load a halfword onto the instruction register. */
2762 dc->ir = lduw_code(dc->pc);
2763
2764 /* Now decode it. */
2765 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2766 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2767 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2768 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2769 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2770 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2771
2772 /* Large switch for all insns. */
2773 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2774 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2775 {
2776 insn_len = decinfo[i].dec(dc);
2777 break;
2778 }
2779 }
2780
2781 return insn_len;
2782 }
2783
2784 static void check_breakpoint(CPUState *env, DisasContext *dc)
2785 {
2786 int j;
2787 if (env->nb_breakpoints > 0) {
2788 for(j = 0; j < env->nb_breakpoints; j++) {
2789 if (env->breakpoints[j] == dc->pc) {
2790 cris_evaluate_flags (dc);
2791 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2792 t_gen_mov_env_TN(pc, cpu_T[0]);
2793 t_gen_raise_exception(EXCP_DEBUG);
2794 dc->is_jmp = DISAS_UPDATE;
2795 }
2796 }
2797 }
2798 }
2799
2800 /* generate intermediate code for basic block 'tb'. */
2801 struct DisasContext ctx;
2802 static int
2803 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2804 int search_pc)
2805 {
2806 uint16_t *gen_opc_end;
2807 uint32_t pc_start;
2808 unsigned int insn_len;
2809 int j, lj;
2810 struct DisasContext *dc = &ctx;
2811 uint32_t next_page_start;
2812
2813 if (!logfile)
2814 logfile = stderr;
2815
2816 /* Odd PC indicates that branch is rexecuting due to exception in the
2817 * delayslot, like in real hw.
2818 * FIXME: we need to handle the case were the branch and the insn in
2819 * the delayslot do not share pages.
2820 */
2821 pc_start = tb->pc & ~1;
2822 dc->env = env;
2823 dc->tb = tb;
2824
2825 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2826
2827 dc->is_jmp = DISAS_NEXT;
2828 dc->ppc = pc_start;
2829 dc->pc = pc_start;
2830 dc->singlestep_enabled = env->singlestep_enabled;
2831 dc->flags_live = 1;
2832 dc->flagx_live = 0;
2833 dc->flags_x = 0;
2834 dc->cc_mask = 0;
2835 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2836
2837 dc->user = env->pregs[PR_CCS] & U_FLAG;
2838 dc->delayed_branch = 0;
2839
2840 if (loglevel & CPU_LOG_TB_IN_ASM) {
2841 fprintf(logfile,
2842 "search=%d pc=%x ccs=%x pid=%x usp=%x dbg=%x %x %x\n"
2843 "%x.%x.%x.%x\n"
2844 "%x.%x.%x.%x\n"
2845 "%x.%x.%x.%x\n"
2846 "%x.%x.%x.%x\n",
2847 search_pc, env->pc, env->pregs[PR_CCS],
2848 env->pregs[PR_PID], env->pregs[PR_USP],
2849 env->debug1, env->debug2, env->debug3,
2850 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2851 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2852 env->regs[8], env->regs[9],
2853 env->regs[10], env->regs[11],
2854 env->regs[12], env->regs[13],
2855 env->regs[14], env->regs[15]);
2856
2857 }
2858
2859 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2860 lj = -1;
2861 do
2862 {
2863 check_breakpoint(env, dc);
2864 if (dc->is_jmp == DISAS_JUMP
2865 || dc->is_jmp == DISAS_SWI)
2866 goto done;
2867
2868 if (search_pc) {
2869 j = gen_opc_ptr - gen_opc_buf;
2870 if (lj < j) {
2871 lj++;
2872 while (lj < j)
2873 gen_opc_instr_start[lj++] = 0;
2874 }
2875 if (dc->delayed_branch == 1) {
2876 gen_opc_pc[lj] = dc->ppc | 1;
2877 gen_opc_instr_start[lj] = 0;
2878 }
2879 else {
2880 gen_opc_pc[lj] = dc->pc;
2881 gen_opc_instr_start[lj] = 1;
2882 }
2883 }
2884
2885 dc->clear_x = 1;
2886 insn_len = cris_decoder(dc);
2887 dc->ppc = dc->pc;
2888 dc->pc += insn_len;
2889 if (dc->clear_x)
2890 cris_clear_x_flag(dc);
2891
2892 /* Check for delayed branches here. If we do it before
2893 actually genereating any host code, the simulator will just
2894 loop doing nothing for on this program location. */
2895 if (dc->delayed_branch) {
2896 dc->delayed_branch--;
2897 if (dc->delayed_branch == 0)
2898 {
2899 if (dc->bcc == CC_A) {
2900 tcg_gen_mov_tl(env_pc, env_btarget);
2901 dc->is_jmp = DISAS_JUMP;
2902 }
2903 else {
2904 t_gen_cc_jmp(dc->delayed_pc, dc->pc);
2905 dc->is_jmp = DISAS_JUMP;
2906 }
2907 }
2908 }
2909
2910 /* If we are rexecuting a branch due to exceptions on
2911 delay slots dont break. */
2912 if (!(tb->pc & 1) && env->singlestep_enabled)
2913 break;
2914 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2915 && ((dc->pc < next_page_start) || dc->delayed_branch));
2916
2917 if (dc->delayed_branch == 1) {
2918 /* Reexecute the last insn. */
2919 dc->pc = dc->ppc | 1;
2920 }
2921
2922 if (!dc->is_jmp) {
2923 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2924 dc->is_jmp, dc->delayed_branch));
2925 /* T0 and env_pc should hold the new pc. */
2926 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2927 tcg_gen_mov_tl(env_pc, cpu_T[0]);
2928 }
2929
2930 cris_evaluate_flags (dc);
2931 done:
2932 if (__builtin_expect(env->singlestep_enabled, 0)) {
2933 t_gen_raise_exception(EXCP_DEBUG);
2934 } else {
2935 switch(dc->is_jmp) {
2936 case DISAS_NEXT:
2937 gen_goto_tb(dc, 1, dc->pc);
2938 break;
2939 default:
2940 case DISAS_JUMP:
2941 case DISAS_UPDATE:
2942 /* indicate that the hash table must be used
2943 to find the next TB */
2944 tcg_gen_exit_tb(0);
2945 break;
2946 case DISAS_SWI:
2947 case DISAS_TB_JUMP:
2948 /* nothing more to generate */
2949 break;
2950 }
2951 }
2952 *gen_opc_ptr = INDEX_op_end;
2953 if (search_pc) {
2954 j = gen_opc_ptr - gen_opc_buf;
2955 lj++;
2956 while (lj <= j)
2957 gen_opc_instr_start[lj++] = 0;
2958 } else {
2959 tb->size = dc->pc - pc_start;
2960 }
2961
2962 #ifdef DEBUG_DISAS
2963 if (loglevel & CPU_LOG_TB_IN_ASM) {
2964 fprintf(logfile, "--------------\n");
2965 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2966 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
2967 fprintf(logfile, "\nisize=%d osize=%d\n",
2968 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
2969 }
2970 #endif
2971 return 0;
2972 }
2973
2974 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2975 {
2976 return gen_intermediate_code_internal(env, tb, 0);
2977 }
2978
2979 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2980 {
2981 return gen_intermediate_code_internal(env, tb, 1);
2982 }
2983
2984 void cpu_dump_state (CPUState *env, FILE *f,
2985 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2986 int flags)
2987 {
2988 int i;
2989 uint32_t srs;
2990
2991 if (!env || !f)
2992 return;
2993
2994 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2995 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2996 "debug=%x %x %x\n",
2997 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2998 env->cc_op,
2999 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
3000 env->debug1, env->debug2, env->debug3);
3001
3002 for (i = 0; i < 16; i++) {
3003 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3004 if ((i + 1) % 4 == 0)
3005 cpu_fprintf(f, "\n");
3006 }
3007 cpu_fprintf(f, "\nspecial regs:\n");
3008 for (i = 0; i < 16; i++) {
3009 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3010 if ((i + 1) % 4 == 0)
3011 cpu_fprintf(f, "\n");
3012 }
3013 srs = env->pregs[PR_SRS];
3014 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3015 if (srs < 256) {
3016 for (i = 0; i < 16; i++) {
3017 cpu_fprintf(f, "s%2.2d=%8.8x ",
3018 i, env->sregs[srs][i]);
3019 if ((i + 1) % 4 == 0)
3020 cpu_fprintf(f, "\n");
3021 }
3022 }
3023 cpu_fprintf(f, "\n\n");
3024
3025 }
3026
3027 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
3028 {
3029 }
3030
3031 CPUCRISState *cpu_cris_init (const char *cpu_model)
3032 {
3033 CPUCRISState *env;
3034 int i;
3035
3036 env = qemu_mallocz(sizeof(CPUCRISState));
3037 if (!env)
3038 return NULL;
3039 cpu_exec_init(env);
3040
3041 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
3042 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3043 #if TARGET_LONG_BITS > HOST_LONG_BITS
3044 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3045 TCG_AREG0, offsetof(CPUState, t0), "T0");
3046 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3047 TCG_AREG0, offsetof(CPUState, t1), "T1");
3048 #else
3049 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3050 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3051 #endif
3052
3053 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3054 offsetof(CPUState, cc_src), "cc_src");
3055 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3056 offsetof(CPUState, cc_dest),
3057 "cc_dest");
3058 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3059 offsetof(CPUState, cc_result),
3060 "cc_result");
3061 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3062 offsetof(CPUState, cc_op), "cc_op");
3063 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3064 offsetof(CPUState, cc_size),
3065 "cc_size");
3066 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3067 offsetof(CPUState, cc_mask),
3068 "cc_mask");
3069
3070 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3071 offsetof(CPUState, pc),
3072 "pc");
3073 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3074 offsetof(CPUState, btarget),
3075 "btarget");
3076
3077 for (i = 0; i < 16; i++) {
3078 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3079 offsetof(CPUState, regs[i]),
3080 regnames[i]);
3081 }
3082 for (i = 0; i < 16; i++) {
3083 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3084 offsetof(CPUState, pregs[i]),
3085 pregnames[i]);
3086 }
3087
3088 TCG_HELPER(helper_raise_exception);
3089 TCG_HELPER(helper_store);
3090 TCG_HELPER(helper_dump);
3091 TCG_HELPER(helper_dummy);
3092
3093 TCG_HELPER(helper_tlb_flush);
3094 TCG_HELPER(helper_movl_sreg_reg);
3095 TCG_HELPER(helper_movl_reg_sreg);
3096 TCG_HELPER(helper_rfe);
3097
3098 TCG_HELPER(helper_evaluate_flags_muls);
3099 TCG_HELPER(helper_evaluate_flags_mulu);
3100 TCG_HELPER(helper_evaluate_flags_mcp);
3101 TCG_HELPER(helper_evaluate_flags_alu_4);
3102 TCG_HELPER(helper_evaluate_flags_move_4);
3103 TCG_HELPER(helper_evaluate_flags_move_2);
3104 TCG_HELPER(helper_evaluate_flags);
3105
3106 cpu_reset(env);
3107 return env;
3108 }
3109
3110 void cpu_reset (CPUCRISState *env)
3111 {
3112 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3113 tlb_flush(env, 1);
3114
3115 #if defined(CONFIG_USER_ONLY)
3116 /* start in user mode with interrupts enabled. */
3117 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3118 #else
3119 env->pregs[PR_CCS] = 0;
3120 #endif
3121 }
3122
3123 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3124 unsigned long searched_pc, int pc_pos, void *puc)
3125 {
3126 env->pc = gen_opc_pc[pc_pos];
3127 }
HPPA (PA-RISC) target for QEMU